CN105428419B - 一种电阻栅薄膜晶体管及其制备方法 - Google Patents
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Abstract
本发明公开了一种电阻栅薄膜晶体管及其制备方法。电阻栅薄膜晶体管包括衬底、过渡层、栅端电极、电阻栅薄膜层、绝缘栅介质层、半导体有源层、源漏电极；所述电阻栅薄膜层位于栅端电极与绝缘栅介质层之间；所述栅端电极位于电阻栅薄膜层下方；所述源漏极在半导体有源层上，且源漏电极两端与两个栅端电极存在交叠区域。本发明可通过两个栅端电极偏压有效调控器件处于不截止、遥截止或锐截止转移特性,可根据实际应用需要获得所需的阈值电压、关态电流和跨导值，两个栅端电极可同时作为控制栅和信号栅使用，使电路得到简化，从而有效扩大了薄膜晶体管的应用范围，能有效地解决阈值电压漂移、大信号堵塞、自动增益控制动态范围窄等问题。
Description
技术领域
本发明涉及半导体技术领域，特别涉及一种电阻栅薄膜晶体管结构及其制备方法。
背景技术
近年来，供平板显示器件和其它图像显示器用的薄膜晶体管（TFT）方面的研究与开发极为活跃。用于有源矩阵LCD和其它显示器件的TFT需要具有高迁移率、低关态电流、高开关电流比、低阈值电压等特性，且电性能需要具有偏压应力稳定性和工作环境稳定性。本世纪以来，随着平板显示技术的快速发展，对TFT器件性能提出了更高要求。多年来，围绕器件性能的改进，已开发出多种可用于TFT的半导体薄膜材料，主要包括非晶硅、多晶硅、以并五苯为代表的有机小分子半导体材料、以聚噻吩类为代表的有机聚合物半导体材料、以氧化锌为代表的宽能隙氧化物半导体材料等。非晶硅TFT由于低迁移率在高分辨率显示方面受到限制。多晶硅TFT虽具有较高的迁移率，但具有工艺复杂、制作成本昂贵、大面积难以实现等缺点而制约其市场空间。更重要的是，硅为窄能隙半导体，硅基TFT对可见光敏感，光照条件下器件性能发生明显的变化，因此，在平板显示中需要引入黑矩阵，这不仅增加了制备工艺的复杂度，而且降低了显示器件的开口率。有机TFT尽管在低成本、柔性化方面有优势，但低迁移率和性能不稳定等难以解决的关键技术问题影响其应用前景。相对而言，采用以氧化锌材料为代表的宽能隙透明氧化物半导体材料作为TFT的有源层是目前有效解决TFT器件中迁移率、大面积、黑矩阵、开口率、亮度等问题最佳方案。比如，氧化锌基薄膜晶体管具有相对高的迁移率、低功耗、环境友好、可见光透明、低温工艺等诸多优势，在透明电子器件、液晶显示、太阳能电池、触摸屏、柔性显示、电子纸、集成电路等诸多领域具有广阔的应用前景，被认为是最有希望的下一代薄膜晶体管技术。
薄膜晶体管的电性能由材料参数、器件结构和工艺参数共同决定，强烈地依赖于栅极、栅介质、半导体有源层和源漏电极的材料特性和制备工艺，以及它们之间的界面特性。近年来，为了改善TFT器件的电性能及其稳定性，在材料选择、工艺和界面优化等方面进行了大量的研究工作，使TFT器件的迁移率、开关电流比、关态电流、亚阈值摆幅等参数得到明显提高。现有的TFT器件的电特性往往不能根据实际应用的需要进行合理调控，而且普遍存在工作电压所引起的阈值电压漂移、关态电流增加和迁移率退化等现象，从而影响电子系统的稳定性和可靠性。
发明内容
为了克服现有技术的上述缺点与不足，本发明的目的在于提供一种电阻栅薄膜晶体管，可通过电阻栅上的两个端电极偏压有效调控器件处于不截止、遥截止或锐截止转移特性, 可根据实际应用需要获得所需的阈值电压、关态电流和跨导值, 两个栅端可同时作为控制栅和信号栅使用，使电路得到简化，从而有效扩大了薄膜晶体管的应用范围，能有效地解决阈值电压漂移、大信号堵塞、自动增益控制动态范围窄等问题。
本发明的另一目的在于提供上述电阻栅薄膜晶体管的制备方法。
本发明的目的通过以下技术方案实现。
一种电阻栅薄膜晶体管，由下至上依次衬底、过渡层、栅端电极、电阻栅薄膜层、绝缘栅介质层、半导体有源层和源漏电极；所述电阻栅薄膜层的电阻率低于半导体有源层，位于栅端电极与绝缘栅介质层之间；所述栅端电极位于电阻栅薄膜层下方，其连线方向与沟道方向垂直，其结构和功能上是等效的；所述源漏极在半导体有源层上，电极长度（沟道宽度）小于两栅端电极宽度与其间距的总和，且源漏电极两端与两个栅端电极存在交叠区域（类#型）。
进一步优化地，所述半导体有源层可为厚度30～80纳米的非晶硅、多晶硅、有机和氧化物半导体薄膜中的一种。
进一步优化地，所述电阻栅薄膜层的电阻率低于半导体有源层。
进一步优化地，所述栅端电极与电阻栅薄膜层之间，源漏电电极与半导体有源层之间形成欧姆接触。-
进一步优化地，所述绝缘栅介质层为100～300纳米厚的二氧化硅、氧化铝或氧化钽绝缘介质材料中的一 种，但不限于此。
进一步优化地，所述衬底为玻璃衬底或者塑料衬底。
上述电阻栅薄膜晶体管的制备方法，包括以下步骤：
（1）在衬底上沉积100～200纳米厚的二氧化硅薄膜作为过渡层；
（2）在经步骤（1）处理后的过渡层上沉积金属（或ITO）导电薄膜，光刻形成两栅端电极；
（3）在经步骤（2）处理后的两栅端电极和过渡层上通过掩膜版技术沉积100～200纳米厚的电阻型薄膜，形成电阻栅薄膜层；
（4）在电阻栅薄膜层上通过掩膜版技术沉积100～300纳米厚的绝缘薄膜形成绝缘栅介质层；
（5）在经步骤（4）处理后的绝缘栅介质层上沉积半导体薄膜，形成半导体有源层；
（6）在半导体有源层上沉积100～200纳米厚的金属薄膜，光刻形成源、漏电极；
（7）在经（6）处理后的器件在200～250 oC氮氛下退火处理30～60分钟。
与现有技术相比，本发明具有以下优点和有益效果：
本发明采用电阻型薄膜作为栅，通过调整垂直沟道方向的两个栅端电极的偏压可使晶体管工作于不同的状态，呈现不截止、遥截止或锐截止的转移特性, 可根据实际应用需要获得所需的阈值电压、关态电流和跨导值, 两个栅端可同时作为控制栅和信号栅使用，使电路得到简化，从而有效扩大了薄膜晶体管的应用范围，能有效地解决阈值电压漂移、大信号堵塞、自动增益控制动态范围窄等问题。
附图说明
图1为本发明的实施例的电阻栅薄膜晶体管的结构示意图。
图2a～图2f分别为实例中电阻栅薄膜晶体管的一个制作过程不同步骤对应的示意图。
图3a和图3b分别为电阻栅薄膜晶体管的一个应用实例电路的示意图和对应的栅端电极偏压控制转移特性的验证曲线。
具体实施方式
下面结合实施例，对本发明作进一步地详细说明，但本发明的实施方式不限于此。
实施例
本实施例的双有源层结构氧化锌基薄膜晶体管，由下至上依次包括衬底1、过渡层2、两栅端电极（301,302）、电阻栅薄膜层4、绝缘栅介质层5、半导体有源层6、源电极701和漏电极702，所述电阻栅薄膜层的电阻率低于半导体有源层，位于栅端电极与绝缘栅介质层之间；所述栅端电极位于电阻栅薄膜层下方，其连线方向与沟道方向垂直，其结构和功能上是等效的；所述源漏极在半导体有源层上，电极长度（沟道宽度）小于两栅端电极宽度与其间距的总和，且源漏电极两端与两个栅端电极存在交叠区域。
本实施例的衬底可为玻璃衬底或者塑料衬底。
本实施例的半导体有源层可为厚度30或80纳米的非晶硅、多晶硅、有机和氧化物半导体薄膜中的一种。
本实施例的电阻栅薄膜层为100或200纳米厚的电阻型薄膜材料，可与半导体有源层具有相同材料的高掺杂薄膜。
本实施例的两栅端电极的连线方向垂直于源、漏电极连线方向，构成类“#”型交叠区域。
本实施例的电阻栅薄膜晶体管的制备方法，包括以下步骤：
（1）采用PECVD技术在玻璃或者塑料基板上沉积100或200纳米厚的二氧化硅薄膜形成过渡层，如图2a所示。
（2）采用磁控溅射或真空蒸镀法在过渡层上沉积金属薄膜，光刻形成两个栅端电极，如图2b所示。
（3）采用PECVD技术或磁控溅射通过掩膜版技术在栅端电极和过渡层上沉积100或200纳米厚的电阻型薄膜材料，形成电阻栅薄膜层，如图2c所示。
（4）采用磁控溅射或真空蒸镀法通过掩膜版技术在电阻栅薄膜层上沉积100或300纳米厚的二氧化硅薄膜形成绝缘栅介质层，绝缘栅介质层还可以选用氮化硅、氧化铪、氧化铝、氧化钽等绝缘薄膜。如图2d所示。
（5）采用PECVD技术、磁控溅射法或旋涂工艺在绝缘栅介质层上沉积半导体薄膜，[e1] ，如图2e所示。
（6）采用磁控溅射法或真空蒸镀法在半导体有源层上100或200纳米厚的Al、Cr、Mo、Au或ITO导电薄膜，光刻形成源漏电极，如图2f所示。
（7）在经（6）处理后的器件在200～250 oC氮氛下退火处理30分钟。
本发明采用电阻型薄膜作为栅，通过调整垂直沟道方向的两个栅端电极的偏压可使薄膜晶体管的转移特性分别处于不截止、遥截止或锐截止状态, 因此可根据实际应用需要获得所需的阈值电压、关态电流和跨导值, 且两个栅端电极可同时作为控制栅和信号栅使用，使电路得到简化，从而有效扩大了薄膜晶体管的应用范围，能有效地解决阈值电压漂移、大信号堵塞、自动增益控制动态范围窄等问题。本发明的电阻栅薄膜晶体管的一种实际应用电路示意图如图3a所示，图中R和Rg分别电阻栅和外接电阻的电阻值，Eg为电源电压，改变Eg的大小即改变栅端电极G1的电压VG1，从而调控输出特性(即输出电流ID与输出电压VDS的关系)和转移特性（输出电流ID与输入电压VG2的关系），图3b示意了栅端电极偏压VG1对应的转移特性曲线（ID与VG2的关系）。验证条件：N=R/Rg=1，迁移率为5 cm2/V.s，沟道宽度与长度之比为20，单位面积绝缘栅介质层电容为34 nF/cm2，金属栅对于的阈值电压为2 V。
上述实施例为本发明较佳的实施方式，但本发明的实施方式并不受所述实施例的限制，其他的任何未背离本发明的精神实质与原理下所作的改变、修饰、替代、组合、简化，均应为等效的置换方式，都包含在本发明的保护范围之内。
Claims (6)
1.一种电阻栅薄膜晶体管，其特征在于，由下至上依次包括衬底、过渡层、栅端电极、电阻栅薄膜层、绝缘栅介质层、半导体有源层、源漏电极，所述电阻栅薄膜层（4）位于两栅端电极 (301和302) 与绝缘栅介质层（5）之间，电阻栅薄膜层的电阻率低于半导体有源层；所述两栅端电极位于电阻栅薄膜层下方，其连线方向与沟道方向垂直，其结构和功能上是等效的；所述源电极（701）和漏电极（702）制作在垂直于两栅端电极连线的方向，使得源漏电极两端与两个栅端电极构成类#型交叠区域，且源漏电极长度小于两栅端电极宽度与两栅端电极间距的总和；所述电阻栅薄膜层为高掺杂半导体薄膜层；所述高掺杂半导体薄膜的电阻明显低于半导体有源层薄膜的电阻；所述电阻栅薄膜层的厚度为80～120纳米。
2.根据权利要求1所述的电阻栅薄膜晶体管，其特征在于，所述半导体有源层是非晶或多晶硅薄膜、有机薄膜和氧化物薄膜中的一种。
3.根据权利要求1所述的电阻栅薄膜晶体管，其特征在于，所述半导体有源层的本体载流子浓度为1015～1018 cm-3。
4.根据权利要求1所述的电阻栅薄膜晶体管，其特征在于，所述半导体有源层的厚度为30～80纳米。
5.根据权利要求1所述的电阻栅薄膜晶体管，其特征在于，所述绝缘栅介质层为100～300纳米厚的二氧化硅、氮化硅、氧化铝、氧化铪或氧化钽薄膜；所述栅端电极、源极或漏极为Al、Cr、Mo、Au或ITO导电薄膜。
6.制备权利要求1~5任一项所述的电阻栅薄膜晶体管的方法，其特征在于，包括以下步骤：
（1）在衬底上沉积二氧化硅或氮化硅薄膜作为过渡层；
（2）在过渡层上沉积金属或ITO导电薄膜，光刻形成两栅端电极；
（3）在两栅端电极和过渡层上沉积高掺杂半导体薄膜，形成电阻栅薄膜层；
（4）在电阻栅薄膜层上沉积二氧化硅、氮化硅、氧化铝、氧化铪或氧化钽薄膜形成绝缘栅介质层；
（5）在绝缘栅介质层上沉积半导体薄膜层，形成半导体有源层；
（6）在半导体沟道有源层上通过掩膜版技术于沟道有源层两端沉积Cr、Mo、Au或ITO导电薄膜，光刻形成源漏电极，并使得源、漏电极的连线方向与两栅端电极的连线方向垂直；
（7）将（6）制得的器件在200～250 oC氮氛下退火处理30～60分钟。
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