CN105428306B - A kind of lithographic method on via bottoms barrier layer - Google Patents
A kind of lithographic method on via bottoms barrier layer Download PDFInfo
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- CN105428306B CN105428306B CN201410449745.6A CN201410449745A CN105428306B CN 105428306 B CN105428306 B CN 105428306B CN 201410449745 A CN201410449745 A CN 201410449745A CN 105428306 B CN105428306 B CN 105428306B
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Abstract
The present invention provides a kind of lithographic methods on via bottoms barrier layer, include the following steps：It is passed through etching gas into reaction chamber, and opens top electrode power supply and lower electrode supply, to remove the barrier layer for being located at via bottoms on substrate；Wherein, etching gas includes oxygen and fluorinated gas, and the throughput of oxygen is more than the throughput of fluorinated gas；Meanwhile the set-up mode of the chamber pressure of reaction chamber, the lower electrode power of lower electrode supply and substrate temperature is：By reducing chamber pressure, lower electrode power and substrate temperature, to avoid crack is generated over the substrate surface.The lithographic method on via bottoms barrier layer provided by the invention can be in direct contact the risk for causing short circuit with wafer, so as to improve yields and production capacity to avoid generating crack on the surface of the substrate, thus after can be reduced postchannel process deposited metal layer.
Description
Technical field
The invention belongs to microelectronic processing technique fields, and in particular to a kind of lithographic method on via bottoms barrier layer.
Background technology
Silicon hole technology (through silicon via, hereinafter referred to as TSV) is by being made between chip and chip
Vertical conducting, realizes the state-of-the-art technology that interconnects between chip, and TSV technology is due to density that chip can be made to be stacked in three-dimensional
Interconnection line maximum, between chip is most short, appearance and size is minimum, and substantially improves the performance of chip speed and low-power consumption, because
And as state-of-the-art a kind of technology in current Electronic Encapsulating Technology.
Referring to Fig. 1, TSV packaging technologies generally comprise following steps：Wafer (Si) is thinned in step S1, to meet envelope
Fill the smaller requirement of thickness；Wafer is bonded on substrate Glass by step S2, and cavity C V is formed below wafer, to avoid
Wafer is in direct contact with substrate Glass to protect wafer；Step S3 etches wafer, to form vertical or inclined through-hole；Step
Rapid S4 deposits barrier layer polymer on the inner surface of through-hole, prevents from leaking electricity to form electricity isolated layer；Step S5, using quarter
Etching method removes via bottoms barrier layer polymer, to expose the conductive metal layer pad as metal pad；Step S6,
Deposited metal layer and subsequent metal line.
Above-mentioned steps S5 generally use inductively coupled plasma dry etchings realize that typical technological parameter is：It adopts
Use CF4And O2Single step etching, wherein CF are carried out as etching gas4For main etching gas, O2To assist gas；CF4Throughput
For 100sccm；O2Throughput be 20sccm；Reaction chamber pressure is 30mT；The output power of top electrode power supply is 1500W；
The output power of lower electrode supply is 300W；The preset temperature of substrate is 20 DEG C.
In practical applications, often there is following ask using the lithographic method of above-mentioned via bottoms barrier layer polymer
Topic：To prevent the excessively thin subsequent device that influences of remaining barrier layer polymer on through-hole side wall after the etch and upper surface
Electrical property, the barrier layer polymer and photoresist layer PR generally deposited is thicker, for example, barrier layer polymer is generally 6~8 μ
The thickness of m, photoresist layer PR are generally 8~14 μm, this makes barrier layer polymer and photoresist layer PR poor radiations, thus
Barrier layer polymer and photoresist layer PR accumulation of heat can be caused, easily causes substrate surface to overheat and generate crack A, such as Fig. 2
Shown, after continuing subsequent metallisation circuit, its surface as shown in Figure 3 still has crack A, and crack A can be from the light
The surfaces photoresist layer PR extend to wafer, to easily cause subsequent deposited metal layer and wafer short circuit, and then seriously affect device
The electrical property of part.
Invention content
The present invention is directed at least solve one of the technical problems existing in the prior art, it is proposed that and it is a kind of, it can be to avoid
Generate crack on the surface of the substrate, thus can be reduced be in direct contact with wafer after postchannel process deposited metal layer cause it is short
The risk on road, so as to improve yields and production capacity.
One of in order to solve the above problem, the present invention provides a kind of lithographic method on via bottoms barrier layer, including it is following
Step：It is passed through etching gas into reaction chamber, and opens top electrode power supply and lower electrode supply, is led to removing to be located on substrate
The barrier layer of hole bottom；Wherein, the etching gas includes oxygen and fluorinated gas, and the throughput of the oxygen is more than institute
State the throughput of fluorinated gas；Meanwhile the lower electrode power of the chamber pressure of the reaction chamber, the lower electrode supply and
The set-up mode of substrate temperature is：By reducing the chamber pressure, lower electrode power and substrate temperature, to avoid in substrate table
Crack is generated on face.
Wherein, the range of the chamber pressure is in 8~20mT.
Wherein, the range of the chamber pressure is in 8~15mT.
Wherein, the throughput of the fluorinated gas accounts for the range of general gas flow 10~30%.
Wherein, the range of the throughput of the oxygen is in 50~300sccm.
Wherein, the range of the throughput of the oxygen is in 80~150sccm.
Wherein, the range of the substrate temperature is at -20~10 DEG C.
Wherein, the range of the substrate temperature is at -20~-10 DEG C.
Wherein, the range of the lower electrode power is in 10~100W.
Wherein, the range of the lower electrode power is in 30~50W.
The invention has the advantages that：
The lithographic method on via bottoms barrier layer provided by the invention, the throughput of oxygen is more than fluorine-containing in etching gas
The throughput of class gas, in other words, oxygen is as main etching gas, and fluorinated gas is as auxiliary etch gas；Meanwhile it reacting
The set-up mode of the chamber pressure of chamber, the lower electrode power of lower electrode supply and substrate temperature is：By reduce chamber pressure,
Lower electrode power and substrate temperature, that is, compared with the existing technology use lower chamber pressure, lower lower electrode power and compared with
Low substrate temperature performs etching.Since the fluorinated gas of relatively low throughput accounting can reduce table of the fluorine-containing particle to substrate
Face is bombarded, this can generate crack to avoid excessive fluorine-containing particle bombardment substrate surface.Lower chamber pressure can make gas
Volume ionization degree reduces, thus can make the negligible amounts of the oxygen-containing particle and fluorine-containing particle of bombardment substrate；And lower lower electricity
Pole power can reduce the energy of oxygen-containing particle and fluorine-containing particle, thus lower chamber pressure and lower electrode power can subtract
The heat of small substrate accumulation, so as to reduce the possibility for generating crack on substrate surface.Lower substrate temperature can be to prevent
Only substrate surface overheats and generates crack, so as to reduce the possibility for generating crack on substrate surface.It therefore, can from above
Know, the lithographic method on via bottoms barrier layer provided by the invention can be to avoid generating crack on the surface of the substrate, thus can
The risk for causing short circuit is in direct contact after postchannel process deposited metal layer with wafer to reduce, so as to improve yields and
Production capacity.
Description of the drawings
Fig. 1 is the diagrammatic cross-section of via bottoms barrier etch；
Fig. 2 is the shape appearance figure of substrate surface after completing step S5；
Fig. 3 is the shape appearance figure for completing substrate surface after metal line in step S6；
Fig. 4 is the flow chart of the lithographic method on via bottoms barrier layer provided in an embodiment of the present invention；
And
Fig. 5 be using via bottoms barrier layer provided in an embodiment of the present invention lithographic method and complete metal line it
The shape appearance figure of substrate surface afterwards.
Specific implementation mode
To make those skilled in the art more fully understand technical scheme of the present invention, come below in conjunction with the accompanying drawings to the present invention
The lithographic method on the via bottoms barrier layer that embodiment provides is described in detail.
Fig. 4 is the flow chart of the lithographic method on via bottoms barrier layer provided in an embodiment of the present invention.Referring to Fig. 4, this
Inventive embodiments provide a kind of lithographic method on via bottoms barrier layer, include the following steps：
It is passed through etching gas into reaction chamber, and opens top electrode power supply, top electrode power supply to reaction chamber for applying
In addition electrode power, so that the indoor etching gas of reaction chamber excites to form plasma；Open lower electrode supply, lower electrode electricity
Source is used to apply lower electrode power to substrate, so that plasma etching substrate, until being located at via bottoms on removal substrate
Barrier layer.
Before performing etching technique, it usually needs the output power of type and throughput, upper power supply to etching gas,
The output power of lower power supply, the pressure of reaction chamber and the technological parameter of process time etc. are configured, to meet different works
The requirement of skill.
Specifically, in the present embodiment, etching gas includes oxygen and fluorinated gas, and the throughput of oxygen is more than and contains
The throughput of fluorine type gas；Also, the chamber pressure of reaction chamber, the lower electrode power of lower electrode supply and substrate temperature are set
The mode of setting is：By reducing the chamber pressure, lower electrode power and substrate temperature, split to avoid generating over the substrate surface
Seam.That is, in the present embodiment, using the oxygen of high gas flow amount, the fluorinated gas of low-flow amount compared with the existing technology
Body, lower chamber pressure, lower lower electrode power and lower substrate temperature perform etching.
Operation principle using the setting of above-mentioned set-up mode is described below in detail.Specifically, as follows：
(1) it is directed to etching gas.Oxygen as main etching gas, fluorinated gas as auxiliary etch gas, this with it is existing
Have in technology fluorinated gas as main etching gas oxygen as auxiliary etch gas phase ratio, increase oxygen throughput and
The throughput for reducing fluorinated gas, oxygen is excited to form oxygen particle in technical process, and fluorinated gas is excited shape
At fluorine-containing particle, since the physical bombardment ability of fluorine-containing particle is much larger than oxygen particle, it is provided in an embodiment of the present invention logical
The lithographic method of hole bottom barrier can reduce surface bombardment of the fluorine-containing particle to substrate, you can to avoid excessive fluorine-containing particle
It bombards substrate surface and generates crack, thus the possibility for generating crack on substrate surface can be reduced.
Preferably, fluorinated gas includes CF4、SF6、C4F8、CHF3、C2F6Or C5F8One or more of equal gases.
It is further preferred that the throughput of fluorinated gas accounts for the range of total gas couette 10~30%, can both utilize so fluorine-containing
Particle (for example, carbon fluorine particle, fluorine particle) the strong characteristic of physical bombardment power ensures etch rate, and can be to avoid fluorine-containing particle
It is excessive that substrate surface is caused to generate crack by bombardment.
Additionally preferably, the range of the throughput of oxygen is in 50~300sccm.It is further preferred that the throughput of oxygen
Range in 80~150sccm.
(2) it is directed to the chamber pressure of reaction chamber.Since higher chamber pressure (for example, >=30mTorr) can to carve
Erosion gas is adequately ionized, this can make the concentration of oxygen particle and fluorine-containing particle in reaction chamber increase, thus can make more
Oxygen particle and fluorine-containing particle bombardment substrate, to can cause substrate accumulate heat increase and make the excessively high surface of its temperature be easy
Generate crack；In addition, higher chamber pressure is also easy to cause oxygen particle and fluorine-containing Particles Moving directionality difference and easily collision, it can
The etching efficiency on via bottoms barrier layer can be caused to decline.Therefore, the present embodiment makes by using lower chamber pressure
Gas ionization degree reduces, and can make the negligible amounts of the oxygen-containing particle and fluorine-containing particle of bombardment substrate, thus can reduce base
The heat of piece accumulation, so as to reduce the possibility for generating crack on substrate surface；But also via bottoms resistance can be solved
The problem of etching efficiency of barrier declines.
Preferably, the range of the chamber pressure of reaction chamber is in 8~20mT；It is further preferred that the chamber of reaction chamber
The range of pressure is in 8~15mT.
(3) it is directed to lower electrode power.Since the output power (for example, >=100W) of higher lower electrode supply can enhance
Oxygen particle and fluorine-containing particle energy in reaction chamber, therefore the bombardment intensity of oxygen particle and fluorine-containing particle to substrate can be enhanced, because
And the heat that substrate can be caused to accumulate increases and the excessively high substrate surface of its temperature is made to easy to produce crack；In addition, the oxygen of high-energy
Particle and fluorine-containing particle can cause through-hole upper surface and madial wall to damage and increase the bombardment intensity to photoresist, to make
The etch rate of photoresist improves, and in turn results in etching selection ratio reduction.Therefore, the present embodiment is by using lower lower electrode
Power, can reduce the energy of oxygen-containing particle and fluorine-containing particle, thus can reduce the heat of substrate accumulation, to not only can be with
The possibility for generating crack on substrate surface is reduced, but also through-hole upper surface and madial wall generation damage can be solved and carved
Erosion selection is than low problem.
Preferably, the range of lower electrode power is in 10~100W；It is further preferred that the range of lower electrode power 30~
50W。
(4) it is directed to substrate temperature.It is appreciated that by being performed etching to the lower substrate of temperature, substrate table can be prevented
Face overheat generates crack, so as to reduce the possibility for generating crack on substrate surface.To realize to the lower substrate of temperature
It performs etching, it specifically, can be by the temperature of the cooler in the bogey of setting carrying substrates, so that cooler is indirect
Heat exchange is carried out to reduce the temperature of substrate by bogey and substrate, and in other words, the cooler of lower temperature is taken away in time
The heat that substrate generates in technical process, you can to reduce the accumulation of heat of substrate, thus realize the substrate in technical process
Temperature it is relatively low, so as to prevent substrate surface overheat from generating crack, and then can reduce and to generate crack on substrate surface
Possibility.
Preferably, the range of substrate temperature is at -20~10 DEG C；It is further preferred that the range of substrate temperature -20~-
10℃。
It is tested below using the lithographic method on via bottoms barrier layer provided in an embodiment of the present invention, experiment is used
Technological parameter be specially：Chamber pressure is 10mT；Upper electrode power is 1500W；Lower electrode power is 50W；The air-flow of oxygen
Amount is 100sccm；Fluoro-gas includes CF4, and CF4Throughput be 40sccm；Substrate temperature is -20 DEG C.
It is obtained using the lithographic method on via bottoms barrier layer provided in an embodiment of the present invention and above-mentioned technological parameter
Substrate surface pattern is as shown in Figure 5 after completing metal line, it is therefore apparent that is not produced on the surface that etching completes meron
Raw crack, therefore after continuing to complete metal line, crack is not present on the surface of substrate.
Therefore, the experiment it can be shown that via bottoms barrier layer provided in this embodiment lithographic method, oxygen make
It is main etching gas and fluorinated gas as auxiliary etch gas, and passes through and reduce chamber pressure, lower electrode power and base
Under the premise of piece temperature, the surface that substrate may be implemented not will produce crack, good so as to largely improve product
Rate.
It should be noted that in the present embodiment, through-hole can be round, rectangular in the contour shape of its radial section
Shape, straight line or curve concatenate the shapes such as the figure to be formed.
It should also be noted that, other than technological parameter condition mentioned above, via bottoms resistance provided by the embodiment
Other technological parameter conditions of the lithographic method of barrier are similar with the prior art, for example, the process environments temperature of reaction chamber
>=20 DEG C etc. are answered, will not enumerate herein.
It is understood that the principle that embodiment of above is intended to be merely illustrative of the present and the exemplary implementation that uses
Mode, however the present invention is not limited thereto.For those skilled in the art, in the essence for not departing from the present invention
In the case of refreshing and essence, various changes and modifications can be made therein, these variations and modifications are also considered as protection scope of the present invention.
Claims (7)
1. a kind of lithographic method on via bottoms barrier layer, which is characterized in that include the following steps：
It is passed through etching gas into reaction chamber, and opens top electrode power supply and lower electrode supply, is led to removing to be located on substrate
The barrier layer of hole bottom；
Wherein, the etching gas includes oxygen and fluorinated gas, and the throughput of the oxygen is more than the fluorinated gas
The throughput of body；Meanwhile the chamber pressure of the reaction chamber, the lower electrode power of the lower electrode supply and substrate temperature are set
It is set to：The range of the chamber pressure is in 8~20Mt, and the range of the substrate temperature is at -20~10 DEG C, the lower electrode power
Range in 10~100W, to avoid crack is generated over the substrate surface.
2. the lithographic method on via bottoms barrier layer according to claim 1, which is characterized in that the model of the chamber pressure
It is trapped among 8~15mT.
3. the lithographic method on via bottoms barrier layer according to claim 1, which is characterized in that the fluorinated gas
Throughput accounts for the range of general gas flow 10~30%.
4. the lithographic method on via bottoms barrier layer according to claim 1, which is characterized in that the throughput of the oxygen
Range in 50~300sccm.
5. the lithographic method on via bottoms barrier layer according to claim 4, which is characterized in that the throughput of the oxygen
Range in 80~150sccm.
6. the lithographic method on via bottoms barrier layer according to claim 1, which is characterized in that the model of the substrate temperature
It is trapped among -20~-10 DEG C.
7. the lithographic method on via bottoms barrier layer according to claim 1, which is characterized in that the lower electrode power
Range is in 30~50W.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101667542A (en) * | 2008-09-02 | 2010-03-10 | 中芯国际集成电路制造(上海)有限公司 | Method for repairing and etching polysilicon |
| CN103367139A (en) * | 2013-07-11 | 2013-10-23 | 华进半导体封装先导技术研发中心有限公司 | TSV hole bottom medium layer etching method |
| CN103811406A (en) * | 2012-11-05 | 2014-05-21 | 上海华虹宏力半导体制造有限公司 | Method for improving automatic alignment contact hole electric leakage of SONOS device |
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| JP5373669B2 (en) * | 2010-03-05 | 2013-12-18 | 東京エレクトロン株式会社 | Manufacturing method of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101667542A (en) * | 2008-09-02 | 2010-03-10 | 中芯国际集成电路制造(上海)有限公司 | Method for repairing and etching polysilicon |
| CN103811406A (en) * | 2012-11-05 | 2014-05-21 | 上海华虹宏力半导体制造有限公司 | Method for improving automatic alignment contact hole electric leakage of SONOS device |
| CN103367139A (en) * | 2013-07-11 | 2013-10-23 | 华进半导体封装先导技术研发中心有限公司 | TSV hole bottom medium layer etching method |
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