CN109643651B - Etching stop layer and method for manufacturing semiconductor device - Google Patents

Etching stop layer and method for manufacturing semiconductor device Download PDF

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CN109643651B
CN109643651B CN201880003102.5A CN201880003102A CN109643651B CN 109643651 B CN109643651 B CN 109643651B CN 201880003102 A CN201880003102 A CN 201880003102A CN 109643651 B CN109643651 B CN 109643651B
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etching
layer
stop layer
semiconductor device
target
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CN109643651A (en
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中村真也
逸见充则
藤井佳词
池田佳广
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Ulvac Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Plasma & Fusion (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Weting (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

The invention provides an etching stop layer with excellent control when wet etching and a method for manufacturing a semiconductor device. When etching the etching target layer (Le) in one direction by dry etching, the etching stop layer (Ls) of the present invention is laminated on the etching advancing direction front side of the etching target layer, the etching stop layer being composed of an aluminum oxide film (BAlOx film, YAlOx film) containing 20 to 50 wt% of boron or yttrium.

Description

Etching stop layer and method for manufacturing semiconductor device
Technical Field
The present invention relates to an etching stop layer and a method for manufacturing a semiconductor device having a laminated structure of the etching stop layer and an etched layer.
Background
As a large-capacity semiconductor device, for example, a 3D (three-dimensional) NAND flash memory in which memory cells are vertically laminated is known in patent document 1. The manufacturing process of the 3D-NAND flash memory comprises the following steps: forming an etching stop layer; a step of laminating a polysilicon layer, a silicon oxide layer, or the like constituting the memory cell on the etching stopper layer; and forming a hole for forming a wiring by dry etching the etched layer in the vertical direction by using the laminated product as the etched layer. An aluminum oxide film is generally used as such an etching stop layer.
After forming the hole by dry etching, hydrogen was usedAn etching solution such as fluoric acid wets the etching stop layer. However, the wet etching rate of the alumina film is
Figure BDA0001967052550000011
On the left and right, it is relatively quick and difficult to end at a timing suitable for wet etching. Once the end timing of the wet etching is delayed, the wet etching isotropically advances, and thus, there is a problem that the etching stopper layer is overetched in the lateral direction. This problem is more pronounced when the thickness of the alumina film is thin. Thus, the etching stopper layer formed of the aluminum oxide film is not a product having good controllability to wet etching.
Prior art literature
Patent literature
Japanese patent laid-open publication 2016-25141 (patent document 1)
Disclosure of Invention
Technical problem to be solved by the invention
In view of the foregoing, an object of the present invention is to provide an etching stop layer having excellent controllability when wet-etched and a method for manufacturing a semiconductor device.
Means for solving the technical problems
In order to solve the above problems, an etching stop layer according to the present invention is characterized in that: when etching the etching target layer in one direction by dry etching, the etching stop layer is laminated on the etching advancing direction front side of the etching target layer, and the etching stop layer is composed of an aluminum oxide film containing 20 to 50 wt% of boron.
According to the present invention, since the aluminum oxide film contains 20 to 50 wt% of boron, the wet etching rate of the etching stopper layer can be reduced. Using the experiments described below, it was confirmed that the wet etching rate was controlled to be low when wet etching was performed using hydrofluoric acid as an etching liquid
Figure BDA0001967052550000021
Within a range of (2). Thus, an etching stop layer having excellent controllability at the time of wet etching can be obtained.
The present invention is preferably applied to a case where the layer to be etched is formed of a laminated film in which 32 or more polysilicon layers and a silicon-containing insulating layer are laminated by dry etching using oxygen.
The method for manufacturing a semiconductor device according to the present invention for manufacturing a semiconductor device having a laminated structure of the etching stopper layer and the etched layer, includes: a step of wet etching the etching stopper layer using an etching liquid selected from hydrofluoric acid and the like after dry etching the etching target layer, wherein a wet etching rate of the etching stopper layer is set to be at
Figure BDA0001967052550000022
Within a range of (2).
Drawings
Fig. 1 is a schematic cross-sectional view of a semiconductor device using an etch stop layer of an embodiment of the present invention.
Fig. 2 (a) to (d) are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device.
Fig. 3 is a diagram schematically illustrating a sputtering apparatus capable of forming an etching stopper layer according to an embodiment of the present invention.
Fig. 4 is a graph showing experimental results for confirming the effects of the present invention.
Detailed Description
A semiconductor device to which an etching stopper layer according to an embodiment of the present invention is applied will be described below with reference to the drawings.
As shown in fig. 1, the semiconductor device SD has a substrate S, an etching stop layer Ls formed on the substrate S, and an etched layer Le formed on the etching stop layer Ls.
The substrate S may be appropriately selected from a silicon substrate, a GaAs substrate, a GaP substrate, an InP substrate, and the like, depending on the type of the semiconductor device SD. The substrate S includes a substrate on the surface of which a semiconductor element such as a transistor is formed.
When etching the etching target layer Le in one direction by dry etching, the etching stop layer Ls is laminated on the etching advancing direction front side (lower side) of the etching target layer Le. The etching stop layer Ls is composed of an aluminum oxide film (BAlOx film) containing 20 to 50 wt% of boron. If the boron content is less than 20 wt%, the wet etching rate of the etching stopper layer Ls may not be sufficiently suppressed, whereas if the boron content exceeds 50 wt%, the dry etching resistance may be lowered.
The etched layer Le is, for example, a layer of a laminated film of a plurality of layers (for example, 32 layers and 32 or more) of polysilicon layers and a silicon-containing insulating layer. Here, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film may be used as the insulating layer containing silicon. A method for manufacturing the semiconductor device SD will be described below with reference to fig. 2.
First, as shown in fig. 2 (a), an etching stop layer Ls is formed on a substrate S. Here, the etching stop layer Ls may be formed using a sputtering apparatus SM as shown in fig. 3. The sputtering apparatus SM has a vacuum chamber 1 defining a process chamber 10, and a gas pipe 11 for introducing a sputtering gas into the process chamber 10 is connected to a side wall of the vacuum chamber 1, and a mass flow controller 12 is inserted into the gas pipe 11 and communicates with a source 13 of the sputtering gas. The sputtering gas contains reactive gases such as oxygen and water vapor in addition to inert gases such as argon during reactive sputtering. An exhaust pipe 14 communicating with a vacuum exhaust device P such as a rotary pump or a turbo molecular pump is connected to the bottom wall of the vacuum chamber 1. Thereby, the pressure of the processing chamber 10 during film formation is kept substantially constant.
A substrate stage 2 is provided at the bottom center of the vacuum chamber 1. The substrate stage 2 is composed of, for example, a base 21 made of a metal material having an upper surface shape corresponding to the contour of the substrate S, and a chucking plate 22 attached to the upper surface of the base 21. A well-known electrode, not shown, is incorporated in the chucking plate 22, and a chuck voltage is applied to the electrode from a chuck power source, so that the substrate S is held on the upper surface of the chucking plate 22 with its film-forming surface facing upward. A rotation shaft 24 supported by a bearing 23 is connected to the center of the lower surface of the base 21, and the bearing 23 is inserted through an opening provided in the bottom surface of the vacuum chamber 1, and the rotation shaft 24 is driven to rotate by a driving unit (not shown) outside the vacuum chamber 1, whereby the substrate stage 2 can be rotated while holding the substrate S. The base 21 may be provided with a coolant circulation passage and a heater, and the substrate S may be controlled to a predetermined temperature during the sputtering film formation.
At the inner top of the vacuum chamber 1, two targets 3a, 3b are provided obliquely at 180 ° intervals in the circumferential direction so that the sputtering surfaces 3a, 3b are opposed to the substrate S, respectively. As the target 3a, a target made of alumina may be used, and as the target 3b, a target made of boron may be used. Although not shown, backing plates made of copper for cooling the targets 3a and 3b during the sputtering film formation are bonded to the upper surfaces (surfaces facing the sputtering surfaces 3a and 3 b) of the targets 3a and 3b by an adhesive material made of a material having high thermal conductivity such as indium or tin. Further, a known magnet unit may be disposed above each of the targets 3a and 3b, and a magnetic field (known closed magnetic field or cusp magnetic field) may be generated in a space below the sputtering surfaces 3a and 3b of the targets 3a and 3b, whereby ionized electrons or the like are trapped below the sputtering surfaces 3a and 3b during sputtering, and sputtered particles scattered from the targets 3a and 3b are effectively ionized.
The targets 3a and 3b are connected to high-frequency power supplies E1 and E2 as sputtering power supplies, respectively, and high-frequency power of a predetermined frequency (for example, 13.56 MHz) is applied between them and the ground during sputtering. The sputtering apparatus SM includes a known control device including a microcomputer, a sequencer, and the like, and controls the operation of the mass flow controller 12, the operation of the vacuum evacuation device P, the operation of the sputtering power sources E1 and E2, and the like.
When an aluminum oxide film is formed as an etching stop layer Ls on a substrate S by using the sputtering apparatus SM, the inside of the vacuum chamber 1 (processing chamber 10) is evacuated to a predetermined vacuum degree (for example, 1×10) -5 Pa), the substrate S is transported into the vacuum chamber 1 by a transport robot, not shown, and is positioned and held on the substrate stage 2. Subsequently, the mass flow controller 12 is controlled to introduce argon gas at a predetermined flow rate (at this time, the pressure in the process chamber 10 is 0.1 to 0.2 Pa), and in combination with this, a high-frequency power of, for example, 13.56MHz of 100W to 500W is applied from the high-frequency power source E1 to the target 3a, and a high-frequency power of, for example, 13.56MHz of 100W to 500W is applied from the high-frequency power source E2 to the target 3b. Thereby, plasma is formed in the vacuum chamber 1, and sputtering is performed on the target 31. The sputtered particles scattered from the targets 3a and 3b are deposited on the surface of the substrate S by sputtering, whereby a boron-containing aluminum oxide film (BAlOx film) is formed on the surface of the substrate S. The boron content in the aluminum oxide film can be controlled by changing the ratio of the electric power applied to the target 3a to the electric power applied to the target 3b。
Next, a multi-layered polysilicon film, a silicon oxide film, or the like is formed on the etching stopper layer Ls as an etching target layer Le. These polysilicon films and silicon oxide films can be formed by a known method such as sputtering or CVD, and therefore, detailed description thereof is omitted here. In the case of using a known sputtering apparatus, a target made of silicon may be used as the target in the processing chamber. If a resist pattern is formed as a mask layer Lm on the etched layer Le by a known method, the structure shown in fig. 2 (a) can be obtained.
Next, as shown in fig. 2 (b), the etching target layer Le is vertically dry etched, and wiring holes h are formed in the etching target layer Le. Furthermore, for the conditions of dry etching, for example, a known RIE condition using CHF can be used 3 、C 2 F 6 、CF 4 Such as a fluorine-containing gas, as an etching gas, and therefore, a detailed description thereof will be omitted here.
After the dry etching is completed, the etching stop layer Ls is wet etched as shown in fig. 2 (c). As the etching liquid used for wet etching, for example, a known etching liquid selected from hydrofluoric acid and the like can be used. Here, since the etching stopper layer Ls of the present embodiment is made of an aluminum oxide film containing 20 to 50 wt% of boron, the wet etching speed of the etching stopper layer Ls can be reduced. Therefore, the wet etching can be terminated at an appropriate timing, and the etching stopper Ls can be prevented from being excessively advanced in the lateral direction. Thus, the etching stopper layer Ls of the present embodiment can be said to have excellent controllability for wet etching.
Finally, after removing the mask layer Lm by ashing, the semiconductor device SD shown in fig. 2 (d) can be obtained. Further, a conductive film is formed in the hole h as needed. As for the ashing conditions, well-known conditions can be used, and therefore, a detailed description thereof is omitted here.
Next, in order to confirm the above effect, the following experiment was performed using the sputtering apparatus SM. In this experiment, a silicon substrate having a diameter of 300mm was used as the substrate S, and after the substrate S was set on the substrate stage 2 in the vacuum chamber 1, argon gas was introduced into the processing chamber 10 at a flow rate of 300sccm (at this time, the pressure in the processing chamber 10 was about 1.35 Pa), a high-frequency power of 13.56MHz was applied from the power source E1 to the alumina target 3a at 227W, and from the power sourceE2 applies 300W of high-frequency power of 13.56MHz to the boron target 3b (at this time, the ratio of power applied to the targets 3a, 3b is 1:1.32). Thus, the targets 3a and 3b formed aluminum oxide films (BAlOx films) containing 20 weight percent (wt%) of boron on the surfaces of the substrates S. Wet etching the alumina containing 20 wt% boron, the etching rate was measured to be
Figure BDA0001967052550000041
Using HF H 2 A hydrofluoric acid solution of o=1:2000 (0.05 wt%) was used as an etching solution for wet etching. The ratio of electric power applied to the targets 3a, 3b was changed in a manner of 1:0, 1:0.7, 1:1, 1:1.3, 1:1.5, 1:1.8, 1:2.6, thereby forming aluminum oxide films containing 0 wt%, 10 wt%, 15 wt%, 25 wt%, 30 wt%, 50 wt% of boron, respectively, and wet etching rates were measured as%>
Figure BDA0001967052550000051
Finally as shown in fig. 4. Thereby confirming: by setting the boron content in the aluminum oxide film to be in the range of 20 to 50 wt%, the wet etching rate of the aluminum oxide film can be controlled to +.>
Figure BDA0001967052550000052
Within a range of (2). Further, it was confirmed that the wet etching rate of the aluminum oxide film was controlled to +.>
Figure BDA0001967052550000053
Within a range of (2). Further, it was confirmed that when the boron content exceeds 50 wt%, the wet etching rate was not changed and the particles increased.
The embodiments of the present invention have been described above, but the present invention is not limited to the above embodiments. In the above embodiment, the target 3a made of alumina is used, but the target 3a may be made of aluminum, or a target made of reactive sputtering of the aluminum may be used.
In the above embodiment, the etching stopper Ls was formed using two targets 3a and 3b, but the etching stopper Ls may be formed using one target (BAlOx target) made of alumina containing boron at a predetermined concentration (for example, 30 wt%).
In the above embodiment, the case where the etching stopper layer Ls is formed by sputtering was described as an example, but the method of forming the etching stopper layer Ls is not limited to this, and a known film forming method such as CVD can be used. When the CVD method is used, the boron content can be controlled by controlling the flow ratio of the boron-containing raw material gas and the aluminum-containing raw material gas.
In the above embodiment, the case where the aluminum oxide film containing 20 to 50 wt% of boron is used as the etching stopper layer Ls has been described as an example, but the same effect can be obtained when the aluminum oxide film containing 20 to 50 wt% of yttrium without containing boron is used.
Description of the reference numerals
S … substrate, ls … etch stop layer, le … etched layer.

Claims (2)

1. An etch stop layer, characterized by:
laminating the etching stop layer on the etching advancing direction front side of the etching target layer when etching the etching target layer in one direction by dry etching;
the etching stop layer is composed of an aluminum oxide film containing 20 to 50 wt% of boron or yttrium;
the layer to be etched is formed of a laminated film in which 32 or more polysilicon layers and a silicon-containing insulating layer are laminated by dry etching using oxygen.
2. A method of manufacturing a semiconductor device, characterized by: a method for manufacturing a semiconductor device having the laminated structure of the etching stopper layer and the etched layer according to claim 1, the method comprising:
a step of wet etching the etching stopper layer using an etching solution composed of hydrofluoric acid after dry etching the etching target layer, wherein a wet etching rate of the etching stopper layer is set to be at
Figure FDA0004060225400000011
Within a range of (2). />
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CN1767171A (en) * 2004-10-14 2006-05-03 三星电子株式会社 Etch stop structure and manufacture method, and semiconductor device and manufacture method
CN104051256A (en) * 2013-03-14 2014-09-17 台湾积体电路制造股份有限公司 Semiconductor Devices and Methods of Manufacture Thereof

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US9437606B2 (en) * 2013-07-02 2016-09-06 Sandisk Technologies Llc Method of making a three-dimensional memory array with etch stop
JP2015056444A (en) * 2013-09-10 2015-03-23 株式会社東芝 Nonvolatile storage device and manufacturing method of the same
US9960280B2 (en) * 2013-12-26 2018-05-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
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US4767724A (en) * 1986-03-27 1988-08-30 General Electric Company Unframed via interconnection with dielectric etch stop
CN1767171A (en) * 2004-10-14 2006-05-03 三星电子株式会社 Etch stop structure and manufacture method, and semiconductor device and manufacture method
CN104051256A (en) * 2013-03-14 2014-09-17 台湾积体电路制造股份有限公司 Semiconductor Devices and Methods of Manufacture Thereof

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