CN105097440A - Deep silicon etching method - Google Patents
Deep silicon etching method Download PDFInfo
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- CN105097440A CN105097440A CN201410221761.XA CN201410221761A CN105097440A CN 105097440 A CN105097440 A CN 105097440A CN 201410221761 A CN201410221761 A CN 201410221761A CN 105097440 A CN105097440 A CN 105097440A
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Abstract
The present invention provides a deep silicon etching method including the steps as follows: an anisotropic etching step, wherein, a first reactant gas is provided for etching a silicon material layer in the presence of a plasma, and etching to a certain depth so as to expose an etching interface, the etching interface includes a side wall, the first reactant gas includes an etching gas and a side wall protective gas, and the side wall protective gas is used for compensating the etching action of the etching gas to the side wall in a transverse direction; a side wall protecting step, wherein, a second reactant gas is provided for forming a side wall protective layer on the side wall of the etching interface in the presence of the plasma, the side wall protective layer attaches to the surface of the side wall of the etching interface, and the second reactant gas includes a side wall protective gas; and an alternative circulation step, wherein, the anisotropic etching step and the side wall protecting step are performed alternatively until the silicon material layer is etched to a target depth. According to the invention, the etching rate is rapid, prepared deep silicon through holes or grooves have a good feature and a deep depth, and a problem of waved or tapered side wall can be avoided.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of dark silicon etching method.
Background technology
Etching technics refers to and to adopt in chemical solution or corrosive gas or plasma removing wafer or the technique of unwanted part in crystal column surface rete manufacturing in semiconductor device process.Usually the method that main chemical solution carries out etching is wet etching, and the method adopting corrosive gas or plasma to carry out etching is dry etching.At present, the dry etching that circuitous pattern can be made to become meticulousr obtains using more and more widely.
In wet etching, carry out isotropic etching with the chemical reaction of strong acid, even if also can be etched by the part that mask covers.On the contrary, dry etching reactive ion etching, wherein, uses the aggressive chemistry gas of the halogen of such as plasma state and plasma state ion to etch.Therefore, dry etching can realize only on wafer, carrying out the anisotropic etching that etches by vertical direction, so dry etching is applicable to require high-precision hand work, such as, is applicable to very large scale integration (VLSI) technique.
Traditional plasma treatment appts comprises the reaction chamber importing process gas, is configured with the parallel plate electrode be made up of a pair upper electrode and lower electrode in described reaction chamber.While process gas is imported in reaction chamber, lower electrode applies high frequency voltage, between electrode, forms high-frequency electric field, the plasma of formation processing gas under the effect of high-frequency electric field.
The dark silicon via etch of prior art mainly comprises manufacture silicon through hole or groove.Wherein, in the graphic procedure from the Graphic transitions of photoresist to hard mask, ensure that the figure be transferred on hard mask can not be out of shape and will ensure sidewall etching can not occur in the process of the hard mask of etching, also finally can not cause size offset.In order to enough etch rates, dark silicon via etch also to be avoided to become isotropy etching (isotropicetch).Under the trend that device required precision is more and more higher, above-mentioned two requirements can not be taken into account usually.Usual produced problem comprises sidewall in etching and occurs arc wheel profile, and the line size that the line size of etching gained and mask are defined occurs that very large critical size offsets (CDshift).
Therefore, need in the industry a kind of dark silicon via etch mechanism, can etch topography be ensured, higher etch rate can be kept again.
Summary of the invention
For the problems referred to above in background technology, the present invention proposes a kind of dark silicon etching method.
The invention provides a kind of dark silicon etching method, wherein, described lithographic method comprises the steps:
Anisotropic etch step, the first reacting gas is provided to etch silicon material layer under action of plasma, and be etched to certain depth, to expose an etching interface, described etching interface comprises sidewall, described first reacting gas comprises etching gas and sidewall protective gas, and described sidewall protective gas is for compensating described etching gas to the corrasion in a lateral direction of this sidewall;
Sidewall protection step, provides the second reacting gas, and under action of plasma, form side wall protective layer at the sidewall of described etching interface, be attached to the sidewall surfaces of described etching interface, described second reacting gas comprises sidewall protective gas;
Anisotropic etch step described in alternate cycles and sidewall protection step, until etching arrives target depth.
Further, the time of implementation ratio of described anisotropic etch step and sidewall protection step is for being greater than 5:1.
Further, the time of implementation of described anisotropic etch step and sidewall protection step, than for being greater than 5:1, is less than 20:1.
Further, the etching gas that described first reacting gas comprises is SF6.
Further, the sidewall protective gas that described first reacting gas comprises comprises C4F8, O2, SiF4.
Further, the etching gas in described first reacting gas and the ratio of sidewall protective gas are 4:1 to 2:1.。
Further, the sidewall protective gas that described first reacting gas comprises comprises C4F8 or O2.
Further, mask layer or photoresist layer is also provided with above described silicon material layer.
Further, anisotropic etch step described in alternate cycles and sidewall protection step, until etching arrives target depth to form silicon through hole or groove.
Further, described lithographic method carries out in inductance coupling high type plasma etch chamber room.
Perform silicon through hole/silicon trench depth that dark silicon etching method of the present invention obtains dark, and its from top to bottom transverse width all reach unanimity, there is not the problem that the sidewall of prior art presents waveform or sidewall and presents taper.Further, the present invention, while taking into account silicon through hole/silicon trench pattern, maintains higher etching speed.
Accompanying drawing explanation
Fig. 1 is the structural representation of inductance coupling high type plasma process chamber;
Fig. 2 is the pattern schematic diagram of the dark silicon etching via/trench of non-Bosch of prior art;
Fig. 3 a ~ 3c is the processing step flow chart of the dark silicon etching via/trench of Bosch of prior art;
Fig. 4 a ~ 4d is the processing step flow chart of the dark silicon etching method according to the present invention's specific embodiment;
Fig. 5 is the pattern schematic diagram of the via/trench manufactured by the dark silicon etching method of the present invention's specific embodiment.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described.
Deep hole silicon etching is generally carry out in inductance coupling high type plasma etch chamber room.Fig. 1 is the structural representation of inductance coupling high type plasma process chamber.Inductance coupling plasma processing device 100 comprises metal sidewall 102 and insulation top board 104, forms an airtight vacuum sealing housing, and is vacuumized by vacuum pumping pump (not shown).Described insulation top board 104 only exemplarily, also can adopt other top board pattern, and such as dome shape, with the metal top plate etc. of insulating material window.Pedestal 106 comprises an electrostatic chuck (not shown), described electrostatic chuck is placed pending substrate W.Bias power is applied on described electrostatic chuck, to produce the chucking power to substrate W.The radio-frequency power of radio-frequency power supply 108 be applied to be positioned at insulation top board 104 on radio-frequency power emitter on.Wherein, in the present embodiment, described radio-frequency (RF) transmitter comprises radio-frequency coil 110.Process gas is supplied in reaction chamber from source of the gas through pipeline, to light and to maintain plasma, thus on substrate W, carries out dark silicon etching processing procedure.Preferably, process gas and enter chamber from gas inject mouth 112.
The dark silicon etching mechanism of prior art generally includes two kinds, the common dark silicon etching of the first, namely the dark silicon etching of non-Bosch (Non-Boschprocess).Fig. 2 is the pattern schematic diagram of the dark silicon etching via/trench of non-Bosch of prior art.Simultaneously the dark silicon etching of non-Bosch passes into reacting gas and sidewall protective gas, thus carry out etching and sidewall protection step simultaneously.Owing to carrying out etching and sidewall protection step simultaneously, the etching speed of the dark silicon etching of non-Bosch is very fast, and there will not be the sidewall of Bosch processing procedure to present wavy pattern.But, the shortcoming of the dark silicon etching of non-Bosch is also fairly obvious, as shown in Figure 2, it etches silicon base 204 for mask with mask layer 202, the silicon through hole finally made or silicon trench 200 can present taper, the opening of upper part is comparatively large, and along with the vertical extension of silicon through hole or silicon trench, opening is more and more less.
The another kind of the dark silicon etching mechanism of prior art with more be Bosch technique; Bosch technique (Boschprocess) switchably implements separately etch step and sidewall protection step, and etch step is implemented in circulation and sidewall protects step to reach etching depth.Fig. 3 is the processing step flow chart of the dark silicon etching via/trench of Bosch of prior art, as shown in Figure 3 a, first performs etch step, with mask layer 302 for mask, etches silicon substrate 304, to obtain opening 306.Following execution sidewall protection step, as shown in Figure 3 b, above mask layer 302 and the side wall deposition side wall protective layer 308 of etching interface.Then continue to perform etch step, the etching interface that Formation Depth is darker as shown in Figure 3 c, as shown in Figure 3 c, Bosch lithographic method can form wavy pattern at the sidewall of etching interface, the deep hole (silicon through hole or silicon trench) finally formed also can be wavy pattern, further, its etching efficiency is also very low.
In order to solve the problem, the present invention proposes a kind of dark silicon etching method.Fig. 4 a ~ 4d is the processing step flow chart of the dark silicon etching method according to the present invention's specific embodiment.Describe in detail to dark silicon etching method provided by the invention below in conjunction with accompanying drawing 4a ~ 4d, it comprises the steps.
As shown in fig. 4 a, first perform anisotropic etch step, provide the first reacting gas to etch silicon material layer 404 under action of plasma, and be etched to certain depth, to expose an etching interface 406, described etching interface 406 comprises sidewall 404a.Wherein, described first reacting gas comprises etching gas and sidewall protective gas, and etching gas is used for silicon material layer to be etched to desired depth, and sidewall protective gas does side wall protective layer in the process of etching simultaneously on the sidewall 404a of etching interface 406.Because sidewall protective gas and etching gas act on simultaneously; therefore the side wall protective layer on sidewall 404a can not remain in this step; because it can be etched, attack falls; however; side wall protective layer in this step on sidewall 404a or in and corrasion active force transversely, taken into account again etching speed.
As shown in Figure 4 b, then perform sidewall protection step, the second reacting gas is provided, under action of plasma, form side wall protective layer 408 at the sidewall of described etching interface 406, be attached to the sidewall 406a surface of described etching circle 406.Wherein, described second reacting gas comprises sidewall protective gas.Side wall protective layer 408 can be protected the horizontal proliferation trend of ready-made etching interface and compensate; the a upper anisotropic etch step ready-made degree of depth can not be destroyed when next step performs anisotropic etch step; can also continue toward downward-extension, the etch topography that thus there will not be prior art to occur presents the problem of taper.
As illustrated in fig. 4 c, continue to perform second time anisotropic etch step, provide the first reacting gas to continue to etch further to silicon material layer 404 under action of plasma, and be etched to the necessarily darker degree of depth.Wherein, described first reacting gas comprises etching gas and sidewall protective gas; etching gas is used for continuing silicon material layer 404 to be etched to desired depth, and sidewall protective gas continues to do side wall protective layer in the process of etching simultaneously on the sidewall 404a of etching interface 406.In this step, the side wall protective layer 408 that front sidewall protection step deposits can by eating away in the same time, but compensate for the lateral etching spreading trend of corrasion in the ready-made degree of depth.In being still responsible for the side wall protective layer of stylish formation on sidewall 404a in this step and the active force transversely of the degree of depth that etches in this step of corrasion, and take into account etching speed.
As shown in figure 4d, continue to perform second time sidewall protection step, the second reacting gas is provided, under action of plasma, forms side wall protective layer 408 ' at the sidewall of described etching interface 406, be attached to the sidewall 406a surface of described etching circle 406.Wherein, described second reacting gas comprises sidewall protective gas.Anisotropic etch step described in following alternate cycles and sidewall protection step, until etching arrives target depth.
Further, described anisotropic etch step and sidewall protection step hocket as described above, and both time of implementation ratios are for being greater than 5:1.The present invention arranges the more time in anisotropic etch step; etch rate can be kept like this; and because anisotropic etch step also has sidewall protective effect to carry out simultaneously; so also ensure that the pattern of silicon through hole/silicon trench can not produce taper to a certain extent, therefore the more time can be performed.
Preferably, the time of implementation of described anisotropic etch step and sidewall protection step, than for being greater than 5:1, is less than 20:1.Such as, 6:1,7.2:1,9:1,12:1,13.5:1,18:1 etc. are comprised.
Further, the etching gas that described first reacting gas comprises is SF6.
Further, the sidewall protective gas that described first reacting gas comprises comprises C4F8, O2, SiF4.
Further, the etching gas in described first reacting gas and the ratio of sidewall protective gas are 4:1 to 2:1, such as 3.8:1,3.2:1,2.35:1,2.58:1 etc.
Further, the sidewall protective gas that described first reacting gas comprises comprises C4F8 or O2.
Further, above described silicon material layer, being also provided with mask layer or photoresist layer, for etching silicon material layer as mask, thus forming silicon through hole or silicon trench
Further, anisotropic etch step described in alternate cycles and sidewall protection step, until etching arrives target depth to form silicon through hole or groove 400.
Fig. 5 is the pattern schematic diagram of the via/trench manufactured by the dark silicon etching method of the present invention's specific embodiment.As shown in Figure 5, perform silicon through hole/silicon trench 400 degree of depth that dark silicon etching method of the present invention obtains dark, and its from top to bottom transverse width all reach unanimity, there is not the problem that the sidewall of prior art presents waveform or sidewall and presents taper.Further, the present invention, while taking into account silicon through hole/silicon trench 400 pattern, maintains higher etching speed.
Although content of the present invention has done detailed introduction by above preferred embodiment, will be appreciated that above-mentioned description should not be considered to limitation of the present invention.After those skilled in the art have read foregoing, for multiple amendment of the present invention and substitute will be all apparent.Therefore, protection scope of the present invention should be limited to the appended claims.In addition, any Reference numeral in claim should be considered as the claim involved by restriction; " comprise " word and do not get rid of device unlisted in other claim or specification or step; The word such as " first ", " second " is only used for representing title, and does not represent any specific order.
Claims (10)
1. a dark silicon etching method, is characterized in that, described lithographic method comprises the steps:
Anisotropic etch step, the first reacting gas is provided to etch silicon material layer under action of plasma, and be etched to certain depth, to expose an etching interface, described etching interface comprises sidewall, described first reacting gas comprises etching gas and sidewall protective gas, and described sidewall protective gas is for compensating described etching gas to the corrasion in a lateral direction of this sidewall;
Sidewall protection step, provides the second reacting gas, and under action of plasma, form side wall protective layer at the sidewall of described etching interface, be attached to the sidewall surfaces of described etching interface, described second reacting gas comprises sidewall protective gas;
Anisotropic etch step described in alternate cycles and sidewall protection step, until etching arrives target depth.
2. lithographic method according to claim 1, is characterized in that, the time of implementation ratio of described anisotropic etch step and sidewall protection step is for being greater than 5:1.
3. lithographic method according to claim 2, is characterized in that, the time of implementation of described anisotropic etch step and sidewall protection step, than for being greater than 5:1, is less than 20:1.
4. lithographic method according to claim 2, is characterized in that, the etching gas that described first reacting gas comprises is SF
6.
5. lithographic method according to claim 2, is characterized in that, the sidewall protective gas that described first reacting gas comprises comprises C
4f
8, O
2, SiF
4.
6. the lithographic method according to claim 4 or 5, is characterized in that, the etching gas in described first reacting gas and the ratio of sidewall protective gas are 4:1 to 2:1.
7. lithographic method according to claim 4, is characterized in that, the sidewall protective gas that described second reacting gas comprises comprises C
4f
8or O
2.
8. lithographic method according to claim 1, is characterized in that, is also provided with mask layer or photoresist layer above described silicon material layer.
9. lithographic method according to claim 1, is characterized in that, anisotropic etch step described in alternate cycles and sidewall protection step, until etching arrives target depth to form silicon through hole or groove.
10. lithographic method according to claim 1, is characterized in that, described lithographic method carries out in inductance coupling high type plasma etch chamber room.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410221761.XA CN105097440B (en) | 2014-05-23 | 2014-05-23 | A kind of deep silicon etching method |
| TW103143959A TWI570803B (en) | 2014-05-23 | 2014-12-16 | A deep silicon etch method |
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| CN201410221761.XA CN105097440B (en) | 2014-05-23 | 2014-05-23 | A kind of deep silicon etching method |
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| CN105097440A true CN105097440A (en) | 2015-11-25 |
| CN105097440B CN105097440B (en) | 2018-02-09 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020215183A1 (en) * | 2019-04-22 | 2020-10-29 | Applied Materials, Inc. | Methods for etching a material layer for semiconductor applications |
| CN114477077A (en) * | 2022-02-11 | 2022-05-13 | 丹东华顺电子有限公司 | Silicon deep groove etching method |
| CN116598254A (en) * | 2023-07-19 | 2023-08-15 | 粤芯半导体技术股份有限公司 | Method for forming deep trench isolation structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4521275A (en) * | 1982-07-06 | 1985-06-04 | Texas Instruments Incorporated | Plasma etch chemistry for anisotropic etching of silicon |
| US5078833A (en) * | 1989-07-21 | 1992-01-07 | Sony Corporation | Dry etching method |
| WO2014035820A1 (en) * | 2012-08-27 | 2014-03-06 | Applied Materials, Inc. | Method of silicon etch for trench sidewall smoothing |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101948494B (en) * | 2010-09-14 | 2012-11-21 | 河北华荣制药有限公司 | Method for extracting cobamamide |
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2014
- 2014-05-23 CN CN201410221761.XA patent/CN105097440B/en active Active
- 2014-12-16 TW TW103143959A patent/TWI570803B/en active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4521275A (en) * | 1982-07-06 | 1985-06-04 | Texas Instruments Incorporated | Plasma etch chemistry for anisotropic etching of silicon |
| US4521275B1 (en) * | 1982-07-06 | 1997-10-14 | Texas Instruments Inc | Plasma etch chemistry for anisotropic etching of silicon |
| US5078833A (en) * | 1989-07-21 | 1992-01-07 | Sony Corporation | Dry etching method |
| WO2014035820A1 (en) * | 2012-08-27 | 2014-03-06 | Applied Materials, Inc. | Method of silicon etch for trench sidewall smoothing |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020215183A1 (en) * | 2019-04-22 | 2020-10-29 | Applied Materials, Inc. | Methods for etching a material layer for semiconductor applications |
| CN114477077A (en) * | 2022-02-11 | 2022-05-13 | 丹东华顺电子有限公司 | Silicon deep groove etching method |
| CN116598254A (en) * | 2023-07-19 | 2023-08-15 | 粤芯半导体技术股份有限公司 | Method for forming deep trench isolation structure |
| CN116598254B (en) * | 2023-07-19 | 2023-09-29 | 粤芯半导体技术股份有限公司 | Method for forming deep trench isolation structure |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201545232A (en) | 2015-12-01 |
| CN105097440B (en) | 2018-02-09 |
| TWI570803B (en) | 2017-02-11 |
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Address after: 201201 No. 188 Taihua Road, Jinqiao Export Processing Zone, Pudong New Area, Shanghai Patentee after: Medium and Micro Semiconductor Equipment (Shanghai) Co., Ltd. Address before: 201201 No. 188 Taihua Road, Jinqiao Export Processing Zone, Pudong New Area, Shanghai Patentee before: Advanced Micro-Fabrication Equipment (Shanghai) Inc. |