CN105428277A - Method for improving wafer yield in flash memory product manufacturing - Google Patents
Method for improving wafer yield in flash memory product manufacturing Download PDFInfo
- Publication number
- CN105428277A CN105428277A CN201510765546.0A CN201510765546A CN105428277A CN 105428277 A CN105428277 A CN 105428277A CN 201510765546 A CN201510765546 A CN 201510765546A CN 105428277 A CN105428277 A CN 105428277A
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- China
- Prior art keywords
- flash memory
- silicon chip
- yield
- product manufacturing
- temperature
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67248—Temperature monitoring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
Abstract
The present invention relates to the field of flash memory product manufacturing and particularly relates to a method for improving wafer yield in flash memory product manufacturing. In the field wet generation process in gate oxide layer growth, the temperature of a probe at a most edge is reduced for t relative to process temperature, a test shows that an anti-deformation effect is best when t is below 7 DEG C, especially in 6 to 7 DEG C. Through simple control, the deformation of a wafer in the flash memory product manufacturing is effectively reduced, the yield of the wafer is improved, and by using the method, the yield of the wafer is improved by 7%.
Description
Technical field
The present invention relates to flash memory products and manufacture field, be specifically related to a kind of method improving silicon chip yield when flash memory products manufactures.
Background technology
For flash memory products, grid oxic horizon is vital core processing procedure in whole technological process, and the uniformity of temperature is its key index in grid oxic horizon growth course, it decides the quality superposed in follow-up lithographic process, also defect and the product yield of product silicon chip edge is affected, ISSG (on-the-spot moisture generation) is under the environment of low-voltage high-temperature, pass into certain hydrogen, oxygen, the technique of silicon dioxide is generated through series of chemical silica atom, silicon chip is under the heating of bulb, control temperature is carried out by 7 probes, and then control the uniformity of growth.Because silicon chip edge the most easily produces deformation, the probe when most edge is heated too high, and silicon chip produces plastic deformation, and after technique completes, silicon chip is resilient not.
Summary of the invention
The technical scheme that the present invention solves the problems of the technologies described above is as follows:
A method for silicon chip yield is improved, in the on-the-spot moisture generating process when gate oxidation layer growth, within the probe temperature at most edge is 7 DEG C relative to the scope that technological temperature reduces uniform temperature t, described t when flash memory products manufactures.
The invention has the beneficial effects as follows: this method, by simple control, effectively reduces the deformation of silicon chip when flash memory products manufactures, improves the yield of silicon chip, and after using the method, the yield of silicon chip improves 7%.
On the basis of technique scheme, the present invention can also do following improvement.
Further, described t is 6 DEG C ~ 7 DEG C.
The invention has the beneficial effects as follows: when most edge probe temperature reduces by 6 DEG C ~ 7 DEG C, effect is best.
Accompanying drawing explanation
Fig. 1 is the position view of most edge probe in the on-the-spot moisture generating process of the present invention.
In figure, 1 probe representing most edge.
Embodiment
Be described principle of the present invention and feature below in conjunction with accompanying drawing, example, only for explaining the present invention, is not intended to limit scope of the present invention.
A kind of method improving silicon chip yield when flash memory products manufactures, in on-the-spot moisture generating process when gate oxidation layer growth, the probe temperature at most edge is reduced uniform temperature t relative to technological temperature, effectively can reduce the distortion of silicon chip, improve the yield of silicon chip, as shown in table 1, in form, T7 represents the probe at most edge, and the basal temperature of T7 is the temperature of this operation, + 3 DEG C represent that the temperature of most edge probe increases by 3 degrees Celsius, by that analogy.
From form, T7 compare technological temperature reduce by 6 ~ 9 DEG C, deformation is minimum, but silicon chip edge temperature reduces too many, makes silicon chip edge oxide layer growth slack-off, lower thickness, the final puncture voltage affecting chip and the read-write storing data, therefore reduce the temperature 6 ~ 7 DEG C of silicon chip most edge probe, can make the minimum deformation of silicon chip, the oxide layer at edge also can meet technique needs.
As shown in Figure 1, be the particular location of T7 in on-the-spot moisture generating process.
Subsequent technique photoetching is very strict to the deformation requirements of silicon chip, if silicon chip deformation is serious, board is often reported to the police, and reduces production efficiency, proves through test, before using this method, the non-deformed area of silicon chip is 91.31%, and after using this method, the non-deformed area of silicon chip is 98.79%, the yield of silicon chip improves 7%, improves the just product efficiency of subsequent technique photoetching simultaneously.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (2)
1. one kind is improved the method for silicon chip yield when flash memory products manufactures, it is characterized in that, in on-the-spot moisture generating process when gate oxidation layer growth, within the probe temperature at most edge is 7 DEG C relative to the scope that technological temperature reduces uniform temperature t, described t.
2. the method improving silicon chip yield when flash memory products manufactures according to claim 1, it is characterized in that, described t is 6 DEG C-7 DEG C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510765546.0A CN105428277A (en) | 2015-11-11 | 2015-11-11 | Method for improving wafer yield in flash memory product manufacturing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510765546.0A CN105428277A (en) | 2015-11-11 | 2015-11-11 | Method for improving wafer yield in flash memory product manufacturing |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105428277A true CN105428277A (en) | 2016-03-23 |
Family
ID=55506386
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510765546.0A Pending CN105428277A (en) | 2015-11-11 | 2015-11-11 | Method for improving wafer yield in flash memory product manufacturing |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105428277A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01255228A (en) * | 1988-04-05 | 1989-10-12 | Nec Corp | Gate-oxide-film forming method |
| CN102024692A (en) * | 2009-09-23 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of oxide layer between splitting grids |
| CN102386132A (en) * | 2010-08-27 | 2012-03-21 | 中芯国际集成电路制造(上海)有限公司 | Method of reducing alignment tolerance and special equipment thereof applied in heat treatment process |
-
2015
- 2015-11-11 CN CN201510765546.0A patent/CN105428277A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01255228A (en) * | 1988-04-05 | 1989-10-12 | Nec Corp | Gate-oxide-film forming method |
| CN102024692A (en) * | 2009-09-23 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of oxide layer between splitting grids |
| CN102386132A (en) * | 2010-08-27 | 2012-03-21 | 中芯国际集成电路制造(上海)有限公司 | Method of reducing alignment tolerance and special equipment thereof applied in heat treatment process |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160323 |
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| RJ01 | Rejection of invention patent application after publication |