CN105428252A - 功率型大电流器件装片工艺 - Google Patents

功率型大电流器件装片工艺 Download PDF

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CN105428252A
CN105428252A CN201510976871.1A CN201510976871A CN105428252A CN 105428252 A CN105428252 A CN 105428252A CN 201510976871 A CN201510976871 A CN 201510976871A CN 105428252 A CN105428252 A CN 105428252A
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徐青青
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ZHANGZHOU YINHESHIJI MICRO-ELECTRONIC Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4842Mechanical treatment, e.g. punching, cutting, deforming, cold welding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

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Abstract

本发明公开了一种功率型大电流器件装片工艺,该工艺采用具有升温区域、温度稳定区域和降温区域的温度轨道,并且该工艺的步骤如下:(a)将器件框架送入升温区域进行加热处理;(b)接着将器件框架送入温度稳定区域,并将焊料点焊在器件框架的PAD区域上;(c)在温度稳定区域内,采用压模头将器件框架的PAD区域上的焊料修整为配合芯片尺寸的具有一定高度的“口”字形结构;(d)在温度稳定区域内,将芯片安放于器件框架的PAD区域上,使芯片背面的金属与焊料在温度环境下共熔形成合金,从而得到半成品;(e)将半成品送入降温区域,在降温区域内,芯片和器件框架之间的合金固化。本发明能够提高产品制程质量以及可靠性水平,降低客户端失效比例,提高使用寿命。

Description

功率型大电流器件装片工艺
技术领域
本发明涉及一种功率型大电流器件装片工艺。
背景技术
目前,随着功率型大电流器件技术的不断进步,要求功率型大电流器件的尺寸越来越小,但是处理速度和功率要求越来越高。但是,现有功率型大电流器件的芯片面积大于3.0mm时,其封装芯片面积较大,装片后芯片容易倾斜,导致装片不平整、散热不均匀等影响后道加工以及客户端应用风险的不良现象。
发明内容
本发明所要解决的技术问题是克服现有技术的缺陷,提供一种功率型大电流器件装片工艺,它能够提高产品制程质量以及可靠性水平,降低客户端失效比例,提高使用寿命。
为了解决上述技术问题,本发明的技术方案是:一种功率型大电流器件装片工艺,该工艺采用具有升温区域、温度稳定区域和降温区域的温度轨道,并且该工艺的步骤如下:
(a)将器件框架送入升温区域进行加热处理;
(b)接着将器件框架送入温度稳定区域,并将焊料点焊在器件框架的PAD区域上;
(c)在温度稳定区域内,采用压模头将器件框架的PAD区域上的焊料修整为配合芯片尺寸的具有一定高度的“口”字形结构;
(d)在温度稳定区域内,将芯片安放于器件框架的PAD区域上,使芯片背面的金属与焊料在温度环境下共熔形成合金,从而得到半成品;
(e)将半成品送入降温区域,在降温区域内,芯片和器件框架之间的合金固化,从而使芯片和框架之间形成牢固的电性接触。
进一步,在步骤(b)中,所述焊料的组分和各组分质量份如下:铅:92.5%;锡:5%;银:2.5%。
进一步提供了一种在温度稳定区域内最合理的温度,所述温度轨道在温度稳定区域内的温度为390℃。
进一步为了合理控制焊料的厚度,防止焊料过薄造成的产品分层和散热不均的问题,在所述步骤(c)中,修整后的焊料的高度范围为35μm~75μm。
进一步为了避免顶针顶出过程中将顶针芯片顶破或者吸片歪斜造成装片后芯片高低倾斜,从而引起焊料厚度不均匀导致局部散热过高引起的失效现象,在所述步骤(d)中,首先采用多顶针顶出机构将芯片顶起,然后采用具有真空吸附功能的焊头吸取芯片,再采用所述焊头将芯片输送至器件框架的PAD区域上。
进一步为了防止硬度过高刺破芯片的现象,所述多顶针顶出机构的顶针的针头部分由硬质塑料制成。
进一步,所述多顶针顶出机构中的顶针设置有四个。
进一步为了防止产品在高温状态下氧化,从而影响塑封料与框架的结合牢度,降低分层风险,在所述步骤(b)、步骤(c)和步骤(d)的过程中,温度稳定区域的温度轨道中灌入氢气和氮气的混合气体。
进一步,所述混合气体中含有的氢气体积百分比为3%~5%,其余为氮气,总计100%。
采用了上述技术方案后,本发明具有以下的有益效果:
1、本发明采用了压模头对焊料进行修整,使其焊料厚度均匀,使散热均衡,避免了芯片高低倾斜的现象,从而增大了功率型大电流器件能够装片的最大芯片尺寸,提高了功率大电流器件的散热能力和可靠性,提高了器件的使用寿命,降低了客户端失效比例,将封装的功率能力提升到了最大。
2、本发明可采用压模头将焊料修整为需要尺寸的“口”字形结构,该焊料四边相等形成正方形,或相对的两边相等,相邻的两边不等,从而形成长方形,将焊料的高度限制在35μm~75μm,防止了焊料过薄造成的产品分层、散热不均匀的问题。
3、本发明采用多顶针顶出机构,提高了芯片顶起的水平度,避免了顶针顶出过程中将芯片顶破或吸片歪斜造成装片后芯片高低倾斜,从而引起焊料厚度不均匀,导致局部散热过高引起的失效现象。
4、将顶针的针头部分更改为硬质塑料,防止了金属硬度过高刺破芯片的现象。
5、温度稳定区域内向温度轨道内灌入的氢氮混合气体,防止了产品在高温状态下的氧化,影响塑封料与框架的结合牢度,降低了分层风险。
附图说明
图1为本发明的功率型大电流器件装片工艺最后成品的产品结构图;
其中,1为器件框架;2为器件框架上的PAD区域上的成形后的焊料;3为芯片。
具体实施方式
为了使本发明的内容更容易被清楚地理解,下面根据具体实施例并结合附图,对本发明作进一步详细的说明。
如图1所示,一种功率型大电流器件装片工艺,该工艺采用具有升温区域、温度稳定区域和降温区域的温度轨道,并且该工艺的步骤如下:
(a)将器件框架1送入升温区域进行加热处理;
(b)接着将器件框架1送入温度稳定区域,并将焊料点焊在器件框架1的PAD区域上;焊料的点焊长度可以自动选择;
(c)在温度稳定区域内,采用压模头将器件框架1的PAD区域上的焊料修整为配合芯片尺寸的具有一定高度的“口”字形结构;
(d)在温度稳定区域内,将芯片安放于器件框架1的PAD区域上,使芯片3背面的金属与焊料在温度环境下共熔形成合金,从而得到半成品;
(e)将半成品送入降温区域,在降温区域内,芯片3和器件框架1之间的合金固化,从而使芯片3和器件框架1之间形成牢固的电性接触。
在步骤(b)中,所述焊料的组分和各组分质量份如下:铅:92.5%;锡:5%;银:2.5%。
进一步,所述温度轨道在温度稳定区域内的温度为390℃。
在所述步骤(c)中,修整后的焊料的高度范围为35μm~75μm。
在所述步骤(d)中,首先采用多顶针顶出机构将芯片顶起,然后采用具有真空吸附功能的焊头吸取芯片,再采用所述焊头将芯片3输送至器件框架1的PAD区域上。
所述多顶针顶出机构的顶针的针头部分由硬质塑料制成,但是不限于此。
所述多顶针顶出机构中的顶针设置有四个,但是不限于此。
在所述步骤(b)、步骤(c)和步骤(d)的过程中,温度稳定区域的温度轨道中灌入氢气和氮气的混合气体。
所述混合气体中含有的氢气体积百分比为3%~5%,其余为氮气,总计100%。
本发明具有以下的有益效果:
1、本发明采用了压模头对焊料进行修整,使其焊料厚度均匀,使散热均衡,避免了芯片高低倾斜的现象,从而增大了功率型大电流器件能够装片的最大芯片尺寸,提高了功率大电流器件的散热能力和可靠性,提高了器件的使用寿命,降低了客户端失效比例,将封装的功率能力提升到了最大。
2、本发明可采用压模头将焊料修整为需要尺寸的“口”字形结构,该焊料四边相等形成正方形,或相对的两边相等,相邻的两边不等,从而形成长方形,将焊料的高度限制在35μm~75μm,防止了焊料过薄造成的产品分层、散热不均匀的问题。
3、本发明采用多顶针顶出机构,提高了芯片顶起的水平度,避免了顶针顶出过程中将芯片顶破或吸片歪斜造成装片后芯片高低倾斜,从而引起焊料厚度不均匀,导致局部散热过高引起的失效现象。
4、将顶针的针头部分更改为硬质塑料,防止了金属硬度过高刺破芯片的现象。
5、温度稳定区域内向温度轨道内灌入的氢氮混合气体,防止了产品在高温状态下的氧化,影响塑封料与框架的结合牢度,降低了分层风险。
以上所述的具体实施例,对本发明解决的技术问题、技术方案和有益效果进行了进一步详细说明,所应理解的是,以上所述仅为本发明的具体实施例而已,并不用于限制本发明,凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。

Claims (9)

1.一种功率型大电流器件装片工艺,其特征在于,该工艺采用具有升温区域、温度稳定区域和降温区域的温度轨道,并且该工艺的步骤如下:
(a)将器件框架送入升温区域进行加热处理;
(b)接着将器件框架送入温度稳定区域,并将焊料点焊在器件框架的PAD区域上;
(c)在温度稳定区域内,采用压模头将器件框架的PAD区域上的焊料修整为配合芯片尺寸的具有一定高度的“口”字形结构;
(d)在温度稳定区域内,将芯片安放于器件框架的PAD区域上,使芯片背面的金属与焊料在温度环境下共熔形成合金,从而得到半成品;
(e)将半成品送入降温区域,在降温区域内,芯片和器件框架之间的合金固化,从而使芯片和器件框架之间形成牢固的电性接触。
2.根据权利要求1所述的功率型大电流器件装片工艺,其特征在于:在步骤(b)中,所述焊料的组分和各组分质量份如下:铅:92.5%;锡:5%;银:2.5%。
3.根据权利要求1所述的功率型大电流器件装片工艺,其特征在于:所述温度轨道在温度稳定区域内的温度为390℃。
4.根据权利要求1所述的功率型大电流器件装片工艺,其特征在于:在所述步骤(c)中,修整后的焊料的高度范围为35μm~75μm。
5.根据权利要求1所述的功率型大电流器件装片工艺,其特征在于:在所述步骤(d)中,首先采用多顶针顶出机构将芯片顶起,然后采用具有真空吸附功能的焊头吸取芯片,再采用所述焊头将芯片输送至器件框架的PAD区域上。
6.根据权利要求5所述的功率型大电流器件装片工艺,其特征在于:所述多顶针顶出机构的顶针的针头部分由硬质塑料制成。
7.根据权利要求5所述的功率型大电流器件装片工艺,其特征在于:所述多顶针顶出机构中的顶针设置有四个。
8.根据权利要求1所述的功率型大电流器件装片工艺,其特征在于:在所述步骤(b)、步骤(c)和步骤(d)的过程中,温度稳定区域的温度轨道中灌入氢气和氮气的混合气体。
9.根据权利要求8所述的功率型大电流器件装片工艺,其特征在于:所述混合气体中含有的氢气体积百分比为3%~5%,其余为氮气,总计100%。
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