CN105428237B - Nmos transistor and forming method thereof - Google Patents
Nmos transistor and forming method thereof Download PDFInfo
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- CN105428237B CN105428237B CN201410431676.6A CN201410431676A CN105428237B CN 105428237 B CN105428237 B CN 105428237B CN 201410431676 A CN201410431676 A CN 201410431676A CN 105428237 B CN105428237 B CN 105428237B
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Abstract
A kind of NMOS transistor and forming method thereof, the wherein forming method of NMOS transistor, including：Semiconductor substrate is provided, pseudo- grid are formed in the semiconductor substrate, side wall, the interior formation carbon silicon source drain region of semiconductor substrate of the puppet grid and side wall both sides are formed on the side wall of the puppet grid；Dielectric layer is formed on the semiconductor substrate, and the surface of the dielectric layer and the flush of puppet grid are etched back to the pseudo- grid of removal segment thickness, expose the part surface of side wall side wall；The side wall of etching removal Partial Height；Remaining pseudo- grid are removed, form the groove of " T " font, the groove of " T " font exposes the surface of semiconductor substrate；Form the metal gates of the groove of full " T " font of filling.The opening width that the method for the present invention increases the groove to be formed prevents from forming defect in metal gates when forming metal gates.
Description
Technical field
The present invention relates to field of semiconductor fabrication, more particularly to a kind of NMDOS transistors and forming method thereof.
Background technology
Smaller and smaller with the characteristic size of semiconductor devices, area occupied by corresponding core devices also accordingly reduces,
The energy density of unit area is caused substantially to increase, electrical leakage problems more highlight, and power consumption also increases therewith.Therefore 45 nanometers with
Under technique in, it is traditional to have encountered bottleneck by the technique of the gate dielectric layer of material of silica, cannot be satisfied semiconductor
The technological requirement of device；To solve above-mentioned bottleneck, high-k (high k is used at present：K values are more than or equal to 3.5) dielectric material
As gate dielectric layer, then, it is that the grid of material is leaked electricity with reducing to be formed using metal, and power consumption is made to be well controlled.
Since stress can change the energy gap and carrier mobility of silicon materials, semiconductor device is improved by stress
The performance of part becomes more and more common means.Specifically, by suitable control stress, carrier (NMOS device can be improved
In electronics, the hole in PMOS device) mobility, and then improve driving current, semiconductor devices greatlyd improve with this
Performance.
Fig. 1~Fig. 4 is the structural schematic diagram of the forming process of the NMOS transistor with embedded stress source-drain area.
With reference to figure 1, semiconductor substrate 100 is provided, forms pseudo- grid structure, the puppet grid in the semiconductor substrate 100
Structure includes the silicon oxide layer 101 being located in semiconductor substrate and the pseudo- grid 102 on 101 surface of silicon oxide layer.
It is also formed with side wall 103 in the sidewall surfaces of dummy gate structure, is mask etching with the pseudo- grid and side wall 103
The semiconductor substrate 100 of 103 both sides of pseudo- grid 102 and side wall forms groove in the semiconductor substrate 100；In the groove
Middle filling silicon carbide layer forms carbon silicon source/drain region 108, raceway groove of the carbon/silicon source drain region 108 to the transistor being subsequently formed
Area provides tensile stress, improves the mobility of the carrier (electronics) of trench area；It is formed and covers the semiconductor substrate 100 and side
The dielectric layer 104 of 103 sidewall surfaces of wall, the surface of the dielectric layer 104 are flushed with the surface of pseudo- grid 102.
With reference to figure 2, dummy gate structure is removed, forms the second groove 105, second groove 105 exposes semiconductor
The surface of substrate 100.
With reference to figure 3, in the side wall and bottom surface and 104 surface shape of dielectric layer of second groove 105 (with reference to figure 2)
At high-K gate dielectric material layer；Metal layer, full second groove of metal layer filling are formed on the high-K gate dielectric material layer；
Using the high-K gate dielectric material layer and metal layer on 104 surface of chemical mechanical milling tech removal dielectric layer, in the second groove side
High-K gate dielectric layer is formed in wall and bottom surface, the metal gates include the high K grid positioned at the second recess sidewall and bottom
Dielectric layer 106 forms metal gate electrode 107, full second groove of the filling of metal gate electrode 107, institute on high-K gate dielectric layer 106
It states metal gate electrode 107 and high-K gate dielectric layer 106 constitutes metal gate structure.
But the performance of the NMOS transistor of prior art formation is still to be improved.
Invention content
Problems solved by the invention is how to improve the performance to form NMOS transistor.
To solve the above problems, the present invention provides a kind of forming methods of NMOS transistor, including：Semiconductor lining is provided
Bottom is formed with pseudo- grid in the semiconductor substrate, is formed with side wall on the side wall of the puppet grid, the puppet grid and side wall both sides
Carbon silicon source drain region is formed in semiconductor substrate；Dielectric layer, surface and the puppet of the dielectric layer are formed on the semiconductor substrate
The flush of grid is etched back to the pseudo- grid of removal segment thickness, exposes the part surface of side wall side wall；Etching removal part is high
The side wall of degree；Remaining pseudo- grid are removed, the groove of " T " font is formed；Form the metal gates of the groove of full " T " font of filling.
Optionally, the side wall includes：Positioned at the first side wall of pseudo- grid side wall, positioned at the second of the first side wall sidewall surfaces
Side wall, positioned at the third side wall of the second side wall sidewall surfaces, first side wall and the material of the second side wall and third side wall are not
It is identical；The pseudo- grid of part are etched back to, the partial sidewall of the first side wall is exposed；First side of etching removal Partial Height
Wall.
Optionally, before forming pseudo- grid, high-K gate dielectric layer is formed on the semiconductor substrate, is situated between in the high K grid
Function metal layer is formed on matter layer.
Optionally, the forming process in the pseudo- grid and carbon silicon source drain region is：High-K gate dielectric material is formed on a semiconductor substrate
The bed of material；Functional metal materials layer is formed on high-K gate dielectric material layer；Polysilicon layer is formed on functional metal materials layer；
Patterned hard mask layer is formed on the polysilicon layer；Using the patterned hard mask layer as mask, it is sequentially etched described
Polysilicon layer, functional metal materials layer and high-K gate dielectric material layer form high-K gate dielectric layer, are located at height on a semiconductor substrate
Function metal layer on K gate dielectric layers and the pseudo- grid on function metal layer；The is formed in the sidewall surfaces of the pseudo- grid
One side wall；Using the pseudo- grid and the first side wall as mask, shallow Doped ions injection is carried out, half in pseudo- grid and the first side wall both sides
Shallow doped region is formed in conductor substrate；The second side wall is formed in the first side wall sidewall surfaces, in the second side wall side wall table
Third side wall is formed on face；Using the third side wall and pseudo- grid as mask, partly leading for the pseudo- grid and third side wall both sides is etched
Body substrate forms the second groove in semiconductor substrate；Form the carbon silicon source drain region of full second groove of filling.
Optionally, the forming process of dielectric layer is：Form the covering pseudo- grid, the first side wall, the second side wall, third side
Wall, carbon silicon source drain region and semiconductor substrate surface layer of dielectric material；Certain media material is removed using chemical mechanical milling tech
The bed of material and patterned hard mask layer expose the top surface of pseudo- grid, form dielectric layer.
Optionally, the material of first side wall is the nitride of low-k, and the third spacer material is Gao Jie
The nitride of matter constant.
Optionally, the material of the nitride of low-k is the silicon nitride of carbon dope, the nitride of the high dielectric constant
Material for silicon nitride, second side wall is silica.
Optionally, the first side wall of Partial Height is removed using plasma etching industrial.
Optionally, the plasma etching uses etching gas for N2, N2Flow be 50sccm-1000sccm, chamber temperature
Degree is 0-100 DEG C, source power 100W-1000W, bias power 0-300W.
Optionally, the etching gas that the plasma etching uses is CH2F2、CHF3、H2、N2, CH2F2Flow be 5-
100sccm, CHF3Flow be 5-100sccm, H2Flow be 10-500sccm, N2Flow be 50-1000sccm, chamber
Temperature is 0-100 DEG C, source power 100w-1000W, bias power 0-300W.
Optionally, the etching gas that the plasma etching uses is C4F8、C4F6、Ar、O2, C4F8Flow be 5-
100sccm, C4F6Flow be 5-100sccm, the flow of Ar is 50-500sccm, O2Flow be 5-100scc, chamber temp
It is 0-100 DEG C, source power 100w-1000W, bias power 0-300W.
Optionally, the plasma etching is cycle plasma etching, including deposition step alternately and etching step
Suddenly, the gas of the deposition step material is C4F8, the gas that etch step uses is Ar, C4F8Flow be 5-100sccm,
The flow of Ar is 50-500sccm, source power 100w-1000W, bias power 0-300W.
Optionally, the material of the function metal layer is TiN, TaN, TiAl, TaC, TaSiN, TiAlN.
Optionally, remaining pseudo- grid are removed, the groove of " T " font is formed, the groove of " T " font exposes function gold
Belong to the surface of layer, removes remaining pseudo- grid and use plasma etching industrial, the etching gas that the plasma etching industrial uses
For HBr and O2。
Optionally, plasma cleaning is carried out to the function metal layer of bottom portion of groove.
Optionally, the gas that the plasma cleaning uses is N2, N2Flow be 50-1000sccm, chamber temp 0-
100 DEG C, source power 100-1000W, bias power 0-300W.
Optionally, the plasma cleaning includes deposition step alternately and etch step, the deposition step material
The gas of material is C4F8, the gas that etch step uses is Ar, C4F8Flow be 5-200sccm, the flow of Ar is 50-
1000sccm, source power 100-1000W, bias power 0-300W.
Optionally, the material of first side wall is the nitride of high-k, and the third spacer material is low Jie
First side wall of the nitride of matter constant, etching removal Partial Height uses wet etching, the etching solution that wet etching uses
For concentrated phosphoric acid.
The present invention also provides a kind of NMOS transistors, including：Semiconductor substrate is formed with carbon in the semiconductor substrate
Silicon source/drain region；The dielectric layer of the semiconductor substrate is covered, is had in the dielectric layer between exposing carbon silicon source/drain region
The groove of semiconductor substrate；Positioned at the side wall of groove both sides sidewall surfaces, the top surface of the side wall is less than the table of dielectric layer
Face；" T " font metal gates of the full groove of filling, the metal gates cover the side coping and sidewall surfaces, and gold
The top surface for belonging to grid is flushed with the surface of dielectric layer.
Optionally, the side wall includes：Positioned at the third side wall on recess sidewall surface, positioned at third side wall sidewall surfaces
Second side wall, positioned at the first side wall of the second side wall sidewall surfaces, the material of first side wall and the second side wall and third side wall
Material differs, and the top surface of the first side wall is less than the surface of dielectric layer, the top surface of the second side wall and third side wall with
Dielectric layer surface flushes, and " T " font metal gates cover the side wall and top surface of first side wall.
Compared with prior art, technical scheme of the present invention has the following advantages：
The forming method of NMOS transistor of the present invention removes the side wall of Partial Height so that side wall after forming dielectric layer
Top surface be less than the surface of dielectric layer, after the pseudo- grid of removal, so as to form the groove of " T " font, " T " font it is recessed
The width of the opening of slot can be more than the width of bottom, the width of the slot opening formed after the pseudo- grid of removal compared with the prior art
It spends, the width of the opening of the groove formed in the embodiment of the present invention is broadening, therefore even if the carbon silicon source formed in semiconductor substrate
The side wall and dielectric layer that drain region pair comes close to or in contact with its (carbon silicon source drain region) will produce outside tensile stress so that side wall and
Dielectric layer can be tilted to the groove direction formed after pseudo- grid is removed, the groove formed after the pseudo- grid of removal in the embodiment of the present invention
Opening width still can be more than the width for removing the groove formed after pseudo- grid in the prior art, thus when forming metal gates,
Prevent void defects.
Further, the side wall includes：Positioned at the first side wall of pseudo- grid side wall, positioned at the second of the first side wall sidewall surfaces
Side wall, positioned at the third side wall of the second side wall sidewall surfaces, on the one hand, first side wall can be used as when forming shallow doped region
Mask, the second side wall and third side wall form mask when the second groove as subsequent etching semiconductor substrate, on the other hand,
By removing the first side wall of Partial Height, after removing remaining pseudo- grid, keep the groove to be formed T-shaped, to increase
The width of slot opening, in addition the material of first side wall be subsequently formed the material of the second side wall and third side wall not phase
Together, when being subsequently etched back to the first side wall of removal Partial Height so that be much larger than the etch rate of the first side wall to second
The etch rate of side wall and third side wall.
Further, after forming groove, plasma cleaning is carried out with remove function metal to bottom portion of groove function metal layer
The metal oxide that layer surface is formed, prevents metal oxide from being had an impact to the adjustment effect of the work function of function metal layer.
Description of the drawings
Fig. 1~Fig. 3 is the cross-sectional view of prior art NMOS transistor forming process；
Fig. 4~Figure 13 is the cross-sectional view of the forming process of NMOS transistor of the embodiment of the present invention.
Specific implementation mode
As described in the background art, the performance for the NMOS transistor that the prior art is formed is still to be improved, for example, with device
The continuous reduction of size when forming metal gates, is easy when filling metal into the second groove in the metal gate electrode of formation
Void defects 109 are generated, are specifically please referred to Fig.3.
The study found that please referring to Fig.2 and Fig. 3, in the manufacturing process of NMOS transistor, it is recessed to form second in the pseudo- grid of removal
After slot 105, the side wall 103 of both sides is easy to tilt to the direction of the second groove 105 so that the width of the opening of the second groove 105
It can reduce (width that the width on 105 top of the second groove is less than lower part), therefore form the gold for filling full second groove 105
When belonging to layer, metal material is easy to block the opening of the second groove 105 so that the metal gate electrode 107 formed in the second groove 105
In easy to produce void defects 109.Further study show that side wall 103 is the reason of inclination to 105 direction of the second groove：
In NMOS transistor, in order to improve the mobility of carrier (electronics), the semiconductor substrate 100 in 103 both sides of pseudo- grid and side wall
Interior formation carbon silicon source/drain region 108, carbon silicon source/drain region 108 generate tensile stress to channel region, and carbon silicon source/drain region 108 is right
The dielectric layer 104 and side wall 103 that are come close to or in contact with its (carbon silicon source drain region) can also have the effect of outside tensile stress 11,
In addition a side surface of side wall 103 is hanging (being the second groove 105 between side wall 103), thus 103 He of side wall of upper part
Dielectric layer 104 is easy to tilt to the direction of the second groove 105 so that the opening of the second groove 105 reduces.
An embodiment of the present invention provides a kind of forming methods of NMOS transistor thus, including：After forming dielectric layer, go
Except the side wall of Partial Height so that the top surface of side wall is less than the surface of dielectric layer, after the pseudo- grid of removal, so as to be formed
The groove of " T " font, the width of the opening of the groove of " T " font can be more than the width of bottom, remove compared with the prior art
The width of the width of the slot opening formed after pseudo- grid, the opening of the groove formed in the embodiment of the present invention is broadening, thus even if
The side wall and dielectric layer that the carbon silicon source drain region pair formed in semiconductor substrate comes close to or in contact with its (carbon silicon source drain region) will produce
Outside tensile stress so that side wall and dielectric layer can be tilted to the groove direction formed after pseudo- grid is removed, the embodiment of the present invention
In the opening width of groove that is formed after the pseudo- grid of removal still can be more than and remove the groove formed after pseudo- grid in the prior art
Width, to when forming metal gates, prevent void defects.
To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.When describing the embodiments of the present invention, for purposes of illustration only, schematic diagram can disobey general proportion
Make partial enlargement, and the schematic diagram is example, should not limit the scope of the invention herein.In addition, in reality
In making should include length, width and depth three-dimensional space.
Fig. 4~Figure 13 is the cross-sectional view of the forming process of NMOS transistor of the embodiment of the present invention.
With reference to figure 4, semiconductor substrate 200 is provided, pseudo- grid 202 are formed in the semiconductor substrate 200.
The material of platform of the semiconductor substrate 200 as subsequent technique, the semiconductor substrate 200 is silicon, described
In semiconductor substrate 200 also well region is formed doped with foreign ion.It is miscellaneous doped with p-type in this implementation semiconductor substrate 200
Matter ion, the p type impurity ion are one or more of boron ion, indium ion, gallium ion.
It is also formed with high-K gate dielectric layer 210 and function metal layer 201 between the puppet grid 202 and semiconductor substrate 200,
The function metal layer 201 is located on 210 surface of high-K gate dielectric layer.
The puppet grid 202 form groove, form metal gates in a groove as grid, the follow-up pseudo- grid 202 of removal are sacrificed.
Stop-layer when pseudo- as the follow-up removal grid 202 of the function metal layer 201, and as the protective layer of high-K gate dielectric layer 210,
Work function regulating course is can simultaneously serve as, for adjusting the work function for forming NMOS transistor.
The puppet grid 202, function metal layer 201 and high-K gate dielectric layer 210 forming process be：In semiconductor substrate 200
Upper formation high-K gate dielectric material layer；Functional metal materials layer is formed on high-K gate dielectric material layer；In functional metal materials layer
Upper formation polysilicon layer；Patterned hard mask layer is formed on the polysilicon layer；It is with the patterned hard mask layer
Mask is sequentially etched the polysilicon layer, functional metal materials layer and high-K gate dielectric material layer, on semiconductor substrate 200 shape
At high-K gate dielectric layer 210, the function metal layer 201 on high-K gate dielectric layer 210 and on function metal layer 201
Pseudo- grid 202.
The material of the puppet grid 202 can be polysilicon, silicon nitride or amorphous carbon, the material of the function metal layer 201
Material can be TiN, TaN, TiAl, TaC, TaSiN, TiAlN, and the material of the high-K gate dielectric layer 210 can be HfO2、TiO2、
HfZrO、HfSiNO、Ta2O5、ZrO2、ZrSiO2、Al2O3、SrTiO3Or BaSrTiO.
In the present embodiment, the material of the puppet grid 202 is polysilicon, and the material of the function metal layer 201 is TiN, institute
The material for stating high-K gate dielectric layer 210 is HfO2。
Can also form fleet plough groove isolation structure (not shown) in the semiconductor substrate 200, the shallow trench every
The active area adjacent for electric isolation from structure.The material of the fleet plough groove isolation structure is silica.
With reference to figure 5, the first side wall 203 is formed in the sidewall surfaces of the pseudo- grid 202；With 202 and first side of the pseudo- grid
Wall 203 is mask, carries out shallow Doped ions injection, the shape in the semiconductor substrate 200 of 203 both sides of pseudo- grid 202 and the first side wall
At shallow doped region 211.
First side wall 203 forms mask when shallow doped region 211 as ion implanting, and subsequently through removal portion
Divide the first side wall 203 of height so that the opening width that groove can be formed after the pseudo- grid of removal increases.
The material of first side wall 203 is differed with the material for being subsequently formed the second side wall and third side wall, follow-up
When being etched back to the first side wall of removal Partial Height so that the etch rate of the first side wall 203 is much larger than to the second side wall and
The etch rate of third side wall.
In the present embodiment, the material of first side wall 203 is that (relative dielectric constant is less than for the nitride of low-k
3.5), the nitride of low-k is the silicon nitride of carbon dope or the silicon oxide carbide of carbon dope.
The width of first side wall 203 is 50~150 angstroms.
In other embodiments of the invention, the material of first side wall 203 can also be that high-k is (opposite to be situated between
Electric constant is more than nitride 3.5), such as silicon nitride or silicon oxynitride etc..
The shallow doped region 211 is formed by shallow ion injection technology, the foreign ion of shallow doping injection is the impurity of N-type
Ion, the N-type impurity ion are phosphonium ion, arsenic ion, one or more of antimony ion, the shallow Doped ions injection
Dosage is 2E13atom/cm2~2E15atom/cm2, the energy range of injection is 0.5KeV~6KeV.
With reference to figure 6, the second side wall 204 is formed in 203 sidewall surfaces of the first side wall, in 204 side wall of the second side wall
Third side wall 205 is formed on surface.
When second side wall 204 and third side wall 205 are as the second groove of formation of subsequent etching semiconductor substrate 200
Mask can adjust carbon silicon source/drain region and the metal gates of formation by adjusting the second side wall 204 and 205 width of third side wall
Distance.
In the present embodiment, the material of second side wall 204 is silica, and the material of third side wall 205 is that high dielectric is normal
The nitride of number (relative dielectric constant be more than 3.5), the nitride of the high-k be silicon nitride or silicon oxynitride etc..
205 material of third material and 204 material of the second side wall use the material of different dielectric constants, and it is high to remove part in subsequent etching
When the first side wall 203 of degree so that the first side wall 203 relative to the second side wall 204 and third side wall 205 there is high etching to select
Select ratio.
In other embodiments of the invention, the material of the third side wall can be the nitride (phase of low-k
3.5) dielectric constant is less than, for example can be the silicon nitride of carbon dope or the silicon oxide carbide of carbon dope.
In the present embodiment, first side wall 203, the second side wall 204 and third side wall 205 constitute side wall, the second side wall
204 are located at 203 sidewall surfaces of the first side wall, third side wall 205 is located at 204 sidewall surfaces of the second side wall, compared to the side of single layer
Wall, the side wall that the first side wall 203, the second side wall 204 and third side wall 205 are constituted have multiple contact surfaces, have higher machine
Tool stability, and multiple mutual contact surfaces can effectively offset part tensile stress and (be subsequently formed carbon silicon source drain region offside
The tensile stress that wall and dielectric layer generate) influence to side wall, and the of Partial Height can be only removed in the embodiment of the present invention
One side wall can't have an impact the height of the second side wall and third side wall with increasing the width of the opening of the groove of formation,
So that the mechanical stability of side wall and keeping good to the negative function of tensile stress.
First side wall 203, the second side wall 204 and third side wall 205 are by deposition and without mask etching technique
It is formed, thus the width at 205 top of the first side wall 203, the second side wall 204 and third side wall can be less than the width of bottom, it is unfavorable
The side wall of Partial Height is removed in subsequent etching.Therefore in embodiment, after forming pseudo- grid 202, retain the figure on pseudo- grid 202
The hard mask layer of change so that form the hard of first side wall 203, the second side wall 204 and third side wall 205 also cover graphics
The side wall of mask layer, the first side wall 203 of formation, the second side wall 204 and the smaller part of 205 width of third side wall are located at figure
On the side wall of the hard mask layer of change, subsequently when forming dielectric layer, it can be removed by chemical mechanical milling tech patterned
The smaller part of the width of hard mask layer and the first side wall 203, the second side wall 204 and third side wall 205 so that remaining
The width at the top of the first side wall 203, the second side wall 204 and third side wall 205 increases, in favor of removing the first of Partial Height
Side wall 203.
It is mask with the third side wall 205 and pseudo- grid 202 with reference to figure 7, etches the pseudo- grid 202 and third side wall 205
The semiconductor substrate 200 of both sides forms the second groove 212 in semiconductor substrate 200.
Second groove 212 is the groove of sigma shapes, since the second groove 212 has channel region direction outstanding
Protrusion can increase the stretching that carbon silicon source drain region applies to channel region and answer when forming carbon silicon source drain region subsequently in the second groove 212
The size of power, to improve the mobility of carrier.
The forming process of second groove 212 of the sigma shapes is：Using 205 liang of third side wall described in dry etching
The semiconductor substrate 200 of side forms rectangular recess, and the etching gas that dry etching uses is CF4And HBr；Using wet etching institute
The second groove 212 that rectangular recess forms sigma shapes is stated, the etching solution that wet etching uses is TMAH or NH3.H2O。
With reference to figure 8, the carbon silicon source drain region 213 of full second groove 212 (with reference to figure 7) of filling is formed.
213 material of carbon silicon source drain region is silicon carbide, and formation process is selective epitaxial process.Carbon silicon source drain region 213
In doped with N-type foreign ion, can be mixed by situ be entrained in the carbon silicon source drain region 213 to be formed in selective epitaxial
Miscellaneous foreign ion, can also by ion implantation technology in carbon silicon source drain region 213 impurity ion.
Since the lattice constant of silicon carbide is less than the lattice constant of crystalline silicon, carbon silicon source drain region 213 is to transistor
Channel region will produce tensile stress, and in addition the lattice constant of silicon carbide is again smaller than Jie third side wall 205 material and be subsequently formed
The lattice constant of matter layer material, to its close (carbon silicon source drain region 213) surface or with it, (carbon silicon source is leaked in carbon silicon source drain region 213
Area 213) surface contact third side wall 205 and dielectric layer also will produce the effect of tensile stress, formed in the pseudo- grid of follow-up removal
After groove, under the action of tensile stress, side wall and dielectric layer are easy to tilt to the direction of groove so that the opening width of groove
Reduce, influences the formation of metal gates.
With reference to figure 9, dielectric layer 206, the surface of the dielectric layer 206 and pseudo- grid are formed in the semiconductor substrate 200
202 flush.
The material of the dielectric layer 206 is silica or other suitable materials.
The forming process of the dielectric layer 206 is：It is formed using chemical vapor deposition method and covers the semiconductor substrate
200, the layer of dielectric material of pseudo- grid 202 and side wall, the dielectric material layer surface are higher than the surface of pseudo- grid 202；Using chemical machine
Tool grinding technics planarizes the layer of dielectric material, using the top surface of pseudo- grid 202 as stop-layer, forms dielectric layer 206.
Chemical mechanical milling tech planarize the layer of dielectric material when, while remove the patterned hard mask layer,
And part the first side wall 203, the second side wall 204 and third side wall 205 so that remaining first side wall 203, the second side wall
204 and 205 top surface of third side wall and pseudo- grid 202 flush.
With reference to figure 10, the pseudo- grid 202 of removal segment thickness are etched back to, the part surface of side wall side wall is exposed.
The pseudo- grid 202 for being etched back to segment thickness use plasma etching industrial, the etching gas that plasma etching industrial uses
Body is HBr and O2。
In the embodiment of the present invention, the pseudo- grid 202 of segment thickness are etched back to, expose the partial sidewall table of the first side wall 203
Face in order to subsequently can easily remove the first side wall 203 of Partial Height, and can control 203 quilt of the first side wall well
The height of removal protects remaining first side wall 203 not to be etched damage.
The thickness that the puppet grid 202 are removed is the 1/2~1/5 of 202 whole thickness of pseudo- grid.
In other embodiments of the invention, the sidewall surfaces that whole pseudo- grid 202 expose side wall can also be removed.
With reference to figure 11, the side wall (the first side wall 203) of etching removal Partial Height；Remove 202 (reference chart of remaining pseudo- grid
10) groove 207 of " T " font, is formed, the groove 207 of " T " font exposes the work(on the surface of semiconductor substrate 200
It can metal layer 201.
By removing the first side wall 203 of Partial Height, after removing remaining pseudo- grid, it is in " T " to make the groove to be formed 207
Font, so that the width of the opening of the groove 207 formed broadens, even if side wall and dielectric layer 206 are in carbon silicon source drain region 213
It can be tilted to the direction of groove 207 under the action of the tensile stress of generation so that the opening width of groove 207 can reduce, still,
Under the action of same tensile stress, the opening width for the groove 207 that the embodiment of the present invention is formed is greater than the prior art and exists
The width of the opening of the groove formed after the pseudo- grid of removal, to reduce the generation of defect when forming gate structure.
The height that first side wall 203 is removed is the 1/2~1/5 of 203 total height of the first side wall.
The first side wall 203 that Partial Height is removed using plasma etching industrial, in order to when etching the first side wall 203,
The damage or loss of second side wall 204 and third side wall 205 and dielectric layer 206 are smaller, can pass through several implementations below
Example performs etching the first side wall 203.
In one embodiment, the plasma etching uses etching gas for N2, N2Flow be 50sccm-1000sccm,
Chamber temp is 0-100 DEG C, source power 100W-1000W, bias power 0-300W.
In another embodiment, the etching gas that the plasma etching uses is CH2F2、CHF3、H2、N2, CH2F2Stream
Amount is 5-100sccm, CHF3Flow be 5-100sccm, H2Flow be 10-500sccm, N2Flow be 50-
1000sccm, chamber temp are 0-100 DEG C, source power 100w-1000W, bias power 0-300W.
In another embodiment, the etching gas that the plasma etching uses is C4F8、C4F6、Ar、O2, C4F8Flow
For 5-100sccm, C4F6Flow be 5-100sccm, the flow of Ar is 50-500sccm, O2Flow be 5-100scc, chamber
Temperature is 0-100 DEG C, source power 100w-1000W, bias power 0-300W.
In another embodiment, the plasma etching is cycle plasma etching, including deposition step alternately
And etch step, the gas of the deposition step material is C4F8, the gas that etch step uses is Ar, C4F8Flow be 5-
The flow of 100sccm, Ar are 50-500sccm, source power 100w-1000W, bias power 0-300W, logical when deposition step
Enter C4F8It is used to form the polymer of protection, when etch step is passed through for being performed etching to the first side wall 203, using cycle etc.
Ion etch process can control the height that the first side wall 203 is removed well, and deposition step forms polymer energy very well
The second side wall of protection 204 and third side wall 205 will not be etched.
It removes remaining pseudo- grid 202 and uses plasma etching industrial, the etching gas that plasma etching industrial uses is HBr
And O2。
In other embodiments of the invention, the material of first side wall is the nitride of high-k, described the
When three spacer materials are the nitride of low dielectric constant, the first side wall of etching removal Partial Height uses wet etching, wet method
The etching solution used is etched as concentrated phosphoric acid.
With reference to figure 12, plasma cleaning 21 is carried out to the function metal layer 201 of 207 bottom of groove.
After the pseudo- grid of removal, the oxygen in air can generate oxidation to the function metal layer 201 of 207 bottom of groove,
Metal oxide is will produce on the surface of function metal layer 201, especially in the pseudo- grid of removal, there are oxygen, at high temperature, work(
201 surface of energy metal layer is more prone to metal oxide, and the presence of metal oxide can influence the metal gates being subsequently formed
Electrical performance, and the adjustment effect of the work function of function metal layer 201 is had an impact.In this implementation, groove 207 is being formed
Afterwards, the gold that plasma cleaning 21 is formed with 201 surface of remove function metal layer is carried out to 207 bottom function metal layer 201 of groove
Belong to oxide.
In one embodiment, the gas that the plasma cleaning uses is N2, N2Flow be 50-1000sccm, chamber temperature
Degree is 0-100 DEG C, source power 100-1000W, bias power 0-300W.
In another embodiment, the plasma cleaning includes deposition step alternately and etch step, described heavy
The gas of product step material is C4F8, the gas that etch step uses is Ar, C4F8Flow be 5-200sccm, the flow of Ar is
50-1000sccm, source power 100-1000W, bias power 0-300W.
With reference to figure 13, the metal gates 209 of the groove 207 (with reference to figure 12) of full " T " font of filling are formed.
The material of the metal gates 209 is tungsten, aluminium, copper or other suitable metal materials, the formation of metal gates 209
Technique is sputtering.
The embodiment of the present invention additionally provides a kind of NMOS transistor, please refers to Fig.1 3, including：
Semiconductor substrate 200 is formed with carbon silicon source/drain region 213 in the semiconductor substrate 200；
The dielectric layer 206 of the semiconductor substrate 200 is covered, has in the dielectric layer 206 and exposes carbon silicon source/drain region
The groove of semiconductor substrate 200 between 213；
Positioned at the side wall of groove both sides sidewall surfaces, the top surface of the side wall is less than the surface of dielectric layer 206；
" T " the font metal gates 209 of the full groove of filling, the metal gates 209 cover the side coping and side
Wall surface, and the top surface of metal gates 209 is flushed with the surface of dielectric layer 206.
Specifically, the side wall includes：Positioned at the third side wall 205 on recess sidewall surface, positioned at 205 side wall of third side wall
Second side wall 204 on surface, the first side wall 203 positioned at 204 sidewall surfaces of the second side wall, first side wall 203 and second
The material of side wall 204 and third side wall 205 differs, and the top surface of the first side wall 203 is less than the surface of dielectric layer 206,
The top surface of second side wall 204 and third side wall 205 is flushed with dielectric layer surface, and " T " font metal gates 209 cover described
The side wall and top surface of first side wall 203.
In one embodiment, the material of first side wall 203 be low-k nitride (relative dielectric constant is small
In 3.5), the nitride of low-k is the silicon nitride of carbon dope or the silicon oxide carbide of carbon dope, the material of second side wall 204
Material is silica, and the material of third side wall 205 is the nitride of high-k (relative dielectric constant is more than 3.5), the height
The nitride of dielectric constant be silicon nitride or silicon oxynitride etc..
In another embodiment, the material 203 of first side wall can also be high-k (relative dielectric constant
More than nitride 3.5), such as silicon nitride or silicon oxynitride etc., the material of second side wall 204 is silica, described the
The material of three side walls 5 can be the nitride (relative dielectric constant is less than 3) of low-k, for example can be the nitridation of carbon dope
The silicon oxide carbide of silicon or carbon dope.
It is also formed with high-K gate dielectric layer 210 and function metal layer 201 between the puppet grid 202 and semiconductor substrate 200,
The function metal layer 201 is located on 210 surface of high-K gate dielectric layer.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (18)
1. a kind of forming method of NMOS transistor, which is characterized in that including：
Semiconductor substrate is provided, pseudo- grid are formed in the semiconductor substrate, side wall is formed on the side wall of the puppet grid, it is described
Carbon silicon source drain region is formed in the semiconductor substrate of pseudo- grid and side wall both sides；
Dielectric layer, the flush on the surface of the dielectric layer and pseudo- grid, carbon silicon source drain region are formed on the semiconductor substrate
To will produce the effect of tensile stress close to its surface or the side wall and dielectric layer that are contacted with its surface, in the pseudo- grid of follow-up removal
After forming groove, under the action of tensile stress, side wall and dielectric layer can be tilted to the direction of groove so that the opening of groove is wide
Degree reduces；
The pseudo- grid of removal segment thickness are etched back to, the part surface of side wall side wall is exposed；
The side wall of etching removal Partial Height；
Remaining pseudo- grid are removed, the groove of " T " font is formed, the groove of " T " font is located at the inclined side wall in direction to groove
Between dielectric layer；
Form the metal gates of the groove of full " T " font of filling.
2. the forming method of NMOS transistor as described in claim 1, which is characterized in that the side wall includes：Positioned at pseudo- grid
First side wall of side wall, positioned at the second side wall of the first side wall sidewall surfaces, positioned at the third side wall of the second side wall sidewall surfaces,
The material of first side wall and the second side wall and third side wall differs；The pseudo- grid of part are etched back to, the first side is exposed
The partial sidewall of wall；First side wall of etching removal Partial Height.
3. the forming method of NMOS transistor as claimed in claim 2, which is characterized in that before forming pseudo- grid, described
High-K gate dielectric layer is formed in semiconductor substrate, and function metal layer is formed on the high-K gate dielectric layer.
4. the forming method of NMOS transistor as claimed in claim 3, which is characterized in that the puppet grid and carbon silicon source drain region
Forming process is：High-K gate dielectric material layer is formed on a semiconductor substrate；Function metal is formed on high-K gate dielectric material layer
Material layer；Polysilicon layer is formed on functional metal materials layer；Patterned hard mask layer is formed on the polysilicon layer；With
The patterned hard mask layer is mask, is sequentially etched the polysilicon layer, functional metal materials layer and high-K gate dielectric material
Layer forms high-K gate dielectric layer, the function metal layer on high-K gate dielectric layer and is located at function metal on a semiconductor substrate
Pseudo- grid on layer；The first side wall is formed in the sidewall surfaces of the pseudo- grid；Using the pseudo- grid and the first side wall as mask, carry out
Shallow Doped ions injection, shallow doped region is formed in the semiconductor substrate of pseudo- grid and the first side wall both sides；In first side wall
The second side wall is formed in sidewall surfaces, and third side wall is formed in the second side wall sidewall surfaces；With the third side wall and pseudo- grid
For mask, the semiconductor substrate of the pseudo- grid and third side wall both sides is etched, forms the second groove in semiconductor substrate；It is formed
The carbon silicon source drain region of full second groove of filling.
5. the forming method of NMOS transistor as claimed in claim 4, which is characterized in that the forming process of dielectric layer is：Shape
At cover the pseudo- grid, the first side wall, the second side wall, third side wall, carbon silicon source drain region and semiconductor substrate surface medium material
The bed of material；Certain media material layer and patterned hard mask layer are removed using chemical mechanical milling tech, expose the top of pseudo- grid
Portion surface forms dielectric layer.
6. the forming method of NMOS transistor as claimed in claim 2, which is characterized in that the material of first side wall is low
The nitride of dielectric constant, the third spacer material are the nitride of high-k.
7. the forming method of NMOS transistor as claimed in claim 6, which is characterized in that the material of the nitride of low-k
Material is the silicon nitride of carbon dope, and the nitride of the high-k is silicon nitride, and the material of second side wall is silica.
8. the forming method of NMOS transistor as claimed in claim 7, which is characterized in that removed using plasma etching industrial
First side wall of Partial Height.
9. the forming method of NMOS transistor as claimed in claim 8, which is characterized in that the plasma etching is using etching
Gas is N2, N2Flow be 50sccm-1000sccm, chamber temp be 0-100 DEG C, source power 100W-1000W, bias work(
Rate is 0-300W.
10. the forming method of NMOS transistor as claimed in claim 8, which is characterized in that the plasma etching used
Etching gas is CH2F2、CHF3、H2And N2, CH2F2Flow be 5-100sccm, CHF3Flow be 5-100sccm, H2Stream
Amount is 10-500sccm, N2Flow be 50-1000sccm, chamber temp be 0-100 DEG C, source power 100w-1000W, partially
It is 0-300W to set power.
11. the forming method of NMOS transistor as claimed in claim 8, which is characterized in that the plasma etching used
Etching gas is C4F8、C4F6, Ar and O2, C4F8Flow be 5-100sccm, C4F6Flow be 5-100sccm, the flow of Ar
For 50-500sccm, O2Flow be 5-100scc, chamber temp be 0-100 DEG C, source power 100w-1000W, bias power
For 0-300W.
12. the forming method of NMOS transistor as claimed in claim 8, which is characterized in that the plasma etching is cycle
Plasma etching, including deposition step alternately and etch step, the gas that the deposition step uses is C4F8, etching
The gas that step uses is Ar, C4F8Flow be 5-100sccm, the flow of Ar is 50-500sccm, source power 100w-
1000W, bias power 0-300W.
13. the forming method of NMOS transistor as claimed in claim 3, which is characterized in that the material of the function metal layer
For TiN, TaN, TiAl, TaC, TaSiN, TiAlN.
14. the forming method of NMOS transistor as claimed in claim 13, which is characterized in that the remaining pseudo- grid of removal are formed
The groove of " T " font, the groove of " T " font expose the surface of function metal layer, remove remaining pseudo- grid using etc. from
Sub- etching technics, the etching gas that the plasma etching industrial uses is HBr and O2。
15. the forming method of NMOS transistor as claimed in claim 14, which is characterized in that the function metal of bottom portion of groove
Layer carries out plasma cleaning.
16. the forming method of NMOS transistor as claimed in claim 15, which is characterized in that the plasma cleaning used
Gas is N2, N2Flow be 50-1000sccm, chamber temp is 0-100 DEG C, source power 100-1000W, and bias power is
0-300W。
17. the forming method of NMOS transistor as claimed in claim 15, which is characterized in that the plasma cleaning includes handing over
For the deposition step and etch step of progress, the gas that the deposition step uses is C4F8, gas that etch step uses for
Ar, C4F8Flow be 5-200sccm, the flow of Ar is 50-1000sccm, source power 100-1000W, bias power 0-
300W。
18. the forming method of NMOS transistor as claimed in claim 2, which is characterized in that the material of first side wall is
The nitride of high-k, the third spacer material are the nitride of low-k, the of etching removal Partial Height
One side wall uses wet etching, and the etching solution that wet etching uses is concentrated phosphoric acid.
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| CN108573862B (en) * | 2017-03-07 | 2020-09-08 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109728088A (en) * | 2017-10-30 | 2019-05-07 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN110021560A (en) * | 2018-01-10 | 2019-07-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN110571259B (en) * | 2018-06-05 | 2023-04-07 | 中芯国际集成电路制造(上海)有限公司 | FINFET device and preparation method thereof |
| CN110571141B (en) * | 2018-06-05 | 2022-01-28 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing metal gate and method for manufacturing semiconductor device |
| CN110797261B (en) * | 2018-08-01 | 2023-04-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN112086349A (en) * | 2019-06-14 | 2020-12-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN112151375A (en) * | 2019-06-28 | 2020-12-29 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN112309861B (en) * | 2019-07-30 | 2023-10-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure, forming method thereof and transistor |
| CN114566432A (en) * | 2022-04-29 | 2022-05-31 | 合肥新晶集成电路有限公司 | Method for manufacturing semiconductor device and semiconductor device |
| CN116344623B (en) * | 2023-05-30 | 2023-08-22 | 粤芯半导体技术股份有限公司 | High-voltage MOS device and preparation method thereof |
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