CN106960791B - Transistor and forming method thereof - Google Patents
Transistor and forming method thereof Download PDFInfo
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- CN106960791B CN106960791B CN201610015637.7A CN201610015637A CN106960791B CN 106960791 B CN106960791 B CN 106960791B CN 201610015637 A CN201610015637 A CN 201610015637A CN 106960791 B CN106960791 B CN 106960791B
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- 239000004065 semiconductor Substances 0.000 claims abstract description 178
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- 150000002500 ions Chemical class 0.000 claims description 78
- 239000000463 material Substances 0.000 claims description 71
- 238000002347 injection Methods 0.000 claims description 43
- 239000007924 injection Substances 0.000 claims description 43
- 230000008569 process Effects 0.000 claims description 36
- 239000012535 impurity Substances 0.000 claims description 29
- -1 Nitrogen ion Chemical class 0.000 claims description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 13
- 230000015572 biosynthetic process Effects 0.000 claims description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 13
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 11
- 229910052757 nitrogen Inorganic materials 0.000 claims description 9
- 238000000137 annealing Methods 0.000 claims description 8
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 5
- 229910001449 indium ion Inorganic materials 0.000 claims description 4
- 238000002513 implantation Methods 0.000 claims description 3
- 239000011261 inert gas Substances 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 85
- 238000002955 isolation Methods 0.000 description 14
- 238000005530 etching Methods 0.000 description 13
- 239000007789 gas Substances 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
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- 238000005229 chemical vapour deposition Methods 0.000 description 5
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- 125000006850 spacer group Chemical group 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
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- 238000007254 oxidation reaction Methods 0.000 description 3
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- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 229910001439 antimony ion Inorganic materials 0.000 description 2
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- 238000006243 chemical reaction Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- CKHJYUSOUQDYEN-UHFFFAOYSA-N gallium(3+) Chemical compound [Ga+3] CKHJYUSOUQDYEN-UHFFFAOYSA-N 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 241000828883 Alope Species 0.000 description 1
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- VLQGDKKHHCKIOJ-UHFFFAOYSA-N NNOS Chemical compound NNOS VLQGDKKHHCKIOJ-UHFFFAOYSA-N 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
A kind of transistor and forming method thereof, the wherein forming method of transistor, comprising: semiconductor substrate is provided, is formed with well region in the semiconductor substrate, doped with the foreign ion of the first kind in the well region；Form drain region on the semiconductor substrate surface, doped with the foreign ion of Second Type, the first kind is opposite with Second Type in the drain region；Sidewall surfaces in drain region form side wall；Groove is formed in the semiconductor substrate of drain region and side wall two sides；Source region, foreign ion of the source region doped with Second Type are formed in the semiconductor substrate of bottom portion of groove；Separation layer is formed in area surface；Gate dielectric layer is formed in the sidewall surfaces of groove；After forming gate dielectric layer, the gate electrode of filling groove is formed.The current driving ability for the transistor that the method for the present invention is formed is promoted, and reduces the generation of leakage current.
Description
Technical field
The present invention relates to field of semiconductor fabrication, in particular to a kind of transistor and forming method thereof.
Background technique
Metal-oxide-semicondutor (MOS) transistor is the most basic device in semiconductors manufacture, is widely used in
In various integrated circuits, doping type when according to principal carrier and manufacture is different, is divided into NMOS and PMOS transistor.
The prior art provides a kind of production method of MOS transistor, comprising: provides semiconductor base, partly leads described
Body substrate forms isolation structure, and the semiconductor base between the isolation structure is active area, forms trap in the active area
Area's (not shown)；By the first ion implanting in well region surface doping foreign ion, to adjust the threshold for the transistor being subsequently formed
Threshold voltage；Gate dielectric layer and gate electrode, the gate dielectric layer are sequentially formed on semiconductor base between the isolation structure
Gate structure is constituted with gate electrode；Oxidation technology is carried out, the oxide layer for covering the gate structure is formed；Carry out shallow Doped ions
Injection forms source drain extension area in the semiconductor base of gate structure two sides；Using the gate structure as exposure mask, to grid
The well region of structure two sides carries out deep Doped ions injection, and the energy and dosage of deep Doped ions injection are injected greater than shallow Doped ions
Energy and dosage, form source region and drain region in the well region of gate structure two sides, the depth in the source region and drain region be greater than source/
The depth of drain extension region.
The performance for the transistor that the prior art is formed still has to be hoisted.
Summary of the invention
Problems solved by the invention is how to improve the current driving ability of transistor.
To solve the above problems, the present invention provides a kind of forming method of transistor, comprising:
Semiconductor substrate is provided, is formed with well region in the semiconductor substrate, doped with the first kind in the well region
Foreign ion；Form drain region on the semiconductor substrate surface, the drain region doped with Second Type foreign ion, first
Type is opposite with Second Type；Sidewall surfaces in drain region form side wall；The shape in the semiconductor substrate of drain region and side wall two sides
At groove；Source region, foreign ion of the source region doped with Second Type are formed in the semiconductor substrate of bottom portion of groove；In source
Area surface forms separation layer；Gate dielectric layer is formed in the sidewall surfaces of groove；After forming gate dielectric layer, the grid of filling groove are formed
Electrode.
Optionally, the forming process of the groove are as follows: using the drain region and side wall as exposure mask, etch the drain region and side wall
Semiconductor substrates on two sides forms the groove of sigma shape；Continue to etch the side wall of the groove of the sigma shape, formation has
The groove of arcuation side wall.
Optionally, the forming process of the groove are as follows: using the drain region and side wall as exposure mask, etch the semiconductor material
The semiconductor substrate of layer and side wall forms rectangular recess；Continue to etch the rectangular recess, so that the side wall of rectangular recess is to side
The semiconductor substrate of wall bottom extends.
Optionally, the material of the separation layer is silicon nitride.
Optionally, the forming process of the separation layer are as follows: inject Nitrogen ion on the surface of source region；Annealing process is carried out in source
The surface in area forms the separation layer of silicon nitride material.
Optionally, energy when stating N~+ implantation is 2KeV~10KeV, and dosage is 5e15~5e16/cm2。
Optionally, 600~1000 DEG C of the temperature of the annealing process, time 1min~30min, atmosphere is inert gas.
Optionally, the formation process of the source region is heavy doping ion injection.
Optionally, when arsenic ion or phosphonium ion are injected in heavy doping ion injection, the dosage of injection is 1E15~1E25atom/
cm2, the energy of injection is 10~30Kev, and the angle of injection is 0~5 degree.
Optionally, when boron ion or indium ion are injected in heavy doping ion injection, the dosage of injection is 2KeV~10KeV, note
The energy entered is 3e14~3e15/cm2, the angle of injection is 0~5 degree.
Optionally, further includes: carry out shallow Doped ions injection, formed and be lightly doped in the semiconductor substrate of bottom portion of groove
Area, the doping type of the lightly doped district and the doping type of source region are identical, and the depth of lightly doped district is less than the depth of source region,
The concentration impurity ion of lightly doped district is less than the concentration impurity ion of source region.
Optionally, further includes: carry out bag-shaped ion implanting, form bag-shaped injection in the semiconductor substrate of bottom portion of groove
The doping type in area, the bag-shaped injection region is opposite with the doping type of source region.
Optionally, the forming process in the drain region: forming semiconductor material layer on the semiconductor substrate, described partly to lead
Body material layer includes first part and the second part in first part, doped with the second class in the semiconductor material layer
The foreign ion of type, and the concentration impurity ion in first part is less than the concentration impurity ion of second part；Etch described half
Conductor material layer, forms drain region on the semiconductor substrate, and the drain region includes that the semiconductor material layer of first part is carved
The semiconductor material layer for losing the shallow doped region and second part that are formed etches the heavily doped region to be formed.
Optionally, the groove is at least two discrete grooves, is located in semiconductor material layer and side wall two sides
Semiconductor substrate in.
Optionally, the groove is an annular groove, and the annular groove is located at partly leading in drain region and side wall two sides
In body substrate, and the semiconductor substrate around drain region and side wall bottom.
The present invention also provides a kind of transistors, comprising:
Semiconductor substrate, is formed with well region in the semiconductor substrate, doped with the impurity of the first kind in the well region
Ion；Drain region on semiconductor substrate surface, foreign ion of the drain region doped with Second Type, the first kind and the
Two types are opposite；Side wall in the sidewall surfaces in drain region；Groove in the semiconductor substrate of drain region and side wall two sides；
Source region in the semiconductor substrate of bottom portion of groove, foreign ion of the source region doped with Second Type；Positioned at source region table
The separation layer in face；Positioned at the gate dielectric layer of the sidewall surfaces of groove；Positioned at gate dielectric layer and insulation surface and fill groove
Gate electrode.
Optionally, also there is shallow doped region, the doping class of the lightly doped district in the semiconductor substrate of the bottom portion of groove
Type is identical as the doping type of source region, and the depth of lightly doped district is less than the depth of source region, the concentration impurity ion of lightly doped district
Less than the concentration impurity ion of source region.
Optionally, the drain region includes the shallow doped region in semiconductor substrate and the heavy doping on shallow doped region
Area.
Optionally, the groove is at least two discrete grooves, is located in semiconductor material layer and side wall two sides
Semiconductor substrate in.
Optionally, the groove is an annular groove, and the annular groove is located at partly leading in drain region and side wall two sides
In body substrate, and the semiconductor substrate around drain region and side wall bottom.
Compared with prior art, technical solution of the present invention has the advantage that
The forming method of transistor of the invention forms drain region on the semiconductor substrate surface, the side wall in drain region
After surface forms side wall；Groove is formed in the semiconductor substrate of drain region and side wall two sides；In the semiconductor substrate of bottom portion of groove
Interior formation source region, foreign ion of the source region doped with Second Type；Separation layer is formed in area surface；In the side wall of groove
Surface forms gate dielectric layer；After forming gate dielectric layer, the gate electrode of filling groove is formed.It can in the semiconductor substrate of recess sidewall
To form the three-dimensional channel region of multidimensional, while guaranteeing that the transistor formed occupies lesser lateral dimension, so that channel region
Area increase, allow channel region by bigger driving current, improve the current driving ability to form transistor.Separately
Outside, gate structure, three-dimensional channel of the gate structure to the multidimensional formed in the semiconductor substrate of recess sidewall are formed in groove
Area is controlled, and is improved gate structure to channel region control ability, is prevented the generation of leakage current.
Further, the semiconductor material layer includes first part and the second part in first part, and described half
Concentration impurity ion doped with the foreign ion of Second Type in conductor material layer, and in first part is less than second part
Concentration impurity ion, the first part of etching semiconductor material layer are subsequently formed lightly doped district, and the of etching semiconductor material layer
Two parts form heavily doped region, and lightly doped district and heavily doped region constitute drain region, and the purpose for forming lightly doped district is in order to effectively anti-
Only hot carrier injection effect.
Further, the side wall of the groove is arcuation side wall, the semiconductor substrate of the arcuation side wall to drain region bottom
Direction protrusion, the side wall of groove are in the purpose of arcuation: on the one hand, (including being located at groove when forming gate structure in a groove
The gate dielectric layer of side wall and the gate electrode of filling groove), when applying operating voltage on gate structure, prevent point discharge；Separately
On the one hand, forming channel region since side wall is arc, in the semiconductor substrate of corresponding recess sidewall is also arc, thus
Transistor of the invention may be implemented with existing transistor have equal length channel region length while, reduce drain region and
The distance of the source region formed in the semiconductor substrate of bottom portion of groove.
Further, the groove is at least two discrete grooves, corresponding in the semiconductor substrate of multiple bottom portion of groove
Multiple source regions are formed, form multiple gate structures accordingly in multiple grooves, in the semiconductor substrate of the side wall of multiple grooves
In form multiple channel regions accordingly, to increase the area of channel region.
Further, the groove is an annular groove, and the annular groove is located at half in drain region and side wall two sides
In conductor substrate, and the semiconductor substrate around drain region and side wall bottom further increases channel region when groove is annular
Area improves the current driving ability for the transistor to be formed.
Transistor of the invention can form the three-dimensional channel region of multidimensional in the semiconductor substrate of recess sidewall, guarantee
While the transistor of formation occupies lesser lateral dimension, so that the area of channel region increases, channel region is passed through
Bigger driving current improves the current driving ability to form transistor.In addition, gate structure is formed in groove, grid
Structure controls the three-dimensional channel region of the multidimensional formed in the semiconductor substrate of recess sidewall, improves gate structure to ditch
Road area control ability, prevents the generation of leakage current.
Detailed description of the invention
Fig. 1~Figure 11 is the structural schematic diagram of transistor of embodiment of the present invention forming process.
Specific embodiment
As described in the background art, the performance of the transistor of prior art formation still has to be hoisted, for example the prior art is formed
Transistor current driving ability still have it is to be hoisted.
The study found that the transistor of the prior art is at work, ditch is formed in the semiconductor substrate of gate structure bottom
Road area, which is planar channeling, with the continuous reduction of characteristic size, the size (such as width and length) of channel region by
To the limitation of the structure of the transistor of existing formation, thus the size of current that channel region passes through is conditional, so that electric current
Driving capability is still limited.
The present invention provides a kind of transistors and forming method thereof thus, and leakage is formed on the semiconductor substrate surface
Area, after the sidewall surfaces in drain region form side wall；Groove is formed in the semiconductor substrate of drain region and side wall two sides；In groove-bottom
Source region, foreign ion of the source region doped with Second Type are formed in the semiconductor substrate in portion；It is formed and is isolated in area surface
Layer；Gate dielectric layer is formed in the sidewall surfaces of groove；After forming gate dielectric layer, the gate electrode of filling groove is formed.Recess sidewall
Semiconductor substrate in can form the three-dimensional channel region of multidimensional, guaranteeing that the transistor formed occupies lesser lateral dimension
Meanwhile so that the area of channel region increases, allows channel region by bigger driving current, improve to form transistor
Current driving ability.In addition, form gate structure in groove, gate structure in the semiconductor substrate of recess sidewall to forming
The three-dimensional channel region of multidimensional is controlled, and is improved gate structure to channel region control ability, is prevented the generation of leakage current.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.When describing the embodiments of the present invention, for purposes of illustration only, schematic diagram can disobey general proportion
Make partial enlargement, and the schematic diagram is example, should not limit the scope of the invention herein.In addition, in reality
It should include the three-dimensional space of length, width and depth in production.
Fig. 1~Figure 11 is the structural schematic diagram of transistor of embodiment of the present invention forming process.
With reference to Fig. 1 and Fig. 2, semiconductor substrate 200 is provided, well region is formed in the semiconductor substrate 200 and (does not show in figure
Out), doped with the foreign ion of the first kind in the well region；Drain region 203 is formed on 200 surface of semiconductor substrate,
Doped with the foreign ion of Second Type, the first kind is opposite with Second Type in the drain region 203.
The material of the semiconductor substrate 200 can be silicon (Si), germanium (Ge) or SiGe (GeSi), silicon carbide (SiC)；
It is also possible to silicon-on-insulator (SOI), germanium on insulator (GOI)；Or can also be for other materials, such as GaAs etc.
III-V compounds of group.In the present embodiment, the material of the semiconductor substrate 200 is silicon.In the present embodiment, the semiconductor lining
The material at bottom 200 is silicon.
Fleet plough groove isolation structure 205 is also formed in the semiconductor substrate 200, the fleet plough groove isolation structure 205 is used
In the adjacent active area of isolation.In one embodiment, 205 forming process of fleet plough groove isolation structure are as follows: etching is described partly to be led
Body substrate forms groove；The spacer material layer for covering the semiconductor substrate and filling full groove is formed using depositing operation；It is flat
Smoothization removes the spacer material layer on semiconductor substrate surface, forms fleet plough groove isolation structure in the trench.
Well region is formed in semiconductor substrate 200 between the fleet plough groove isolation structure 205, the well region is doped with
The foreign ion of one type can form the well region by ion implantation technology.
In one embodiment, the forming process in the drain region 203 are as follows: form semiconductor in the semiconductor substrate 200
Material layer 201, doped with the foreign ion of Second Type, Second Type and first kind phase in the semiconductor material layer 201
Instead；Patterned hard mask layer 202 is formed on 201 surface of semiconductor material layer；With the patterned hard mask layer
202 be exposure mask, etches the semiconductor material layer 201, and drain region 203 is formed in the semiconductor substrate 200.
The drain region 203 is located above active area (or well region), or between adjacent shallow trench isolation structure 205
In semiconductor substrate, the patterned hard mask layer 202 can be silica, silicon nitride or other suitable mask materials.
The material of the semiconductor material layer 201 is silicon, SiGe or silicon carbide.The formation of the semiconductor material layer 201
Technique is chemical vapor deposition.In the present embodiment, the material of the semiconductor material layer 201 is silicon, semiconductor material layer 201
With a thickness of 500~2000 angstroms.
When chemical vapor deposition process forms semiconductor material layer 201 the semiconductor material can be entrained in by situ
The foreign ion of the Second Type adulterated in the bed of material 201.It in other embodiments, can be by ion implantation technology in semiconductor
The foreign ion of Second Type is adulterated in material layer.
In one embodiment, the semiconductor material layer 201 includes first part and second in first part
Point, the concentration impurity ion doped with the foreign ion of Second Type in the semiconductor material layer, and in first part is less than
The concentration impurity ion of second part, the first part of etching semiconductor material layer are subsequently formed lightly doped district, etching semiconductor
The second part of material layer forms heavily doped region, and lightly doped district and heavily doped region constitute drain region, and the purpose for forming lightly doped district is
In order to effectively prevent hot carrier injection effect.
In one embodiment, when the material of semiconductor material layer 201 is silicon, chemical vapor deposition process, which is formed, described partly to be led
When body material layer: chamber temp is 650-800 degrees Celsius, and chamber pressure is 5-20torr, silicon source gas SiH4Or
SiCl2H4, the flow of silicon source gas is 30-200sccm, and chemical vapor deposition process further includes being passed through impurity source gas, is deposited
Journey includes first stage and second stage, in the first stage (to first time point since deposition), forms semiconductor material layer
201 first part, the flow of the impurity source gas are first flow；In second stage (when from first time point to second
Between point), form the second part of semiconductor material layer, the thickness of second part is greater than the thickness of first part, the impurity source
Gas is second flow, and second flow is greater than first flow, and the duration of second stage be greater than the first stage it is lasting when
Between, in one embodiment, the first flow is 5~200sccm, and the second flow is 40~800sccm.So that being formed
Semiconductor material layer 201 in first part and second part it is subsequent uniformly, and it is miscellaneous in first part and second part
Matter ion concentration is more accurate, and the distribution of foreign ion is more uniform.
It is different when the type of the foreign ion adulterated according to the difference for forming transistor, in well region and drain region 203, work as shape
When at NNOS transistor, the foreign ion for the first kind adulterated in the well region is in boron ion, gallium ion or indium ion
One or more, the foreign ion for the Second Type that the drain region 203 is adulterated are one of phosphonium ion, arsenic ion or antimony ion
Or it is several；When forming PMOS transistor, the foreign ion of the first kind adulterated in the well region be phosphonium ion, arsenic ion or
One or more of antimony ion, the foreign ion for the Second Type that the drain region 203 is adulterated be boron ion, gallium ion or indium from
One or more of son.
In the present embodiment, to form NMOS transistor as an example, forming the impurity source of semiconductor material layer 201 accordingly
Gas is PH3Or AsH3.In other embodiments, when forming PMOS transistor, the impurity source gas can be BF3。
With reference to Fig. 3, the sidewall surfaces in drain region 203 form side wall 204.
The side wall 204 subsequent etching semiconductor substrate formed groove when for controlling the position for forming groove, and
For protecting the side wall in drain region 204.
The material of the side wall 204 can be one or more of silicon nitride, silica, silicon oxynitride.
The side wall 204 can be single-layer or multi-layer (>=2 layers) stacked structure.
In the present embodiment, the side wall 204 also covers the sidewall surfaces of the patterned hard mask layer 202.
In one embodiment, the forming process of the side wall 204 are as follows: formed and cover the semiconductor substrate 200, drain region
203 and image conversion 202 surface of hard mask layer spacer material layer；The spacer material is etched using no mask etching technique
Layer；Side wall 204 is formed in the sidewall surfaces of the drain region 203 (and hard mask layer 202 of image conversion).
In conjunction with doping Fig. 4 and Fig. 5, groove 206 is formed in the semiconductor substrate 200 of 204 two sides of drain region 203 and side wall.
In the present embodiment, formed groove 206 purpose: on the one hand, after forming groove 206, it is subsequent can be in groove 206
Source region is formed in the semiconductor substrate of bottom；On the other hand, subsequent in the semiconductor substrate (203 bottom of drain region) of recess sidewall can
To form the three-dimensional channel region of multidimensional, while guaranteeing that the transistor formed occupies lesser lateral dimension, so that channel region
Area increase, allow channel region by bigger driving current, improve the current driving ability to form transistor；Again
On the one hand, subsequent that gate structure is formed in groove, gate structure is to the multidimensional formed in the semiconductor substrate of recess sidewall
Three-dimensional channel region is controlled, and is improved gate structure to channel region control ability, is prevented the generation of leakage current.
The depth of the groove 206 is less than the depth of fleet plough groove isolation structure 205.
In one embodiment, the side wall of the groove 206 is arcuation side wall, and the arcuation side wall is to 203 bottom of drain region
The direction protrusion of semiconductor substrate, the side wall of groove 206 is in the purpose of arcuation: on the one hand, subsequent to form grid in a groove
Structure (including being located at the gate dielectric layer of recess sidewall and the gate electrode of filling groove), applies operating voltage on gate structure
When, prevent point discharge；On the other hand, since side wall is arc, ditch is formed in the semiconductor substrate of corresponding recess sidewall
Road area is also arc, thus the channel region length for having equal length with existing transistor may be implemented in transistor of the invention
While, reduce the distance of the source region formed in the semiconductor substrate of 206 bottom of drain region 203 and groove.
In one embodiment, the forming process of the groove 206 with arcuation side wall are as follows: with the drain region 203 and side wall 204
For exposure mask, the semiconductor substrate 200 of 204 two sides of the drain region 203 and side wall is etched, forms the groove 216 of sigma shape；After
The side wall of the groove 216 of the continuous etching sigma shape, forms the groove 206 with arcuation side wall.
The forming process of the groove 216 of sigma shape are as follows: with the drain region 203 and side wall 204 be exposure mask, using it is each to
The semiconductor substrate 200 in dry etch process the etching drain region 203 and 204 two sides of side wall of the same sex, forms in the semiconductor substrate
Rectangular recess, the gas that the dry etch process uses in one embodiment includes: CF4, HBr, He and O2, CF4Gas stream
Amount is 20-200sccm, and the gas flow of HBr is 50-1000sccm, and the gas flow of He is 200-1000sccm, O2Gas
Flow is 5-20sccm, and chamber temp is 40-80 DEG C, chamber pressure 5-50mTorr, radio-frequency power 400-750W, biasing
Power is 0-100W, etch period 20-80S；Then the rectangular recess is etched using wet-etching technology, forms sigma
The groove 216 of shape, in one embodiment, the wet-etching technology use the quarter for having different etching rate to different crystal orientations
Lose solution TMAH solution or NH3.H2O solution, TMAH solution or NH3.H2The mass percent of O solution is 1%-5%, when etching
Between be 20-80S.
Continue to etch the side wall of the groove 216 of the sigma shape, being formed has the groove 206 of arcuation side wall using wet
Method etching technics, in one embodiment, the etching solution that the wet-etching technology uses is nitric acid or nitric acid and hydrofluoric acid
Mixed solution.
In other embodiments, the side wall of the groove of the formation can be vertical sidewall or alope sidewall, vertical sidewall
Refer to the side wall of groove vertically with the bottom surface of groove (or surface of substrate), sloped sidewall refers to the side wall and groove of groove
Bottom surface (or surface of substrate) have an angle.
In one embodiment, the forming process of the groove with vertical sidewall are as follows: using the drain region and side wall as exposure mask, carve
The semiconductor substrate of the semiconductor material layer and side wall is lost, rectangular recess is formed；Continue to etch the rectangular recess, so that square
The side wall of connected in star extends to the semiconductor substrate of side wall bottom.
In one embodiment, the groove is at least two discrete grooves, is located in semiconductor material layer and side
In the semiconductor substrate of wall two sides, i.e., it is not connect between adjacent sub- groove that the described groove, which includes at least two discrete sub- grooves,
Touching, at least two sub- grooves are located in the semiconductor substrate of semiconductor material layer and side wall two sides, it is subsequent can be
The semiconductor substrate of multiple bottom portion of groove forms multiple source regions accordingly, forms multiple grid knots accordingly in multiple grooves
Structure forms multiple channel regions accordingly in the semiconductor substrate of the side wall of multiple grooves, to increase the area of channel region.
In the present embodiment, the groove 206 is two discrete grooves, specific referring to FIG. 6, including the first sub- groove
206a and second sub- groove 206b, the first groove 206a and the second groove 206b are symmetrically distributed in drain region 203 and 204 liang of side wall
In the semiconductor substrate 200 of side.
In other embodiments, the groove is an annular groove, and the annular groove is located in drain region and side wall
In the semiconductor substrate of two sides, and the semiconductor substrate around drain region and side wall bottom further increases when groove is annular
The area of channel region improves the current driving ability for the transistor to be formed, specific referring to FIG. 7, the groove 206 is annular
Groove, annular groove 206 are located in the semiconductor substrate 200 of 204 two sides of drain region 203 and side wall, and around drain region 203 and side
The semiconductor substrate 200 of 204 bottom of wall.Need to illustrate when, when groove 206 is annular, the shallow trench isolation knot that is previously formed
Structure 205 is also annular, and circular semiconductor substrate is active area among fleet plough groove isolation structure 205.
Referring to FIG. 8, in the semiconductor substrate 200 of 206 bottom of groove formed source region 207, the source region 207 doped with
The foreign ion of Second Type.
The formation process of the source region 207 is heavy doping ion injection 21, the depth of the source region 207 be less than shallow trench every
Depth from structure 205.
In one embodiment, formed NMOS transistor when, heavy doping ion injection 21 injection Second Type impurity from
When son is arsenic ion or phosphonium ion, the dosage of injection is 1E15~1E25atom/cm2, the energy of injection is 10~30Kev, note
The angle entered is 0~5 degree.
In another embodiment, when forming PMOS transistor, the impurity of the Second Type of 21 injection of heavy doping ion injection
When ion is boron ion or indium ion, the dosage of injection is 2KeV~10KeV, and the energy of injection is 3e14~3e15/cm2, note
The angle entered is 0~5 degree.
In other embodiments, further includes: carry out shallow Doped ions injection, formed in the semiconductor substrate of bottom portion of groove
Lightly doped district, the doping type of the lightly doped district and the doping type of source region are identical, and the depth of lightly doped district is less than source region
Depth, the concentration impurity ion of lightly doped district is less than the concentration impurity ion of source region, formed lightly doped district purpose be in order to
It effectively prevent hot carrier injection effect.
In other embodiments, further includes: carry out bag-shaped ion implanting, form bag in the semiconductor substrate of bottom portion of groove
Shape injection region, the doping type of the bag-shaped injection region and the doping type of source region are on the contrary, the purpose for forming bag-shaped injection region is
It effectively prevent short-channel effect.
With reference to Fig. 9, separation layer 208 is formed on 207 surface of source region.
The material of the separation layer 208 is silicon nitride, the gate structure and source region that the separation layer 208 is used to be subsequently formed
207 isolation, and prevent the foreign ion in source region 207 from spreading to channel region.
In one embodiment, the forming process of the separation layer 208 are as follows: inject Nitrogen ion on the surface of source region 208；It carries out
Annealing process forms the separation layer of silicon nitride material on the surface of source region 208.Make the position precision for the separation layer 208 to be formed compared with
Height, and formation process will not have an impact the side wall of groove 206.
In one embodiment, the energy when N~+ implantation is 2KeV~10KeV, and dosage is 5e15~5e16/
cm2, it is located at Nitrogen ion near the surface of source region, and Nitrogen ion is uniformly distributed, it is uniform to form thickness in area surface
The silicon nitride of distribution, injection Nitrogen ion keep higher concentration, provide enough nitrogen sources to form silicon nitride, higher with consistency
Silicon nitride, 600~1000 DEG C of the temperature of the annealing process, time 1min~30min, atmosphere is inert gas, in annealing,
Nitrogen ion forms silicon nitride in conjunction with the element silicon in semiconductor substrate, and makes the silicon nitride thickness to be formed uniformly and consistency
It is higher.
In other embodiments, the material of the separation layer can be silica or silicon oxynitride, by 206 bottom of groove
Oxonium ion or oxonium ion and Nitrogen ion are injected in the semiconductor substrate in portion, then carry out carrying out annealing process under anaerobic atmosphere
It is formed.
With reference to Figure 10, after forming separation layer 208, gate dielectric layer 209 is formed in the sidewall surfaces of groove 206.
The material of the gate dielectric layer 209 is silica.
The formation process of the gate dielectric layer 209 is thermal oxidation technology or furnace oxidation technique.
With reference to Figure 11, after forming gate dielectric layer 209, the gate electrode 210 of filling groove 206 (referring to Figure 10) is formed.
The material of the gate electrode 210 is polysilicon.
210 formation process of gate electrode is chemical vapor deposition.
In one embodiment, when the groove 206 is at least two discrete groove, one is formed in corresponding each groove
A gate electrode, multiple gate electrodes are located in the semiconductor substrate of semiconductor material layer and side wall two sides.
When forming gate electrode 210, the multiple gate electrode 210 can pass through the partial polysilicon electricity in semiconductor substrate
It links together, in other embodiments, the multiple gate electrode 210 is also possible to separation, i.e., between Adjacent gate electrodes 210
It is separated.
In other embodiments, the groove is an annular groove, and the gate electrode formed accordingly is the grid of annular
The gate electrode of electrode, the annular is located in the semiconductor substrate of drain region and side wall two sides, and around drain region and side wall bottom
Semiconductor substrate.
The embodiment of the invention also provides a kind of transistors, please refer to Figure 11, comprising:
Semiconductor substrate 200, is formed with well region in the semiconductor substrate 200, doped with the first kind in the well region
Foreign ion；
Drain region 203 on 200 surface of semiconductor substrate, the drain region 203 doped with Second Type foreign ion,
The first kind is opposite with Second Type；
Side wall 204 in the sidewall surfaces in drain region 203；
Groove in the semiconductor substrate 200 of 204 two sides of drain region 203 and side wall；
Source region 207 in the semiconductor substrate 200 of bottom portion of groove, the source region 207 is doped with the miscellaneous of Second Type
Matter ion；
Separation layer 208 positioned at 207 surface of source region；
Positioned at the gate dielectric layer 209 of the sidewall surfaces of groove；
Positioned at gate dielectric layer 209 and 208 surface of separation layer and the gate electrode 210 of filling groove.
In one embodiment, also there is shallow doped region, the lightly doped district in the semiconductor substrate 200 of the bottom portion of groove
Doping type it is identical as the doping type of source region, and the depth of lightly doped district be less than source region depth, the impurity of lightly doped district
Ion concentration is less than the concentration impurity ion of source region.
In one embodiment, the drain region 203 includes the shallow doped region in the semiconductor substrate and is located at shallow doped region
On heavily doped region.
In one embodiment, the groove is at least two discrete grooves, is located in semiconductor material layer and side
In the semiconductor substrate of wall two sides.
In another embodiment, the groove is an annular groove, and the annular groove is located in drain region and side wall two
In the semiconductor substrate of side, and the semiconductor substrate around drain region and side wall bottom.
It should be noted that being please referred in previous embodiment in the present embodiment about other restrictions and description of transistor
The definitions relevant of transistor forming process part and description, details are not described herein.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of forming method of transistor characterized by comprising
Semiconductor substrate is provided, is formed with well region in the semiconductor substrate, doped with the impurity of the first kind in the well region
Ion；
Drain region, foreign ion of the drain region doped with Second Type, the first kind are formed on the semiconductor substrate surface
It is opposite with Second Type；
Sidewall surfaces in drain region form side wall；
Groove is formed in the semiconductor substrate of drain region and side wall two sides；
Source region, foreign ion of the source region doped with Second Type are formed in the semiconductor substrate of bottom portion of groove；
Separation layer is formed in area surface；
Gate dielectric layer is formed in the sidewall surfaces of groove；
After forming gate dielectric layer, the gate electrode of filling groove is formed.
2. the forming method of transistor as described in claim 1, which is characterized in that the forming process of the groove are as follows: with institute
It states drain region and side wall is exposure mask, etch the drain region and side wall semiconductor substrates on two sides, form the groove of sigma shape；Continue
The side wall of the groove of the sigma shape is etched, the groove with arcuation side wall is formed.
3. the forming method of transistor as described in claim 1, which is characterized in that the forming process of the groove are as follows: with institute
It states drain region and side wall is exposure mask, etch the semiconductor substrate of the semiconductor material layer and side wall, form rectangular recess；Continue to carve
The rectangular recess is lost, so that the side wall of rectangular recess extends to the semiconductor substrate of side wall bottom.
4. the forming method of transistor as described in claim 1, which is characterized in that the material of the separation layer is silicon nitride.
5. the forming method of transistor as claimed in claim 4, which is characterized in that the forming process of the separation layer are as follows: In
Nitrogen ion is injected on the surface of source region；It carries out annealing process and forms the separation layer of silicon nitride material on the surface of source region.
6. the forming method of transistor as claimed in claim 5, which is characterized in that the energy when N~+ implantation is
2KeV~10KeV, dosage are 5e15~5e16/cm2。
7. the forming method of transistor as claimed in claim 5, which is characterized in that the temperature 600 of the annealing process~
1000 DEG C, time 1min~30min, atmosphere is inert gas.
8. the forming method of transistor as described in claim 1, which is characterized in that the formation process of the source region is heavy doping
Ion implanting.
9. the forming method of transistor as claimed in claim 8, which is characterized in that heavy doping ion injection injection arsenic ion or
When phosphonium ion, the dosage of injection is 1E15~1E25atom/cm2, the energy of injection is 10~30Kev, the angle of injection is 0~
5 degree.
10. the forming method of transistor as claimed in claim 8, which is characterized in that heavy doping ion injection injection boron ion
Or when indium ion, the dosage of injection is 2KeV~10KeV, and the energy of injection is 3e14~3e15/cm2, the angle of injection is 0~
5 degree.
11. the forming method of transistor as described in claim 1, which is characterized in that further include: carry out shallow Doped ions note
Enter, forms lightly doped district, the doping type of the lightly doped district and the doping class of source region in the semiconductor substrate of bottom portion of groove
Type is identical, and the depth of lightly doped district is less than the depth of source region, the concentration impurity ion of lightly doped district be less than the impurity of source region from
Sub- concentration.
12. the forming method of transistor as claimed in claim 2, which is characterized in that further include: bag-shaped ion implanting is carried out,
Bag-shaped injection region, the doping type of the bag-shaped injection region and the doping class of source region are formed in the semiconductor substrate of bottom portion of groove
Type is opposite.
13. the forming method of transistor as described in claim 1, which is characterized in that the forming process in the drain region: described
Form semiconductor material layer in semiconductor substrate, the semiconductor material layer include first part and in first part
Two parts, doped with the foreign ion of Second Type in the semiconductor material layer, and the concentration impurity ion in first part
Less than the concentration impurity ion of second part；The semiconductor material layer is etched, forms drain region on the semiconductor substrate, institute
State the semiconductor material layer that the semiconductor material layer that drain region includes first part etches the shallow doped region and second part to be formed
Etch the heavily doped region formed.
14. the forming method of transistor as described in claim 1, which is characterized in that the groove is discrete at least two
Groove is located in the semiconductor substrate of semiconductor material layer and side wall two sides.
15. the forming method of transistor as described in claim 1, which is characterized in that the groove is an annular groove, institute
It states annular groove to be located in the semiconductor substrate of drain region and side wall two sides, and around the semiconductor of drain region and side wall bottom lining
Bottom.
16. a kind of transistor, which is characterized in that formed using the forming method of transistor as described in claim 1, comprising:
Semiconductor substrate, is formed with well region in the semiconductor substrate, doped with the foreign ion of the first kind in the well region；
Drain region on semiconductor substrate surface, foreign ion of the drain region doped with Second Type, the first kind and the
Two types are opposite；
Side wall in the sidewall surfaces in drain region；
Groove in the semiconductor substrate of drain region and side wall two sides；
Source region in the semiconductor substrate of bottom portion of groove, foreign ion of the source region doped with Second Type；
Positioned at the separation layer of area surface；
Positioned at the gate dielectric layer of the sidewall surfaces of groove；
Positioned at gate dielectric layer and insulation surface and the gate electrode of filling groove.
17. transistor as claimed in claim 16, which is characterized in that also have in the semiconductor substrate of the bottom portion of groove light
Doped region, the doping type of the lightly doped district and the doping type of source region are identical, and the depth of lightly doped district is less than source region
Depth, the concentration impurity ion of lightly doped district are less than the concentration impurity ion of source region.
18. transistor as claimed in claim 16, which is characterized in that the drain region includes light in semiconductor substrate
Doped region and the heavily doped region in lightly doped district.
19. transistor as claimed in claim 16, which is characterized in that the groove is at least two discrete grooves, respectively
In the semiconductor substrate in semiconductor material layer and side wall two sides.
20. transistor as claimed in claim 16, which is characterized in that the groove is an annular groove, and the annular is recessed
Slot position is in the semiconductor substrate in the semiconductor substrate of drain region and side wall two sides, and around drain region and side wall bottom.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5143859A (en) * | 1989-01-18 | 1992-09-01 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a static induction type switching device |
| CN101170126A (en) * | 2006-10-25 | 2008-04-30 | 国际商业机器公司 | Semiconductor structure and its manufacture method |
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| US7323745B2 (en) * | 2004-01-26 | 2008-01-29 | International Rectifier Corporation | Top drain MOSFET |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5143859A (en) * | 1989-01-18 | 1992-09-01 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a static induction type switching device |
| CN101170126A (en) * | 2006-10-25 | 2008-04-30 | 国际商业机器公司 | Semiconductor structure and its manufacture method |
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