CN106960791A - Transistor and forming method thereof - Google Patents
Transistor and forming method thereof Download PDFInfo
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- CN106960791A CN106960791A CN201610015637.7A CN201610015637A CN106960791A CN 106960791 A CN106960791 A CN 106960791A CN 201610015637 A CN201610015637 A CN 201610015637A CN 106960791 A CN106960791 A CN 106960791A
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- 238000000926 separation method Methods 0.000 claims abstract description 23
- 238000011049 filling Methods 0.000 claims abstract description 12
- 150000002500 ions Chemical class 0.000 claims description 77
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- 238000002347 injection Methods 0.000 claims description 42
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- 230000008569 process Effects 0.000 claims description 29
- -1 Nitrogen ion Chemical class 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 14
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- 229910052757 nitrogen Inorganic materials 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 7
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 5
- 229910001449 indium ion Inorganic materials 0.000 claims description 4
- 238000002513 implantation Methods 0.000 claims description 3
- 239000011261 inert gas Substances 0.000 claims description 2
- 238000009413 insulation Methods 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims 1
- 239000002210 silicon-based material Substances 0.000 claims 1
- 238000002955 isolation Methods 0.000 description 14
- 239000007789 gas Substances 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
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- 238000005229 chemical vapour deposition Methods 0.000 description 5
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- 238000007254 oxidation reaction Methods 0.000 description 3
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- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
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- 238000006243 chemical reaction Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- CKHJYUSOUQDYEN-UHFFFAOYSA-N gallium(3+) Chemical compound [Ga+3] CKHJYUSOUQDYEN-UHFFFAOYSA-N 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 241000828883 Alope Species 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- VLQGDKKHHCKIOJ-UHFFFAOYSA-N NNOS Chemical compound NNOS VLQGDKKHHCKIOJ-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 229910000070 arsenic hydride Inorganic materials 0.000 description 1
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- 229910052738 indium Inorganic materials 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
A kind of forming method of transistor and forming method thereof, wherein transistor, including：Foreign ion in well region, the well region doped with the first kind is provided in offer Semiconductor substrate, the Semiconductor substrate；Form drain region on the semiconductor substrate surface, the drain region is doped with the foreign ion of Second Type, and the first kind is opposite with Second Type；Sidewall surfaces formation side wall in drain region；Groove is formed in the Semiconductor substrate of drain region and side wall both sides；Source region, foreign ion of the source region doped with Second Type are formed in the Semiconductor substrate of bottom portion of groove；In area surface formation separation layer；In the sidewall surfaces formation gate dielectric layer of groove；Formed after gate dielectric layer, form the gate electrode of filling groove.The current driving ability lifting of the transistor of the inventive method formation, and reduce the generation of leakage current.
Description
Technical field
The present invention relates to field of semiconductor fabrication, more particularly to a kind of transistor and forming method thereof.
Background technology
Metal-oxide-semicondutor (MOS) transistor is the most basic device in semiconductor manufacturing, and its is wide
It is general suitable for various integrated circuits, it is different according to doping type when principal carrier and manufacture, point
For NMOS and PMOS transistor.
Prior art provides a kind of preparation method of MOS transistor, including：Semiconductor base is provided,
Semiconductor base between semiconductor base formation isolation structure, the isolation structure is active area,
Well region (not shown) is formed in the active area；By the first ion implanting in well region surface doping impurity
Ion, to adjust the threshold voltage for the transistor being subsequently formed；Semiconductor between the isolation structure
Gate dielectric layer and gate electrode are sequentially formed in substrate, the gate dielectric layer and gate electrode constitute grid structure；
Oxidation technology is carried out, the oxide layer of the covering grid structure is formed；Shallow Doped ions injection is carried out,
Source drain extension area is formed in the semiconductor base of grid structure both sides；It is right using the grid structure as mask
The well region of grid structure both sides carries out deep Doped ions injection, and the energy and dosage of deep Doped ions injection are big
The energy and dosage injected in shallow Doped ions, forms source region and drain region in the well region of grid structure both sides,
The source region and the depth in drain region are more than the depth in source drain extension area.
The performance of the transistor of prior art formation still has to be hoisted.
The content of the invention
The problem of present invention is solved is the current driving ability for how improving transistor.
To solve the above problems, the present invention provides a kind of forming method of transistor, including：
Semiconductor substrate is provided, is formed with well region, the well region in the Semiconductor substrate doped with the
The foreign ion of one type；Drain region is formed on the semiconductor substrate surface, the drain region is doped with
The foreign ion of two types, the first kind is opposite with Second Type；Sidewall surfaces formation side wall in drain region；
Groove is formed in the Semiconductor substrate of drain region and side wall both sides；The shape in the Semiconductor substrate of bottom portion of groove
Into source region, foreign ion of the source region doped with Second Type；In area surface formation separation layer；
The sidewall surfaces formation gate dielectric layer of groove；Formed after gate dielectric layer, form the gate electrode of filling groove.
Optionally, the forming process of the groove is：Using the drain region and side wall as mask, etching is described
Drain region and side wall semiconductor substrates on two sides, form the groove of sigma shapes；Continue to etch the sigma
The side wall of the groove of shape, forms the groove with arcuation side wall.
Optionally, the forming process of the groove is：Using the drain region and side wall as mask, etching is described
The Semiconductor substrate of semiconductor material layer and side wall, forms rectangular recess；Continue to etch the rectangular recess,
So that the side wall of rectangular recess extends to the Semiconductor substrate of side wall bottom.
Optionally, the material of the separation layer is silicon nitride.
Optionally, the forming process of the separation layer is：Nitrogen ion is injected on the surface of source region；Moved back
Ignition technique forms the separation layer of silicon nitride material on the surface of source region.
Optionally, energy when stating N~+ implantation is 2KeV~10KeV, and dosage is 5e15~5e16/cm2。
Optionally, 600~1000 DEG C of the temperature of the annealing process, time 1min~30min, atmosphere is lazy
Property gas.
Optionally, the formation process of the source region is injected for heavy doping ion.
Optionally, when arsenic ion or phosphonium ion are injected in heavy doping ion injection, the dosage of injection is
1E15~1E25atom/cm2, the energy of injection is 10~30Kev, and the angle of injection is 0~5 degree.
Optionally, when boron ion or indium ion are injected in heavy doping ion injection, the dosage of injection is
2KeV~10KeV, the energy of injection is 3e14~3e15/cm2, the angle of injection is 0~5 degree.
Optionally, also include：Carry out shallow Doped ions injection, the shape in the Semiconductor substrate of bottom portion of groove
Into lightly doped district, the doping type of the lightly doped district is identical with the doping type of source region, and lightly doped district
Depth be less than the depth of source region, the concentration impurity ion of lightly doped district is less than the concentration impurity ion of source region.
Optionally, also include：Bag-shaped ion implanting is carried out, is formed in the Semiconductor substrate of bottom portion of groove
Bag-shaped injection region, the doping type of the bag-shaped injection region is opposite with the doping type of source region.
Optionally, the forming process in the drain region：Semiconductor material layer is formed on the semiconductor substrate,
The semiconductor material layer includes Part I and the Part II on Part I, the semiconductor
Doped with the foreign ion of Second Type in material layer, and concentration impurity ion in Part I is less than the
The concentration impurity ion of two parts；The semiconductor material layer is etched, is formed on the semiconductor substrate
Drain region, the semiconductor material layer that the drain region includes Part I etches the shallow doped region and second to be formed
Partial semiconductor material layer etches the heavily doped region to be formed.
Optionally, the groove is at least two discrete grooves, respectively positioned in semiconductor material layer and
In the Semiconductor substrate of side wall both sides.
Optionally, the groove is an annular groove, and the annular groove is located in drain region and side wall two
In the Semiconductor substrate of side, and around the Semiconductor substrate in drain region and side wall bottom.
Present invention also offers a kind of transistor, including：
It is formed with Semiconductor substrate, the Semiconductor substrate in well region, the well region doped with the first kind
The foreign ion of type；Drain region on semiconductor substrate surface, the drain region is doped with Second Type
Foreign ion, the first kind is opposite with Second Type；Side wall in the sidewall surfaces in drain region；It is located at
Groove in the Semiconductor substrate of drain region and side wall both sides；Source in the Semiconductor substrate of bottom portion of groove
Area, foreign ion of the source region doped with Second Type；Positioned at the separation layer of area surface；Positioned at recessed
The gate dielectric layer of the sidewall surfaces of groove；Positioned at gate dielectric layer and insulation surface and the gate electrode of filling groove.
Optionally, also there is shallow doped region, the lightly doped district in the Semiconductor substrate of the bottom portion of groove
Doping type it is identical with the doping type of source region, and lightly doped district depth be less than source region depth, gently
The concentration impurity ion of doped region is less than the concentration impurity ion of source region.
Optionally, the drain region includes the shallow doped region being located in Semiconductor substrate and on shallow doped region
Heavily doped region.
Optionally, the groove is at least two discrete grooves, respectively positioned in semiconductor material layer and
In the Semiconductor substrate of side wall both sides.
Optionally, the groove is an annular groove, and the annular groove is located in drain region and side wall two
In the Semiconductor substrate of side, and around the Semiconductor substrate in drain region and side wall bottom.
Compared with prior art, technical scheme has advantages below：
The forming method of the transistor of the present invention, drain region is formed on the semiconductor substrate surface, in leakage
After the sidewall surfaces formation side wall in area；Groove is formed in the Semiconductor substrate of drain region and side wall both sides；
Source region, foreign ion of the source region doped with Second Type are formed in the Semiconductor substrate of bottom portion of groove；
In area surface formation separation layer；In the sidewall surfaces formation gate dielectric layer of groove；Formed after gate dielectric layer,
Form the gate electrode of filling groove.The three-dimensional raceway groove of multidimensional can be formed in the Semiconductor substrate of recess sidewall
Area, while the transistor for ensureing to be formed occupies less lateral dimension so that the area of channel region increases
Greatly so that channel region can improve the electric current driving energy to form transistor by bigger driving current
Power.In addition, forming grid structure in groove, grid structure is to shape in the Semiconductor substrate of recess sidewall
Into the three-dimensional channel region of multidimensional be controlled, improve grid structure to channel region control ability, prevent
The generation of leakage current.
Further, the semiconductor material layer includes Part I and the Part II on Part I,
Doped with the foreign ion of Second Type in the semiconductor material layer, and the foreign ion in Part I
Concentration is less than the concentration impurity ion of Part II, and the Part I of etching semiconductor material layer is subsequently formed
Lightly doped district, the Part II formation heavily doped region of etching semiconductor material layer, lightly doped district and heavy doping
Area constitutes drain region, and the purpose for forming lightly doped district is to effectively prevent hot carrier injection effect.
Further, the side wall of the groove is arcuation side wall, and arcuation side wall is partly led to drain region bottom
The direction of body substrate is raised, and the side wall of groove is in the purpose of arcuation：On the one hand, when being formed in a groove
Grid structure (gate electrode for including the gate dielectric layer positioned at recess sidewall and filling groove), in grid structure
During upper application operating voltage, point discharge is prevented；On the other hand, because side wall is arc, accordingly
It is also arc that channel region is formed in the Semiconductor substrate of recess sidewall, thus the transistor of the present invention can be with
While realization has the channel region length of equal length with existing transistor, drain region and groove-bottom are reduced
The distance of the source region formed in the Semiconductor substrate in portion.
Further, the groove is at least two discrete grooves, is served as a contrast in the semiconductor of multiple bottom portion of groove
Bottom forms multiple source regions accordingly, forms multiple grid structures accordingly in multiple grooves, multiple recessed
Multiple channel regions are formed accordingly in the Semiconductor substrate of the side wall of groove, so as to add the area of channel region.
Further, the groove is an annular groove, and the annular groove is located in drain region and side wall
In the Semiconductor substrate of both sides, and around the Semiconductor substrate in drain region and side wall bottom, when groove is annular,
The area of channel region is further increased, the current driving ability for the transistor to be formed is improved.
The three-dimensional channel region of multidimensional can be formed in the transistor of the present invention, the Semiconductor substrate of recess sidewall,
While the transistor for ensureing to be formed occupies less lateral dimension so that the area increase of channel region,
Allow channel region by bigger driving current, improve the current driving ability to form transistor.
In addition, form grid structure in groove, grid structure in the Semiconductor substrate of recess sidewall to forming
The three-dimensional channel region of multidimensional is controlled, and improves grid structure to channel region control ability, prevents electric leakage
The generation of stream.
Brief description of the drawings
Fig. 1~Figure 11 is the structural representation of embodiment of the present invention transistor forming process.
Embodiment
Performance such as the transistor that background technology is sayed, prior art is formed still has to be hoisted, such as existing
The current driving ability of the transistor of technology formation still has to be hoisted.
Research find, the transistor of prior art operationally, the Semiconductor substrate in grid structure bottom
Middle formation channel region, the channel region is planar channeling, with the continuous reduction of characteristic size, channel region
Size (such as width and length) is limited by the structure of the transistor of existing formation, thus channel region
The size of current passed through is conditional so that the driving force of electric current is still limited.
It is this invention provides a kind of transistor and forming method thereof, on the semiconductor substrate surface
Drain region is formed, after the sidewall surfaces formation side wall in drain region；Semiconductor substrate in drain region and side wall both sides
Interior formation groove；Source region is formed in the Semiconductor substrate of bottom portion of groove, the source region is doped with Equations of The Second Kind
The foreign ion of type；In area surface formation separation layer；In the sidewall surfaces formation gate dielectric layer of groove；
Formed after gate dielectric layer, form the gate electrode of filling groove.Can be with shape in the Semiconductor substrate of recess sidewall
Into the three-dimensional channel region of multidimensional, while the transistor for ensureing to be formed occupies less lateral dimension, make
Obtain the area increase of channel region so that channel region can be improved to form crystalline substance by bigger driving current
The current driving ability of body pipe.In addition, forming grid structure in groove, grid structure is to recess sidewall
Semiconductor substrate in the three-dimensional channel region of multidimensional that is formed be controlled, improve grid structure to raceway groove
Area's control ability, prevents the generation of leakage current.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings
The specific embodiment of the present invention is described in detail.When the embodiment of the present invention is described in detail, for purposes of illustration only,
Schematic diagram can disobey general ratio and make partial enlargement, and the schematic diagram is example, and it should not herein
Limit the scope of the invention.In addition, the three of length, width and depth should be included in actual fabrication
Dimension space size.
Fig. 1~Figure 11 is the structural representation of embodiment of the present invention transistor forming process.
With reference to Fig. 1 and Fig. 2 there is provided Semiconductor substrate 200, trap is formed with the Semiconductor substrate 200
Doped with the foreign ion of the first kind in area's (not shown), the well region；In semiconductor lining
On the surface of bottom 200 formed drain region 203, the drain region 203 doped with Second Type foreign ion, first
Type is opposite with Second Type.
The material of the Semiconductor substrate 200 can for silicon (Si), germanium (Ge) or SiGe (GeSi),
Carborundum (SiC)；Can also be silicon-on-insulator (SOI), germanium on insulator (GOI)；Or may be used also
Think other materials, III-V compounds of group such as GaAs.In the present embodiment, the semiconductor lining
The material at bottom 200 is silicon.In the present embodiment, the material of the Semiconductor substrate 200 is silicon.
Fleet plough groove isolation structure 205, the shallow trench isolation junction are also formed with the Semiconductor substrate 200
Structure 205 is used to isolate adjacent active area.In one embodiment, the shape of fleet plough groove isolation structure 205
It is into process：The Semiconductor substrate is etched, groove is formed；Using depositing operation formation covering described half
Conductor substrate and the spacer material layer for filling full groove；Planarization removes the isolation on semiconductor substrate surface
Material layer, forms fleet plough groove isolation structure in the trench.
Well region, the trap are formed with Semiconductor substrate 200 between the fleet plough groove isolation structure 205
Area can form the well region doped with the foreign ion of the first kind by ion implantation technology.
In one embodiment, the forming process in the drain region 203 is：In the Semiconductor substrate 200
The foreign ion doped with Second Type in semiconductor material layer 201, the semiconductor material layer 201 is formed,
Second Type is opposite with the first kind；Form patterned hard on the surface of semiconductor material layer 201
Mask layer 202；It is mask with the patterned hard mask layer 202, etches the semiconductor material layer
201, drain region 203 is formed in the Semiconductor substrate 200.
The drain region 203 is located above active area (or well region), or positioned at adjacent shallow trench isolation junction
In Semiconductor substrate between structure 205, the patterned hard mask layer 202 can be silica, nitrogen
SiClx or other suitable mask materials.
The material of the semiconductor material layer 201 is silicon, SiGe or carborundum.The semiconductor material layer
201 formation process is chemical vapor deposition.In the present embodiment, the material of the semiconductor material layer 201
For silicon, the thickness of semiconductor material layer 201 is 500~2000 angstroms.
It can be entrained in chemical vapor deposition method formation semiconductor material layer 201 by original position described
The foreign ion of the Second Type adulterated in semiconductor material layer 201.In other embodiments, Ke Yitong
Ion implantation technology is crossed to adulterate in semiconductor material layer the foreign ion of Second Type.
In one embodiment, the semiconductor material layer 201 includes Part I and on Part I
Part II, doped with the foreign ion of Second Type in the semiconductor material layer, and Part I
In concentration impurity ion be less than Part II concentration impurity ion, etching semiconductor material layer first
Part is subsequently formed lightly doped district, and the Part II formation heavily doped region of etching semiconductor material layer is gently mixed
Miscellaneous area and heavily doped region constitute drain region, and the purpose for forming lightly doped district is to effectively prevent that hot carrier from noting
Enter effect.
In one embodiment, when the material of semiconductor material layer 201 is silicon, chemical vapor deposition method shape
Into during the semiconductor material layer：Chamber temp is 650-800 degrees Celsius, and chamber pressure is 5-20torr,
Silicon source gas is SiH4Or SiCl2H4, the flow of silicon source gas is 30-200sccm, chemical vapor deposition work
Skill also includes being passed through impurity source gas, and deposition process includes first stage and second stage, in the first stage
(to first time point since deposition), forms the Part I of semiconductor material layer 201, the impurity
The flow of source gas is first flow；In second stage (from first time point to the second time point), formed
The Part II of semiconductor material layer, the thickness of Part II is more than the thickness of Part I, the impurity
Source gas is second flow, and second flow is more than first flow, and the duration of second stage is more than the
The duration in one stage, in one embodiment, the first flow are 5~200sccm, the second
Measure as 40~800sccm.To cause Part I and Part II in the semiconductor material layer 201 to be formed
It is follow-up uniform, and the concentration impurity ion in Part I and Part II is more accurate, and impurity
The distribution of ion is more uniform.
According to the difference for forming transistor, during the species of the foreign ion adulterated in well region and drain region 203 not
With, when forming NNOS transistors, the foreign ion for the first kind adulterated in the well region is boron
One or more in ion, gallium ion or indium ion, the Second Type that the drain region 203 is adulterated it is miscellaneous
Matter ion is the one or more in phosphonium ion, arsenic ion or antimony ion；When forming PMOS transistor,
The foreign ion for the first kind adulterated in the well region is one kind in phosphonium ion, arsenic ion or antimony ion
Or it is several, the foreign ion of the Second Type that the drain region 203 is adulterated for boron ion, gallium ion or indium from
One or more in son.
In the present embodiment, to form nmos pass transistor as an example, forming semiconductor material layer accordingly
201 impurity source gas is PH3Or AsH3.In other embodiments, when forming PMOS transistor,
The impurity source gas can be BF3。
With reference to Fig. 3, the sidewall surfaces formation side wall 204 in drain region 203.
The side wall 204 forms the position of groove in subsequent etching Semiconductor substrate formation groove for control
Put, and for protecting the side wall in drain region 204.
The material of the side wall 204 can be the one or more in silicon nitride, silica, silicon oxynitride.
The side wall 204 can be single or multiple lift (>=2 layers) stacked structure.
In the present embodiment, the side wall 204 also covers the side wall table of the patterned hard mask layer 202
Face.
In one embodiment, the forming process of the side wall 204 is：Form the covering Semiconductor substrate
200th, the spacer material layer on the surface of hard mask layer 202 of drain region 203 and image conversion；Using without mask etching
Technique etches the spacer material layer；In the side of the drain region 203 (and hard mask layer 202 of image conversion)
Wall surface formation side wall 204.
With reference to doping Fig. 4 and Fig. 5, the shape in the Semiconductor substrate 200 of drain region 203 and the both sides of side wall 204
Into groove 206.
In the present embodiment, the purpose of groove 206 is formed：On the one hand, after groove 206 is formed, subsequently
Source region can be formed in the Semiconductor substrate of the bottom of groove 206；On the other hand, recess sidewall is partly led
Body substrate can subsequently form the three-dimensional channel region of multidimensional in (bottom of drain region 203), ensure what is formed
While transistor occupies less lateral dimension so that the area increase of channel region so that channel region can
By bigger driving current, to improve the current driving ability to form transistor；Another further aspect, after
Continue and grid structure is formed in groove, grid structure is to the multidimensional that is formed in the Semiconductor substrate of recess sidewall
Three-dimensional channel region be controlled, improve grid structure to channel region control ability, prevent leakage current
Produce.
The depth of the groove 206 is less than the depth of fleet plough groove isolation structure 205.
In one embodiment, the side wall of the groove 206 is arcuation side wall, and arcuation side wall is to drain region
The direction of the Semiconductor substrate of 203 bottoms is raised, and the side wall of groove 206 is in the purpose of arcuation：On the one hand,
Subsequently forming grid structure in a groove (includes the grid of the gate dielectric layer positioned at recess sidewall and filling groove
Electrode), when applying operating voltage on grid structure, prevent point discharge；On the other hand, due to side wall
It is arc, it is also arc that channel region is formed in the Semiconductor substrate of corresponding recess sidewall, thus this
While the transistor of invention can realize the channel region length for having equal length with existing transistor, subtract
The distance of the source region formed in the small Semiconductor substrate in drain region 203 and the bottom of groove 206.
In one embodiment, the forming process of the groove 206 with arcuation side wall is：With the drain region 203
It is mask with side wall 204, etches the Semiconductor substrate 200 of the drain region 203 and the both sides of side wall 204, shape
Into the groove 216 of sigma shapes；Continue the side wall of the groove 216 of the etching sigma shapes, formed
Groove 206 with arcuation side wall.
The forming process of the groove 216 of sigma shapes is：It is mask with the drain region 203 and side wall 204,
The Semiconductor substrate of drain region 203 and the both sides of side wall 204 is etched using isotropic dry etch process
200, rectangular recess is formed in the semiconductor substrate, and the dry etch process is used in one embodiment
Gas includes：CF4, HBr, He and O2, CF4Gas flow be 20-200sccm, HBr gas
Body flow is 50-1000sccm, and He gas flow is 200-1000sccm, O2Gas flow be
5-20sccm, chamber temp is 40-80 DEG C, and chamber pressure is 5-50mTorr, and radio-frequency power is 400-750W,
Bias power is 0-100W, and etch period is 20-80S；Then the square is etched using wet-etching technology
Connected in star, forms the groove 216 of sigma shapes, in one embodiment, and the wet-etching technology is used
There is the etching solution TMAH solution or NH of different etching speed to different crystal orientations3.H2O solution,
TMAH solution or NH3.H2The mass percent of O solution is 1%-5%, and etch period is 20-80S.
Continue the side wall of the groove 216 of the etching sigma shapes, form the groove with arcuation side wall
206 use wet-etching technology, in one embodiment, the etching solution that the wet-etching technology is used for
The mixed solution of nitric acid or nitric acid and hydrofluoric acid.
In other embodiments, the side wall of the groove of the formation can be vertical sidewall or alope sidewall,
Vertical sidewall refers to the lower surface (or surface of substrate) of the side wall of groove vertically with groove, sloped sidewall
Refer to that the side wall of groove and the lower surface (or surface of substrate) of groove have an angle.
In one embodiment, the forming process of the groove with vertical sidewall is：With the drain region and side wall
For mask, the Semiconductor substrate of the semiconductor material layer and side wall is etched, rectangular recess is formed；Continue
Etch the rectangular recess so that the side wall of rectangular recess extends to the Semiconductor substrate of side wall bottom.
In one embodiment, the groove is at least two discrete grooves, respectively positioned in semiconductor material
In the Semiconductor substrate of the bed of material and side wall both sides, i.e., described groove includes at least two discrete sub- grooves,
It is discontiguous between adjacent sub- groove, at least two sub- grooves are located in semiconductor material layer and side respectively
In the Semiconductor substrate of wall both sides, subsequently can accordingly it be formed in the Semiconductor substrate of multiple bottom portion of groove
Multiple source regions, form multiple grid structures accordingly in multiple grooves, the half of the side wall of multiple grooves
Multiple channel regions are formed in conductor substrate accordingly, so as to add the area of channel region.
In the present embodiment, the groove 206 is two discrete grooves, specifically refer to Fig. 6, including the
Points of the one sub- sub- groove 206b of groove 206a and second, the first groove 206a and the second groove 206b symmetrically
Cloth is in the Semiconductor substrate 200 of drain region 203 and the both sides of side wall 204.
In other embodiments, the groove is an annular groove, and the annular groove is located in leakage
In the Semiconductor substrate of area and side wall both sides, and around the Semiconductor substrate in drain region and side wall bottom, groove
During for annular, the area of channel region is further increased, the electric current driving energy for the transistor to be formed is improved
Power, specifically refer to Fig. 7, and the groove 206 is annular groove, and annular groove 206 is located in drain region
203 and the both sides of side wall 204 Semiconductor substrate 200 in, and around drain region 203 and the bottom of side wall 204
Semiconductor substrate 200.Need explanation when, groove 206 for annular when, be previously formed shallow trench isolation
Structure 205 is also annular, and circular Semiconductor substrate is active area in the middle of fleet plough groove isolation structure 205.
Fig. 8 is refer to, source region 207, the source are formed in the Semiconductor substrate 200 of the bottom of groove 206
Foreign ion of the area 207 doped with Second Type.
The formation process of the source region 207 is heavy doping ion injection 21, and the depth of the source region 207 is small
In the depth of fleet plough groove isolation structure 205.
In one embodiment, when forming nmos pass transistor, the Equations of The Second Kind of the injection of heavy doping ion injection 21
When the foreign ion of type is arsenic ion or phosphonium ion, the dosage of injection is 1E15~1E25atom/cm2, injection
Energy be 10~30Kev, the angle of injection is 0~5 degree.
In another embodiment, when forming PMOS transistor, the second of the injection of heavy doping ion injection 21
When the foreign ion of type is boron ion or indium ion, the dosage of injection is 2KeV~10KeV, injection
Energy is 3e14~3e15/cm2, the angle of injection is 0~5 degree.
In other embodiments, also include：Shallow Doped ions injection is carried out, in the semiconductor of bottom portion of groove
Lightly doped district is formed in substrate, the doping type of the lightly doped district is identical with the doping type of source region, and
The depth of lightly doped district is less than the depth of source region, and the concentration impurity ion of lightly doped district is less than the impurity of source region
Ion concentration, the purpose for forming lightly doped district is to effectively prevent hot carrier injection effect.
In other embodiments, also include：Bag-shaped ion implanting is carried out, is served as a contrast in the semiconductor of bottom portion of groove
Bag-shaped injection region, the doping type of the bag-shaped injection region and the doping type of source region are formed in bottom on the contrary,
The purpose for forming bag-shaped injection region is effectively to prevent short-channel effect.
With reference to Fig. 9, separation layer 208 is formed on the surface of source region 207.
The material of the separation layer 208 is silicon nitride, and the separation layer 208 is used for the grid being subsequently formed
Structure is isolated with source region 207, and prevents that the foreign ion in source region 207 from spreading to channel region.
In one embodiment, the forming process of the separation layer 208 is：Injected on the surface of source region 208
Nitrogen ion；Carry out annealing process and form the separation layer of silicon nitride material on the surface of source region 208.Make to be formed
Separation layer 208 positional precision it is higher, and formation process will not produce shadow to the side wall of groove 206
Ring.
In one embodiment, the energy during N~+ implantation is 2KeV~10KeV, and dosage is
5e15~5e16/cm2, Nitrogen ion is located at the near surface of source region, and make it that Nitrogen ion is uniformly distributed, with
In the area surface formation equally distributed silicon nitride of thickness, injection Nitrogen ion keeps higher concentration, to be formed
Silicon nitride provides enough nitrogen sources, with the higher silicon nitride of consistency, the temperature of the annealing process
600~1000 DEG C, time 1min~30min, atmosphere is inert gas, and in annealing, Nitrogen ion is with partly leading
Element silicon in body substrate combines to form silicon nitride, and causes the silicon nitride thickness of formation uniform and consistency
It is higher.
In other embodiments, the material of the separation layer can be silica or silicon oxynitride, by
Oxonium ion or oxonium ion and Nitrogen ion are injected in the Semiconductor substrate of the bottom of groove 206, is then carried out
Annealing process is carried out under anaerobic atmosphere to be formed.
With reference to Figure 10, formed after separation layer 208, in the sidewall surfaces formation gate dielectric layer 209 of groove 206.
The material of the gate dielectric layer 209 is silica.
The formation process of the gate dielectric layer 209 is thermal oxidation technology or furnace oxidation technique.
With reference to Figure 11, formed after gate dielectric layer 209, form the grid of filling groove 206 (referring to Figure 10)
Electrode 210.
The material of the gate electrode 210 is polysilicon.
The formation process of gate electrode 210 is chemical vapor deposition.
In one embodiment, it is corresponding each recessed when the groove 206 is at least two discrete groove
A gate electrode is formed in groove, multiple gate electrodes are located at half in semiconductor material layer and side wall both sides respectively
In conductor substrate.
When forming gate electrode 210, the multiple gate electrode 210 can pass through the portion in Semiconductor substrate
Point polysilicon is electrically connected, in other embodiments, and the multiple gate electrode 210 can also be point
From, i.e., it is separated between Adjacent gate electrodes 210.
In other embodiments, the groove is an annular groove, and the gate electrode formed accordingly is
The gate electrode of annular, the annular gate electrode is located in the Semiconductor substrate of drain region and side wall both sides,
And around the Semiconductor substrate in drain region and side wall bottom.
The embodiment of the present invention additionally provides a kind of transistor, refer to Figure 11, including：
Be formed with Semiconductor substrate 200, the Semiconductor substrate 200 in well region, the well region doped with
The foreign ion of the first kind；
Drain region 203 on the surface of Semiconductor substrate 200, the drain region 203 is doped with Second Type
Foreign ion, the first kind is opposite with Second Type；
Side wall 204 in the sidewall surfaces in drain region 203；
Groove in the Semiconductor substrate 200 of drain region 203 and the both sides of side wall 204；
Source region 207 in the Semiconductor substrate 200 of bottom portion of groove, the source region 207 is doped with second
The foreign ion of type；
Separation layer 208 positioned at the surface of source region 207；
Positioned at the gate dielectric layer 209 of the sidewall surfaces of groove；
Positioned at gate dielectric layer 209 and the surface of separation layer 208 and the gate electrode 210 of filling groove.
In one embodiment, also there is shallow doped region, institute in the Semiconductor substrate 200 of the bottom portion of groove
The doping type for stating lightly doped district is identical with the doping type of source region, and the depth of lightly doped district is less than source region
Depth, the concentration impurity ion of lightly doped district is less than the concentration impurity ion of source region.
In one embodiment, the drain region 203 includes the shallow doped region being located in Semiconductor substrate and is located at
Heavily doped region on shallow doped region.
In one embodiment, the groove is at least two discrete grooves, respectively positioned in semiconductor material
In the Semiconductor substrate of the bed of material and side wall both sides.
In another embodiment, the groove is an annular groove, and the annular groove is located in drain region
In the Semiconductor substrate of side wall both sides, and around the Semiconductor substrate in drain region and side wall bottom.
It should be noted that other restrictions and description in the present embodiment on transistor, refer to foregoing
The definitions relevant of transistor forming process part and description, will not be repeated here in embodiment.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, it can make various changes or modifications, therefore the guarantor of the present invention
Shield scope should be defined by claim limited range.
Claims (20)
1. a kind of forming method of transistor, it is characterised in that including：
There is provided and be formed with Semiconductor substrate, the Semiconductor substrate in well region, the well region doped with first
The foreign ion of type；
Form drain region on the semiconductor substrate surface, the drain region doped with Second Type foreign ion,
The first kind is opposite with Second Type；
Sidewall surfaces formation side wall in drain region；
Groove is formed in the Semiconductor substrate of drain region and side wall both sides；
Form source region in the Semiconductor substrate of bottom portion of groove, the source region doped with Second Type impurity from
Son；
In area surface formation separation layer；
In the sidewall surfaces formation gate dielectric layer of groove；
Formed after gate dielectric layer, form the gate electrode of filling groove.
2. the forming method of transistor as claimed in claim 1, it is characterised in that the formation of the groove
Cheng Wei：Using the drain region and side wall as mask, the drain region and side wall semiconductor substrates on two sides are etched,
Form the groove of sigma shapes；Continue the side wall of the groove of the etching sigma shapes, form tool
There is the groove of arcuation side wall.
3. the forming method of transistor as claimed in claim 1, it is characterised in that the formation of the groove
Cheng Wei：Using the drain region and side wall as mask, the semiconductor of the semiconductor material layer and side wall is etched
Substrate, forms rectangular recess；Continue to etch the rectangular recess so that the side wall of rectangular recess is to side
The Semiconductor substrate extension of wall bottom.
4. the forming method of transistor as claimed in claim 1, it is characterised in that the material of the separation layer
For silicon nitride.
5. the forming method of transistor as claimed in claim 4, it is characterised in that the formation of the separation layer
Process is：Nitrogen ion is injected on the surface of source region；Carry out annealing process and form nitridation on the surface of source region
The separation layer of silicon materials.
6. the forming method of transistor as claimed in claim 5, it is characterised in that during the N~+ implantation
Energy be 2KeV~10KeV, dosage be 5e15~5e16/cm2。
7. the forming method of transistor as claimed in claim 5, it is characterised in that the temperature of the annealing process
600~1000 DEG C of degree, time 1min~30min, atmosphere is inert gas.
8. the forming method of transistor as claimed in claim 1, it is characterised in that the formation work of the source region
Skill is injected for heavy doping ion.
9. the forming method of transistor as claimed in claim 8, it is characterised in that heavy doping ion injection note
When entering arsenic ion or phosphonium ion, the dosage of injection is 1E15~1E25atom/cm2, the energy of injection is
10~30Kev, the angle of injection is 0~5 degree.
10. the forming method of transistor as claimed in claim 8, it is characterised in that heavy doping ion injection note
When entering boron ion or indium ion, the dosage of injection is 2KeV~10KeV, and the energy of injection is
3e14~3e15/cm2, the angle of injection is 0~5 degree.
11. the forming method of transistor as claimed in claim 1, it is characterised in that also include：Carry out shallow mix
Heteroion is injected, and lightly doped district is formed in the Semiconductor substrate of bottom portion of groove, the lightly doped district
Doping type is identical with the doping type of source region, and depth of the depth less than source region of lightly doped district, gently
The concentration impurity ion of doped region is less than the concentration impurity ion of source region.
12. the forming method of transistor as claimed in claim 2, it is characterised in that also include：Carry out bag-shaped
Ion implanting, forms bag-shaped injection region, the bag-shaped injection region in the Semiconductor substrate of bottom portion of groove
Doping type it is opposite with the doping type of source region.
13. the forming method of transistor as claimed in claim 1, it is characterised in that the formation in the drain region
Journey：Semiconductor material layer is formed on the semiconductor substrate, and the semiconductor material layer includes first
Doped with Second Type in part and the Part II on Part I, the semiconductor material layer
Foreign ion, and concentration impurity ion in Part I is less than the concentration impurity ion of Part II；
The semiconductor material layer is etched, drain region is formed on the semiconductor substrate, the drain region includes
The semiconductor material layer of Part I etches the semiconductor material layer of the shallow doped region to be formed and Part II
Etch the heavily doped region formed.
14. the forming method of transistor as claimed in claim 1, it is characterised in that the groove is discrete
At least two grooves, respectively in the Semiconductor substrate in semiconductor material layer and side wall both sides.
15. the forming method of transistor as claimed in claim 1, it is characterised in that the groove is a ring
Connected in star, the annular groove is located in the Semiconductor substrate of drain region and side wall both sides, and around leakage
Area and the Semiconductor substrate of side wall bottom.
16. a kind of transistor, it is characterised in that including：
It is formed with Semiconductor substrate, the Semiconductor substrate in well region, the well region doped with the first kind
Foreign ion；
Drain region on semiconductor substrate surface, the drain region doped with Second Type foreign ion,
One type is opposite with Second Type；
Side wall in the sidewall surfaces in drain region；
Groove in the Semiconductor substrate of drain region and side wall both sides；
Source region in the Semiconductor substrate of bottom portion of groove, the source region doped with Second Type impurity from
Son；
Positioned at the separation layer of area surface；
Positioned at the gate dielectric layer of the sidewall surfaces of groove；
Positioned at gate dielectric layer and insulation surface and the gate electrode of filling groove.
17. transistor as claimed in claim 16, it is characterised in that in the Semiconductor substrate of the bottom portion of groove
Also there is shallow doped region, the doping type of the lightly doped district is identical with the doping type of source region, and gently
The depth of doped region is less than the depth of source region, and the concentration impurity ion of lightly doped district is less than the impurity of source region
Ion concentration.
18. transistor as claimed in claim 16, it is characterised in that the drain region includes being located at Semiconductor substrate
On shallow doped region and the heavily doped region on shallow doped region.
19. transistor as claimed in claim 16, it is characterised in that the groove is that discrete at least two are recessed
Groove, respectively in the Semiconductor substrate in semiconductor material layer and side wall both sides.
20. transistor as claimed in claim 16, it is characterised in that the groove is an annular groove, institute
Annular groove is stated to be located in the Semiconductor substrate of drain region and side wall both sides, and around drain region and side wall bottom
The Semiconductor substrate in portion.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5143859A (en) * | 1989-01-18 | 1992-09-01 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a static induction type switching device |
| US20050194636A1 (en) * | 2004-01-26 | 2005-09-08 | International Rectifier Corp. | Top drain MOSFET |
| CN101170126A (en) * | 2006-10-25 | 2008-04-30 | 国际商业机器公司 | Semiconductor structure and its manufacture method |
-
2016
- 2016-01-11 CN CN201610015637.7A patent/CN106960791B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5143859A (en) * | 1989-01-18 | 1992-09-01 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a static induction type switching device |
| US20050194636A1 (en) * | 2004-01-26 | 2005-09-08 | International Rectifier Corp. | Top drain MOSFET |
| CN101170126A (en) * | 2006-10-25 | 2008-04-30 | 国际商业机器公司 | Semiconductor structure and its manufacture method |
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