CN105427886A - Step-by-step data addition method for NAND Flash storage system during storage period - Google Patents
Step-by-step data addition method for NAND Flash storage system during storage period Download PDFInfo
- Publication number
- CN105427886A CN105427886A CN201510868174.4A CN201510868174A CN105427886A CN 105427886 A CN105427886 A CN 105427886A CN 201510868174 A CN201510868174 A CN 201510868174A CN 105427886 A CN105427886 A CN 105427886A
- Authority
- CN
- China
- Prior art keywords
- data
- labeled
- data block
- nandflash
- storer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- Read Only Memory (AREA)
Abstract
The invention discloses a step-by-step data addition method for an NAND Flash storage system during a storage period. The addition method comprises the following steps: after data are written in an NAND Flash memory, judging whether a data block in which the written data are located is completely written or not, and judging whether the data block belongs to a high-wear block or not; if the data block is completely written and belongs to the high-wear block, marking the data block and recording data updating time; during a data period, querying implementation time of previous data addition operation of the marked data block, and judging whether the implementation time reaches a preset time interval or not; and if the implementation time reaches the preset time interval, performing data addition on the marked data block, and updating the implementation time of the data addition operation. According to the step-by-step data addition method during the storage period, the data retention error rate can be reduced and the data storage reliability can be improved.
Description
Technical field
The invention belongs to technical field of data storage, particularly relate to data substep emphasis method between a kind of NANDFlash storage system storage life.
Background technology
NANDFLASH storer has benefited from numerous advantages such as its height is handled up, low power consumption, shatter-proof, stability is high, low temperature resistant, thermal value is little, operating noise is low, at mobile phone, digital camera, USB flash disk, MP3, the fields such as panel computer, PC, high-performance computer, defense industry have wide market outlook.
For meeting the market active demand growing to NANDFlash memory span, NANDFLASH storer presents process and constantly to reduce and MLC (Multi-LevelCell, many level cell) technology extensively uses two developing directions.But effectively promoting memory capacity, while reducing per bit data carrying cost, NANDFLASH faces more serious integrity problem equally.
In structure, NANDFLASH storer is the preservation realizing data based on floating gate charge storage, as shown in Fig. 1 (a).But, between data retention period, the floating gate charge of NANDFlash storer leaks and causes floating gate charge quantity to reduce, as shown in Fig. 1 (b), the loss of floating gate charge will cause error in data to produce, as shown in Fig. 1 (c), floating gate charge loss constantly accumulation, causes data retention failures.Along with NANDFLASH process constantly reduces, the physical dimension of the storage unit floating gate structure of NANDFlash storer constantly reduces, cause the reduction of floating gate charge stored number, meanwhile, the utilization of MLC technology makes the change of data to floating gate charge quantity more responsive, thus causes data to keep increasing sharply of the bit error rate.
The program/erase number of times that the mass loss rates of NANDFLASH storer floating gate charge and its storage unit stand has close association.Carrying out in program/erase operations process to NANDFlash memory cell, putting on highfield on storage unit tunnel oxide will the generation of induced oxidation layer defects, thus cause tunnel oxide decreasing insulating, thus the escape probability of floating gate charge is increased.At the high eroded area of NANDFlash storer, storage unit tunnel oxide layer defects constantly accumulates, and floating gate charge quantity between data retention period is declined rapidly, thus causes serious data retention failures.
Along with NANDFlash memory process size constantly reduces and the extensive utilization of MLC technology, data retention failures rate too high in high eroded area has become the key factor of restriction NANDFLASH data reliability.The data being illustrated in figure 2 a typical commercial MLCNANDFLASH storer keep the curve synoptic diagram of the variation tendency of the bit error rate and storage unit program/erase number of times and time data memory.Between data retention period, NANDFlash memory data keeps mistake to raise rapidly with the increase of the storage time of storage unit program/erase number of times and data, and the degree of wear of storage unit keeps error rate to have appreciable impact on data.As shown in Figure 2, after the experience data retention over time of 4 years, live through the NANDFlash storer of 6000 program/erases, its data retention failures rate is 7 times in experience 3000 program/erase situations.Data retention failures rate too high in high eroded area has become the key factor of restriction NANDFLASH data reliability.
In real system application, according to different application scenarios and data type, the reliable retention time demand of data has very big-difference.Wherein, for data types such as film, music, archive file, backup files, after system creation, often do not change and refresh operation it for a long time, simultaneity factor requires the reliable preservation realizing such data within very long period.Because retention time demand is longer, in the storing process of data, the integrity problem of such data becomes one of significant challenge that NANDFlash storer faces.
Summary of the invention
The present invention is intended to solve one of technical matters in correlation technique at least to a certain extent.For this reason, the present invention needs to propose data substep emphasis method between a kind of NANDFlash storage system storage life, and the method can reduce data retention failures rate, promotes data storing reliability.
In order to solve the problem, the embodiment of the present invention proposes data substep emphasis method between a kind of NANDFlash storage system storage life, the method comprises the following steps: after NANDFlash storer write data, judge whether write data place data block is fully written, and judge whether described data block belongs to high wear block; If described data block is fully written and belongs to high wear block, then described data block is marked, and record the Data Update time; Between data retention period, inquire about the enforcement time that the last data of the data block be labeled add retry, and judge whether the described enforcement time reaches prefixed time interval; And if the described enforcement time reaches described prefixed time interval, then carry out data to the described data block be labeled and increase the weight of, and more new data increases the weight of to operate the enforcement time.
According to data substep emphasis method between the NANDFlash storage system storage life of the embodiment of the present invention, by marking high wear block after data write, between data retention period, when be labeled data block add retry implement the time reach preset interval time time, substep is carried out to this mark data block and increases the weight of process, the data retention failures rate caused due to the accumulation of floating gate charge leak data during memory cell data keeps can be reduced, effectively promote the reliability that NANDFlash memory data stores.
Wherein, can judge whether described data block belongs to high wear block in the following manner: judged by the program/erase counting how many times experienced described data block; Or, to described data block write given data, by judging the mensuration of data error rate; Or, after the experience known retention time, judged by the mensuration of the data error rate to described data block.
Wherein, carry out data by any one method following to the described data block be labeled to increase the weight of: carry out data by the method reading-rewrite to the described data block be labeled and increase the weight of; The method refreshed by data page is carried out data to the described data block be labeled and is increased the weight of; Carry out data by the method for word line program crosstalk to the described data block be labeled to increase the weight of; Carry out data by the method reading crosstalk to the described data block be labeled to increase the weight of.
Particularly, wherein, described NANDFlash storer is MLCNANDFlash storer, carry out data by the method reading-rewrite to the described data block be labeled to increase the weight of, specifically comprise: S10, all LSB (LeastSignificantBit, LSB, minimum effective bit) page data in the data block be labeled described in reading; S11, in LSB data page corresponding in the data block be labeled described in described LSB page data is written back to, wherein, when described LSB page data write-back, the floating gate charge bringing out described NANDFLASH storer injects to realize floating gate charge precompensation, reduce the susceptibility that between storage life, data are lost storage unit floating gate charge, thus realize high eroded area data pre-emphasis; And repeat step S10-S11, until reach the first preset times.
Wherein, described NANDFlash storer is SLC (Single-LevelCell, single level cell) NANDFlash storer, carry out data by the method reading-rewrite to the described data block be labeled to increase the weight of, specifically comprise: S12, all page datas in the data block be labeled described in reading; S13, in data page corresponding in the data block be labeled described in described page data is written back to, wherein, when described page data write-back, the floating gate charge bringing out described NANDFLASH storer injects to realize floating gate charge precompensation, reduce the susceptibility that between storage life, data are lost storage unit floating gate charge, thus realize high eroded area data pre-emphasis; And repeat step S12-S13, until reach the second preset times.
Particularly, wherein, described NANDFlash storer is MLCNANDFlash storer, the method refreshed by data page is carried out data to the described data block be labeled and is increased the weight of, wherein, for the NANDFlash storer of many level cell, specifically comprise: all LSB page datas in the data block be labeled described in reading; ECC (ErrorCorrectingCode, bug check and correction code) decoding is carried out to described LSB page data; If ECC successfully decoded, in LSB data page corresponding in the data block be labeled described in being written back to by described LSB page data, and repeat write back operations, until write-back number of times reaches the 3rd preset times.
Wherein, wherein, described NANDFlash storer is SLCNANDFlash storer, and the method refreshed by data page is carried out data to the described data block be labeled and increased the weight of, and specifically comprises: all page datas in the data block be labeled described in reading; ECC decoding is carried out to described page data; If ECC successfully decoded, in data page corresponding in the data block be labeled described in being written back to by described page data, and repeat write back operations, until write-back number of times reaches the 4th preset times.
Particularly, wherein, described NANDFlash storer is MLCNANDFlash storer, carry out data by the method for word line program crosstalk to the described data block be labeled to increase the weight of, wherein, for the NANDFlash storer of many level cell, specifically comprise: complete ' 1 ' data are write successively to all LSB data pages in the described data block be labeled, wherein, when described LSB page operations, the floating gate charge bringing out described NANDFLASH storer injects to realize floating gate charge precompensation, reduce the susceptibility that between storage life, data are lost storage unit floating gate charge, thus realize high eroded area data pre-emphasis, and, repeat write operation, until write number of times reaches the 5th preset times.
Wherein, wherein, described NANDFlash storer is SLCNANDFlash storer, carry out data by the method for word line program crosstalk to the described data block be labeled to increase the weight of, specifically comprise: complete ' 1 ' data are write successively to all data pages in the described data block be labeled, wherein, when described page operations, the floating gate charge bringing out described NANDFLASH storer injects to realize floating gate charge precompensation, reduce the susceptibility that between storage life, data are lost storage unit floating gate charge, thus realize high eroded area data pre-emphasis; And, repeat write operation, until write number of times reaches the 6th preset times.
Particularly, carry out data by the method reading crosstalk to the described data block be labeled to increase the weight of, specifically comprise: successively repeatedly read operation is carried out to all data pages in the described data block be labeled, wherein, when described read operation, the floating gate charge bringing out described NANDFLASH storer injects to realize floating gate charge precompensation, reduces the susceptibility that between storage life, data are lost storage unit floating gate charge, thus realizes high eroded area data pre-emphasis; And, repeat read operation, until reading times reaches the 7th preset times.
Accompanying drawing explanation
(a), (b), (c) in Fig. 1 is that in correlation technique, NANDFLASH storer carries out floating gate charge number change schematic diagram when data are preserved;
Fig. 2 be in correlation technique in NANDFlash storer data retention failures rate with storage unit program/erase number of times and storage time variation tendency curve synoptic diagram;
Fig. 3 is the process flow diagram of data substep emphasis method between NANDFlash storage system storage life according to an embodiment of the invention;
Fig. 4 is the process flow diagram of the marking phase according to a specific embodiment of the present invention;
Fig. 5 (a), (b), (c) and (d) carry out according to another specific embodiment of the present invention the contrast effect schematic diagram that data substep increases the weight of to process during data keep;
Fig. 6 is the process flow diagram increasing the weight of the stage according to the substep of another specific embodiment of the present invention;
Fig. 7 is that the method reading-rewrite that adopts for MLCNANDFlash storer according to an embodiment of the invention carries out to the data block be labeled the process flow diagram that data increase the weight of;
Fig. 8 is that the method reading-rewrite that adopts for SLCNANDFlash storer according to an embodiment of the invention carries out to the data block be labeled the process flow diagram that data increase the weight of;
(a) in Fig. 9, (b) and (c) be according to a specific embodiment of the present invention in MLCNANDFLASH storer utilization process at LSB page data by the voltage bias schematic diagram of device array during write-back;
(a) and (b) in Figure 10 is the schematic diagram of LSB and the MSB programmed algorithm of MLCNANDFLASH storer according to another specific embodiment of the present invention;
Figure 11 is that the method adopting data page to refresh for MLCNANDFlash storer according to an embodiment of the invention carries out to the data block be labeled the process flow diagram that data increase the weight of;
Figure 12 is that the method adopting data page to refresh for SLCNANDFlash storer according to still a further embodiment carries out to the data block be labeled the process flow diagram that data increase the weight of;
Figure 13 be according to still another embodiment of the invention to the data block be labeled, the process flow diagram that data increase the weight of is carried out by the method for word line program crosstalk for MLCNANDFlash storer;
In Figure 14, (a) and (b) are that the method for employing word line program crosstalk according to still another embodiment of the invention carries out the voltage bias of the device array that data increase the weight of to the data block be labeled and floating gate charge injects schematic diagram;
Figure 15 be according to still another embodiment of the invention to the data block be labeled, the process flow diagram that data increase the weight of is carried out by the method for word line program crosstalk for SLCNANDFlash storer;
Figure 16 is the maintenance error rate contrast schematic diagram carrying out device after data memory period substep increases the weight of according to the employing word line program crosstalk method of a specific embodiment of the present invention;
To be the method for reading crosstalk according to the employing of another specific embodiment of the present invention carry out to the data block be labeled the process flow diagram that data increase the weight of to Figure 17; And
Figure 18 (a) and (b) are the voltage bias and the charge injection schematic diagram that by the method for reading crosstalk, the data block be labeled are carried out to the device array that data increase the weight of according to still another embodiment of the invention.
Embodiment
Be described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Be exemplary below by the embodiment be described with reference to the drawings, be intended to for explaining the present invention, and can not limitation of the present invention be interpreted as.
Present inventor considers, because NANDFlash memory data keeps Problem-Error to result from the loss of floating gate charge between data retention period, so the problem keeping reliability significantly to degenerate for eroded area data high in NANDFlash storer particularly storer, the embodiment of the present invention proposes by progressively compensating storage unit floating gate charge between data retention period, thus realize increasing the weight of data substep between NANDFlash storage system storage life, significantly can reduce the data retention failures rate caused due to the accumulative of floating gate charge leak data between memory cell data storage life, thus effectively promote the reliability of NANDFlash memory stores data.
The NANDFlash storage system memory period data substep emphasis method proposed according to the embodiment of the present invention is described with reference to the accompanying drawings.
Put it briefly, between the NANDFlash storage system storage life of the embodiment of the present invention, data substep emphasis method can be divided into two separate phases, and namely marking phase and substep increase the weight of the stage.Fig. 3 is the process flow diagram of data substep emphasis method between NANDFlash storage system storage life according to an embodiment of the invention, and as shown in Figure 3, the method comprises:
S1, after NANDFlash storer write data, judges whether write data place data block is fully written, and judges whether data block belongs to high wear block.
It should be noted that, due in NANDFlash storer, erase operation is in units of block, so the storage unit in same has identical program/erase number of times, make the maintenance reliability of storage unit in same block close, so the method for the embodiment of the present invention is carried out in units of block.
Particularly, can judge whether data block belongs to high wear block in the following manner: judged by the program/erase counting how many times experienced data block, because the mass loss rates of the floating gate charge of NANDFlash storer associates with the program/erase number of times that its storage unit experiences, so by judging that the program/erase number of times that data block experiences can judge its abrasion condition, when the program/erase number of times of data block experience reaches preset times, namely judge that this data block is high wear block, wherein, program/erase counting how many times can be recorded in flash memory mapping layer (FTL, Flashtranslationlayer), especially in static wear balance module.
Or, to data block write given data, by judging the mensuration of data error rate, such as, if data error rate reaches preset value, then judge that this data block is high wear block.
Or, after the experience known retention time, judged by the mensuration of the data error rate to data block.
S2, if data block is fully written and belongs to high wear block, then marks data block, and records the Data Update time.
Because the data retention characteristics of high eroded area data block declines, increase the weight of so carry out substep between data retention period for such block, and for not high wear block, because itself data holding ability is comparatively strong, during can not carrying out data maintenance, substep increases the weight of.
In a word, after data write, judge data place block, if this block has been write full, and belonged to high eroded area, then record the Data Update time, and mark it, this stage is marking phase.
Fig. 4 is the process flow diagram of the marking phase according to a specific embodiment of the present invention, as shown in Figure 4, specifically comprises:
S100, carries out data access/write, and data write j, between trigger data storage life, data substep increases the weight of algorithm.
S110, enters marking phase algorithm.
S120, judges whether writing data blocks is fully written, if so, then enters step S130, otherwise enter step S160.
S130, the program/erase number of times record of this data block in queries static abrasion equilibrium module.
S140, judges whether this data block belongs to high wear block, if so, then enters step S150, otherwise enter step S160.
S150, marks this data block, and the data of this data block is increased the weight of the running time and be set to present system time.
S160, exits and increases the weight of algorithm.
S3, between data retention period, inquires about the enforcement time that the last data of the data block be labeled add retry, and judges whether this enforcement time reaches prefixed time interval.
S4, if this enforcement time reaches prefixed time interval, then carries out data to this data block be labeled and increases the weight of, and more new data increases the weight of to operate the enforcement time.
Particularly, between data retention period, when the system is idle, each tag block is processed.Obtaining the tag block last time carries out the enforcement time that data add retry, and homologous ray the time contrasts now, if not yet reach prefixed time interval interval time, then substep increases the weight of algorithm and exits.Otherwise carry out data to this tag block and add retry, more new data increases the weight of to operate the enforcement time, and this stage is substep and increases the weight of the stage simultaneously.
Between data retention period, substep is carried out to the data block of high eroded area and increase the weight of process, progressively can compensate the storage unit floating gate charge of NANDFlash storer, thus significantly reduce the data retention failures rate caused due to the accumulation of floating gate charge leakage quantity between memory cell data storage life, improve the reliability of NANDFlash memory stores data.
As shown in Figure 5, for a specific embodiment according to the present invention data keep during carry out data substep increase the weight of process contrast effect schematic diagram, wherein, Fig. 5 (a) for programming after floating gate charge quantity schematic diagram; The schematic diagram that Fig. 5 (b) causes floating gate charge quantity to reduce for charge leakage between data retention period; Fig. 5 (c) increases the weight of to process the schematic diagram progressively compensated floating gate charge loss for conscientious data substep between data retention period; Fig. 5 (d) is the schematic diagram making floating gate charge evapotranspiration control at reduced levels after increasing the weight of to process through data substep, reduces data error rate.
Fig. 6 is the process flow diagram increasing the weight of the stage according to the substep of a specific embodiment of the present invention, as shown in Figure 6, specifically comprises:
S200, between data retention period, data access, the data substep emphasis method between trigger data storage life when system idles.
S210, enters substep and increases the weight of algorithm.
S220, inquires about the enforcement time that the last data of this data block add retry.
S230, judges whether interval time reaches prefixed time interval, if so, then enters step S240, otherwise enter step S250.
S240, carries out data to this data block and increases the weight of, and more new data increases the weight of to operate the enforcement time.
S250, exits and increases the weight of algorithm.
Wherein, due to after block erasing, wherein data lost efficacy, and adding retry, removing so tackle existing mark without the need to proceeding substep during data keep.Besides, in execution block erase operation process, if this block is labeled, mark should be removed.
Can find out, data substep emphasis method between the NANDFlash storage system storage life of the embodiment of the present invention, by marking high wear block after data write, between data retention period, when be labeled data block add retry implement the time reach preset interval time time, substep is carried out to this mark data block and increases the weight of process, the data retention failures rate caused due to the accumulation of floating gate charge leak data during memory cell data keeps can be reduced, effectively promote the reliability that NANDFlash memory data stores.
Below between data retention period to be labeled data block carry out substep increase the weight of process process be further elaborated.
Particularly, data can be carried out by any one method following to the data block be labeled to increase the weight of: carry out data by the method reading-rewrite to the data block be labeled and increase the weight of; Or the method refreshed by data page is carried out data to the data block be labeled and is increased the weight of; Or, by the method for word line program crosstalk, data are carried out to the data block be labeled and increase the weight of; Or, by the method reading crosstalk, data are carried out to the data block be labeled and increase the weight of.In an embodiment above-mentioned several data emphasis method is described below.
Embodiment 1, adopts the method reading-rewrite to carry out data to the data block be labeled and increases the weight of.
Wherein, for MLCNANDFlash storer, as shown in Figure 7, data increase the weight of specifically to comprise:
S10, reads all LSB page datas in the data block be labeled, is about to need all LSB pages in data weight (Block) to read successively.
S11, LSB page data is written back in LSB data page corresponding in the data block be labeled, wherein, when LSB page data write-back, the floating gate charge bringing out NANDFLASH storer injects to realize floating gate charge precompensation, reduce the susceptibility that between storage life, data are lost storage unit floating gate charge, thus realize high eroded area data pre-emphasis.
Particularly, such as, when write-back, high level in the unit floating boom of NANDFlash storer is put on.In write-back process, during NANDFlash storer array have Different L SB data memory cell voltages be biased, the high level put in write-back process in unit floating boom can bring out floating gate charge and reinject, thus floating gate charge precompensation is carried out to storer height eroded area, realize high eroded area data and increase the weight of.Repeat step S10-S11, until reach the first preset times, such as, repeat N time, compensate to reach more significantly floating gate charge.
For SLCNANDFlash storer, as shown in Figure 8, carry out data to increase the weight of specifically to comprise:
S12, read all page datas in the data block be labeled, can find out, be different from MLCNANDFlash storer and only LSB data page operated, and SLCNANDFlash storer be there is no to the division of LSB/MSB data page, so in SLCNANDFlash storer, all data pages are operated.
S13, page data is written back in data page corresponding in the data block be labeled, wherein, when page data write-back, the floating gate charge bringing out NANDFLASH storer injects to realize floating gate charge precompensation, reduce the susceptibility that between storage life, data are lost storage unit floating gate charge, thus realize high eroded area data pre-emphasis.Such as, when write-back, put on high level in the unit floating boom of NANDFlash storer.Repeat step S12-S13, until reach the second preset times, such as, repeat N1 time, compensate to reach more significant floating gate charge.
In order to understand floating gate charge precompensation mechanism better, below NANDFLASH memory program algorithm is set forth.
Wherein, in MLCNANDFLASH storer, in each storage unit, comprise multiple bit information, multiple bit write storage unit stage by stage.
First, carry out LSB programming, the bit LSB of write, in this stage, according to concrete LSB data, storage unit threshold voltage is divided to two different windows.If LSB write 1, then storage unit is in programming and forbids state, if LSB write 0, then storage unit is in programmed state
After LSB programming, when carrying out the write of MSB (MostSignificantBit, the highest significant bit) data, storage unit threshold voltage is divided to four voltage windows by two voltage windows by storer further.
In programming process, the movement of storage unit threshold voltage injects realization by carrying out floating gate charge to storage unit, and floating gate charge injects a point multiple stage realization, and the quantity of electric charge that each stage injects is little, to prevent the movement of threshold voltage too fast.Each floating gate charge stage of injecting completes, and storer carries out the verification of storage unit threshold voltage, when threshold voltage is lower than predetermined reference voltage (Vref), proceeds next stage floating gate charge injection, otherwise, stop programmed algorithm.
For SLCNANDFLASH storer, owing to only there being a bit in storage unit, so only implement above described LSB programming phases.
The mechanism being realized floating gate charge precompensation by page write-back can be explained by Fig. 9.MLCNANDFLASH storer keeps Fault recovery to adopt LSB page write-back to realize.Particularly, be illustrated in figure 9 according to the present invention an embodiment in MLCNANDFLASH storer utilization process, the voltage bias schematic diagram of device array in LSB page data is by write-back process.
Shown in (a), (b) and (c) in Fig. 9, during the course, first algorithm reads storage unit LSB data in selected word line, and by write back data.If LSB data are 1, then LSB programmed algorithm is as shown in Figure 10 known, and this storage unit is in programming and forbids state.If LSB data are 0, this storage unit is in programmed state.The storage unit of state is forbidden for being in programme, its unit biasing state as shown in the figure, although its voltage applied is lower, significant floating gate charge can not be caused inject, but, because storage unit still exists the high pressure that representative value is 12V, so slight floating gate charge injects phenomenon unavoidably, thus realize storage unit floating gate charge precompensation.
And for being in the storage unit of programming state, although the voltage applied is higher, but because the LSB of storage unit is in 0, so the threshold voltage of storage unit has exceeded corresponding predetermined reference voltage (Vref), so algorithm stops after carrying out first stage floating gate charge injection, prevent crossing of floating gate charge from injecting, meanwhile, the floating gate charge injection that the first stage has implemented is successfully made floating gate charge precompensation.
So by LSB write back operations, all unit all obtain slight floating gate charge and inject thus achieve floating gate charge precompensation, avoid floating gate charge simultaneously and cross injection and cause data corruption.
Embodiment 2, the method refreshed by data page is carried out data to the data block be labeled and is increased the weight of.NANDFlash storer may produce error in data in ablation process, in order to anti-mistake here increases the weight of in process extended in data, first can obtain correct data to it by ECC decoding, and carry out write back data according to correct data, thus realize data and increase the weight of.
Wherein, for MLCNANDFlash storer, as shown in figure 11, the method refreshed by page is carried out data and is increased the weight of specifically to comprise:
S20, reads all LSB page datas in the data block be labeled.
S21, carries out ECC decoding to LSB page data.
S22, judges that whether ECC decoding is successful, if success, then enters step S23, otherwise enter step S25.
S23, is written back to LSB page data in LSB data page corresponding in the data block be labeled, and repeats write back operations, until write-back number of times reaches the 3rd preset times, such as, repeats N2 time, to reach more significant floating gate charge compensation effect.
S24, algorithm failure, loss of data.
For SLCNANDFlash storer, as shown in figure 12, the method refreshed by page is carried out data and is increased the weight of specifically to comprise:
S25, reads all page datas in the data block be labeled.
S26, carries out ECC decoding to page data.
S27, judges that whether ECC decoding is successful, if ECC successfully decoded, enters step S28, otherwise enter step S29.
S28, is written back to page data in data page corresponding in the data block be labeled, and repeats write back operations, until write-back number of times reaches the 4th preset times, such as, repeats N3 time, to reach more significantly floating gate charge compensation effect.
S29, algorithm failure, loss of data.
Embodiment 3, carries out data by the method for word line program crosstalk to the described data block be labeled and increases the weight of.
Wherein, for MLCNANDFlash storer, as shown in figure 13, word line program cross-talk data increases the weight of specifically to comprise:
S30, complete ' 1 ' data are write successively to all LSB data pages in the data block be labeled, for MLCNANDFlash storer, storage unit will be made to be in programming holddown to LSB data page write " 1 ", wherein, when LSB page operations, the floating gate charge bringing out NANDFLASH storer injects to realize floating gate charge precompensation.Such as, high level is imposed between the control gate of the storage unit of NANDFlash storer and raceway groove, its voltage bias is as shown in Figure 14 (a), the storage unit be in programming holddown can not produce significant floating gate charge and inject, but, high voltage between storage unit control gate and raceway groove will lure that slight floating gate charge injects phenomenon as shown in Figure 14 (b) into, and namely this phenomenon is called word line program crosstalk.Floating gate charge precompensation can be carried out to high eroded area by word line program crosstalk, reduce the susceptibility that between storage life, data are lost storage unit floating gate charge, realize high eroded area data and increase the weight of.In order to reach more significant floating gate charge compensation effect, above-mentioned write operation can be repeated, until write number of times reaches the 5th preset times, such as, repeating N4 time.
For SLCNANDFlash storer, as shown in figure 15, word line program cross-talk data increases the weight of specifically to comprise:
S31, complete ' 1 ' data are write successively to all data pages in the data block be labeled, wherein, when page operations, the floating gate charge bringing out NANDFLASH storer injects to realize floating gate charge precompensation, reduces the susceptibility that between storage life, data are lost storage unit floating gate charge, thus realizes high eroded area data pre-emphasis, such as, high level is imposed between the control gate of the storage unit of NANDFlash storer and raceway groove.Be different from MLCNANDFlash storer and only LSB data operated, in SLCNANDFlash storer, all data pages are operated.
Further, in order to reach more significant floating gate charge compensation effect, above-mentioned write operation can be repeated, until write number of times reaches the 6th preset times, such as, repeat N5 time.
As shown in figure 16, for the employing word line program crosstalk method of a specific embodiment according to the present invention carries out after data memory period substep increases the weight of, the maintenance error rate contrast schematic diagram of device, as shown in the figure, when choosing pre-emphasis degree N and being 8 times/3 months, through the holding time of 4 years, compared to the situation not adopting data substep to increase the weight of, its data error rate reduces by 66%, visible, increases the weight of effectively to reduce the data error rate between data retention period by substep.
Embodiment 4, carries out data by the method reading crosstalk to the data block be labeled and increases the weight of.
Particularly, as shown in figure 17, comprise: S40, successively read operation is carried out to all data pages in the data block be labeled, wherein, when read operation, the floating gate charge bringing out NANDFLASH storer injects to realize floating gate charge precompensation, reduce the susceptibility that between storage life, data are lost storage unit floating gate charge, thus realize high eroded area data pre-emphasis, such as, when carrying out read operation, high voltage is imposed between the control gate and raceway groove of the storage unit of NANDFlash storer, the voltage bias of device array is as shown in (a) in Figure 18, in read operation process, the high voltage put between storage unit control gate and raceway groove will lure that slight floating gate charge injects as shown in Figure 18 (b) into, this phenomenon is called reads crosstalk, floating gate charge precompensation can be carried out to high eroded area by reading crosstalk, thus realize adding retry to high eroded area data.
Further, in order to reach more significant floating gate charge compensation effect, above-mentioned read operation can be repeated, until reading times reaches the 7th preset times such as carry out N6 read operation.
It should be noted that, in above implementation procedure, operation multiplicity such as N, N1, N2, N3, N4, N5, N6 need optimised, cause data to cross a large amount of generations of misprogrammed to prevent the excessive injection of floating gate charge.Besides, for different block abrasion conditions, prefixed time interval and each implemented data substep increase the weight of intensity namely operate multiplicity can be different, such as, for the data block of serious wear, the time interval that implementation data substep increases the weight of can shorten, and each implemented data substep increases the weight of intensity and can suitably increase the weight of.In addition, when implementation data adds retry, the data substep implemented increase the weight of intensity can from before to increase the weight of intensity identical or different, after implementation data adds retry, the time interval of presetting can be identical or different from the time interval before, namely carry out data substep add time of retry can even distribution, also can uneven substep.
In the explanation of this instructions, describe and can be understood in process flow diagram or in this any process otherwise described or method, represent and comprise one or more for realizing the module of the code of the executable instruction of the step of specific logical function or process, fragment or part, and the scope of the preferred embodiment of the present invention comprises other realization, wherein can not according to order that is shown or that discuss, comprise according to involved function by the mode while of basic or by contrary order, carry out n-back test, this should understand by embodiments of the invention person of ordinary skill in the field.
In flow charts represent or in this logic otherwise described and/or step, such as, the sequencing list of the executable instruction for realizing logic function can be considered to, may be embodied in any computer-readable medium, for instruction execution system, device or equipment (as computer based system, comprise the system of processor or other can from instruction execution system, device or equipment instruction fetch and perform the system of instruction) use, or to use in conjunction with these instruction execution systems, device or equipment.With regard to this instructions, " computer-readable medium " can be anyly can to comprise, store, communicate, propagate or transmission procedure for instruction execution system, device or equipment or the device that uses in conjunction with these instruction execution systems, device or equipment.The example more specifically (non-exhaustive list) of computer-readable medium comprises following: the electrical connection section (electronic installation) with one or more wiring, portable computer diskette box (magnetic device), random access memory (RAM), ROM (read-only memory) (ROM), erasablely edit ROM (read-only memory) (EPROM or flash memory), fiber device, and portable optic disk ROM (read-only memory) (CDROM).In addition, computer-readable medium can be even paper or other suitable media that can print described program thereon, because can such as by carrying out optical scanning to paper or other media, then carry out editing, decipher or carry out process with other suitable methods if desired and electronically obtain described program, be then stored in computer memory.
Should be appreciated that each several part of the present invention can realize with hardware, software, firmware or their combination.In the above-described embodiment, multiple step or method can with to store in memory and the software performed by suitable instruction execution system or firmware realize.Such as, if realized with hardware, the same in another embodiment, can realize by any one in following technology well known in the art or their combination: the discrete logic with the logic gates for realizing logic function to data-signal, there is the special IC of suitable combinational logic gate circuit, programmable gate array (PGA), field programmable gate array (FPGA) etc.
Those skilled in the art are appreciated that realizing all or part of step that above-described embodiment method carries is that the hardware that can carry out instruction relevant by program completes, described program can be stored in a kind of computer-readable recording medium, this program perform time, step comprising embodiment of the method one or a combination set of.
In addition, term " first ", " second " only for describing object, and can not be interpreted as instruction or hint relative importance or imply the quantity indicating indicated technical characteristic.Thus, be limited with " first ", the feature of " second " can express or impliedly comprise at least one this feature.In describing the invention, the implication of " multiple " is at least two, such as two, three etc., unless otherwise expressly limited specifically.
In the description of this instructions, specific features, structure, material or feature that the description of reference term " embodiment ", " some embodiments ", " example ", " concrete example " or " some examples " etc. means to describe in conjunction with this embodiment or example are contained at least one embodiment of the present invention or example.In this manual, to the schematic representation of above-mentioned term not must for be identical embodiment or example.And the specific features of description, structure, material or feature can combine in one or more embodiment in office or example in an appropriate manner.In addition, when not conflicting, the feature of the different embodiment described in this instructions or example and different embodiment or example can carry out combining and combining by those skilled in the art.
Although illustrate and describe embodiments of the invention above, be understandable that, above-described embodiment is exemplary, can not be interpreted as limitation of the present invention, and those of ordinary skill in the art can change above-described embodiment within the scope of the invention, revises, replace and modification.
Claims (10)
1. a data substep emphasis method between NANDFlash storage system storage life, is characterized in that, comprise the following steps:
After NANDFlash storer write data, judge whether write data place data block is fully written, and judge whether described data block belongs to high wear block;
If described data block is fully written and belongs to high wear block, then described data block is marked, and record the Data Update time;
Between data retention period, inquire about the enforcement time that the last data of the data block be labeled add retry, and judge whether the described enforcement time reaches prefixed time interval; And
If the described enforcement time reaches described prefixed time interval, then data are carried out to the described data block be labeled and increase the weight of, and more new data increases the weight of to operate the enforcement time.
2. data substep emphasis method between NANDFlash storage system storage life as claimed in claim 1, is characterized in that, judge whether described data block belongs to high wear block in the following manner:
Judged by the program/erase counting how many times experienced described data block; Or
To described data block write given data, by judging the mensuration of data error rate; Or
After the experience known retention time, judged by the mensuration of the data error rate to described data block.
3. data substep emphasis method between NANDFlash storage system storage life as claimed in claim 2, is characterized in that, carry out data increase the weight of by any one method following to the described data block be labeled:
Carry out data by the method reading-rewrite to the described data block be labeled to increase the weight of;
The method refreshed by data page is carried out data to the described data block be labeled and is increased the weight of;
Carry out data by the method for word line program crosstalk to the described data block be labeled to increase the weight of;
Carry out data by the method reading crosstalk to the described data block be labeled to increase the weight of.
4. data substep emphasis method between NANDFlash storage system storage life as claimed in claim 3, it is characterized in that, wherein, described NANDFlash storer is MLCNANDFlash storer, carry out data by the method reading-rewrite to the described data block be labeled to increase the weight of, specifically comprise:
S10, all LSB page datas in the data block be labeled described in reading;
S11, in LSB data page corresponding in the data block be labeled described in being written back to by described LSB page data, wherein, when described LSB page data write-back, the floating gate charge bringing out described NANDFLASH storer injects to realize floating gate charge precompensation; And
Repeat step S10-S11, until reach the first preset times.
5. data substep emphasis method between NANDFlash storage system storage life as claimed in claim 3, it is characterized in that, wherein, described NANDFlash storer is SLCNANDFlash storer, carry out data by the method reading-rewrite to the described data block be labeled to increase the weight of, specifically comprise:
S12, all page datas in the data block be labeled described in reading;
S13, in data page corresponding in the data block be labeled described in being written back to by described page data, wherein, when page data write-back, the floating gate charge bringing out NANDFLASH storer injects to realize floating gate charge precompensation; And
Repeat step S12-S13, until reach the second preset times.
6. data substep emphasis method between NANDFlash storage system storage life as claimed in claim 3, it is characterized in that, wherein, described NANDFlash storer is MLCNANDFlash storer, the method refreshed by data page is carried out data to the described data block be labeled and is increased the weight of, and specifically comprises:
All LSB page datas in the data block be labeled described in reading;
ECC decoding is carried out to described LSB page data;
If ECC successfully decoded, in LSB data page corresponding in the data block be labeled described in being written back to by described LSB page data, and repeat write back operations, until write-back number of times reaches the 3rd preset times.
7. data substep emphasis method between NANDFlash storage system storage life as claimed in claim 3, it is characterized in that, wherein, described NANDFlash storer is SLCNANDFlash storer, the method refreshed by data page is carried out data to the described data block be labeled and is increased the weight of, and specifically comprises:
All page datas in the data block be labeled described in reading;
ECC decoding is carried out to described page data;
If ECC successfully decoded, in data page corresponding in the data block be labeled described in being written back to by described page data, and repeat write back operations, until write-back number of times reaches the 4th preset times.
8. data substep emphasis method between NANDFlash storage system storage life as claimed in claim 3, it is characterized in that, wherein, described NANDFlash storer is MLCNANDFlash storer, carry out data by the method for word line program crosstalk to the described data block be labeled to increase the weight of, specifically comprise:
Write complete ' 1 ' data successively to all LSB data pages in the described data block be labeled, wherein, when described LSB page operations, the floating gate charge bringing out described NANDFLASH storer injects to realize floating gate charge precompensation; And
Repeat write operation, until write number of times reaches the 5th preset times.
9. data substep emphasis method between NANDFlash storage system storage life as claimed in claim 3, it is characterized in that, wherein, described NANDFlash storer is SLCNANDFlash storer, carry out data by the method for word line program crosstalk to the described data block be labeled to increase the weight of, specifically comprise:
Write complete ' 1 ' data successively to all data pages in the described data block be labeled, wherein, when described page operations, the floating gate charge bringing out described NANDFLASH storer injects to realize floating gate charge precompensation; And
Repeat write operation, until write number of times reaches the 6th preset times.
10. data substep emphasis method between NANDFlash storage system storage life as claimed in claim 3, is characterized in that, carry out data and increase the weight of, specifically comprise by the method reading crosstalk to the described data block be labeled:
Carry out read operation successively to all data pages in the described data block be labeled, wherein, when described read operation, the floating gate charge bringing out described NANDFLASH storer injects to realize floating gate charge precompensation; And
Repeat read operation, until reading times reaches the 7th preset times.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510868174.4A CN105427886B (en) | 2015-12-01 | 2015-12-01 | Data substep emphasis method during NAND Flash storage system saves |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510868174.4A CN105427886B (en) | 2015-12-01 | 2015-12-01 | Data substep emphasis method during NAND Flash storage system saves |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105427886A true CN105427886A (en) | 2016-03-23 |
| CN105427886B CN105427886B (en) | 2019-10-29 |
Family
ID=55506037
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510868174.4A Active CN105427886B (en) | 2015-12-01 | 2015-12-01 | Data substep emphasis method during NAND Flash storage system saves |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105427886B (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107391300A (en) * | 2017-07-26 | 2017-11-24 | 湖南国科微电子股份有限公司 | A kind of method and system for improving flash data memory reliability |
| CN107480012A (en) * | 2017-08-28 | 2017-12-15 | 郑州云海信息技术有限公司 | The data reconstruction method and data recovery system of a kind of solid state hard disc |
| CN108630280A (en) * | 2017-03-16 | 2018-10-09 | 宇瞻科技股份有限公司 | The control method of data endurance is promoted on non-volatile storage |
| WO2019223175A1 (en) * | 2018-05-25 | 2019-11-28 | 山东大学 | Non-volatile memory-based data self-destruction method and system |
| WO2021162730A1 (en) | 2020-02-13 | 2021-08-19 | Sandisk Technologies Llc | Refresh operations for memory cells based on susceptibility to read errors |
| WO2023024383A1 (en) * | 2021-08-24 | 2023-03-02 | 苏州浪潮智能科技有限公司 | Error rate analysis method, system and apparatus for mlc chip |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140047160A1 (en) * | 2012-08-13 | 2014-02-13 | Phison Electronics Corp. | Data writing method, and memory controller and memory storage apparatus using the same |
| CN103631529A (en) * | 2012-08-21 | 2014-03-12 | 群联电子股份有限公司 | Data writing method, storage controller and storage storing device |
-
2015
- 2015-12-01 CN CN201510868174.4A patent/CN105427886B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140047160A1 (en) * | 2012-08-13 | 2014-02-13 | Phison Electronics Corp. | Data writing method, and memory controller and memory storage apparatus using the same |
| CN103631529A (en) * | 2012-08-21 | 2014-03-12 | 群联电子股份有限公司 | Data writing method, storage controller and storage storing device |
Non-Patent Citations (4)
| Title |
|---|
| CHENGEN YANG等: "Improving the reliability of MLC NAND Flash Memories through adaptive data refresh and error control coding", 《J SIGN PROCESS SYST(2014)》 * |
| MA HAOZHI等: "Data pre-emphasis based retention reliability enhance scheme for MLC NAND flash memories", 《2015 IEEE11TH INTERNATIONAL CONFERENCE ON ASIC》 * |
| SHUHEI TANAKAMARU等: "Error-Prediction LDPC and Error Recovery Schemes for highly reliable solid state drives(SSDs)", 《IEEE JOURNAL OF SOLID-STATE CIRCUITS》 * |
| 李广军等: "《微型计算机原理》", 31 August 2001 * |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108630280A (en) * | 2017-03-16 | 2018-10-09 | 宇瞻科技股份有限公司 | The control method of data endurance is promoted on non-volatile storage |
| CN107391300A (en) * | 2017-07-26 | 2017-11-24 | 湖南国科微电子股份有限公司 | A kind of method and system for improving flash data memory reliability |
| CN107391300B (en) * | 2017-07-26 | 2020-07-14 | 湖南国科微电子股份有限公司 | Method and system for improving data storage reliability of flash memory |
| CN107480012A (en) * | 2017-08-28 | 2017-12-15 | 郑州云海信息技术有限公司 | The data reconstruction method and data recovery system of a kind of solid state hard disc |
| WO2019223175A1 (en) * | 2018-05-25 | 2019-11-28 | 山东大学 | Non-volatile memory-based data self-destruction method and system |
| WO2021162730A1 (en) | 2020-02-13 | 2021-08-19 | Sandisk Technologies Llc | Refresh operations for memory cells based on susceptibility to read errors |
| WO2023024383A1 (en) * | 2021-08-24 | 2023-03-02 | 苏州浪潮智能科技有限公司 | Error rate analysis method, system and apparatus for mlc chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105427886B (en) | 2019-10-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105427886A (en) | Step-by-step data addition method for NAND Flash storage system during storage period | |
| US9377962B2 (en) | Determining bias information for offsetting operating variations in memory cells | |
| USRE47946E1 (en) | Method for determining the exhaustion level of semiconductor memory | |
| US9224456B2 (en) | Setting operating parameters for memory cells based on wordline address and cycle information | |
| US9208871B2 (en) | Implementing enhanced data read for multi-level cell (MLC) memory using threshold voltage-drift or resistance drift tolerant moving baseline memory data encoding | |
| US8792272B2 (en) | Implementing enhanced data partial-erase for multi-level cell (MLC) memory using threshold voltage-drift or resistance drift tolerant moving baseline memory data encoding | |
| CN110047546B (en) | Erase management in a memory system | |
| CN105405462A (en) | Method for preemphasizing data in high wear region of NAND Flash storage system | |
| US8332696B2 (en) | Defect management method for storage medium and system thereof | |
| KR100873825B1 (en) | Multibit Programming Device and Method of Nonvolatile Memory | |
| CN110347335B (en) | Solid state disk data storage method and device | |
| CN103853582A (en) | Refresh method for flash memory and flash memory controller | |
| CN106708754A (en) | Data storage device and data maintenance method thereof | |
| US8699266B2 (en) | Implementing enhanced data write for multi-level cell (MLC) memory using threshold voltage-drift or resistance drift tolerant moving baseline memory data encoding | |
| US10340025B2 (en) | Data-storage device and block-releasing method | |
| CN114063906B (en) | Management method and device for physical blocks in NAND flash memory and SSD (solid State disk) equipment | |
| US20200279610A1 (en) | Method for Retaining Data | |
| CN102789813A (en) | Method and device for controlling use of non-least significant bit page in storage device | |
| CN108255634B (en) | Data reading method and device | |
| CN107193485B (en) | Storage device, control unit thereof and data storage method for storage device | |
| CN105404473A (en) | Data retention error recovery method for NAND FLASH memory | |
| JP2012009112A (en) | Nonvolatile semiconductor memory device | |
| TWI692691B (en) | Memory control device and memory control method | |
| US20130286731A1 (en) | Memory device, memory control device, and memory control method | |
| TWI706251B (en) | Data preservation method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |