CN108255634B - Data reading method and device - Google Patents
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- CN108255634B CN108255634B CN201611239752.9A CN201611239752A CN108255634B CN 108255634 B CN108255634 B CN 108255634B CN 201611239752 A CN201611239752 A CN 201611239752A CN 108255634 B CN108255634 B CN 108255634B
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- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
Abstract
the application discloses a data reading method and a device, which are used for solving the problem that the reading performance of a flash memory is affected because the existing L DPC error correction mechanism needs longer reading time delay and decoding time delay.
Description
Technical Field
The present application relates to the field of storage technologies, and in particular, to a data reading method and apparatus.
Background
Due to the advantages of good random access performance, low density, low power consumption and the like, the flash memory storage system becomes an important storage medium and is widely applied to embedded systems, portable notebooks, data centers and other devices.
the memory Cell represents data by storing a certain amount of charge, and taking a Multi-level Cell (mlc) storing 2 bits per Cell as an example, the memory Cell has 4 voltage states, and when there is no error in flash data, the four voltage states are separated from each other and do not intersect, as shown in fig. 1, however, under the influence of storage time, program disturbance, etc., the voltage of the memory Cell may change, and the voltage state shifts to an adjacent state, as shown in fig. 2, thereby causing a data error and deteriorating the reliability of the flash memory, and as the flash memory technology develops, particularly as the number of bits per Cell increases, such as the latest 6-bit technology, and the size of the Cell decreases, such as the latest 10nm technology, the problem of deteriorating the reliability of the flash memory becomes more and more obvious.
therefore, to solve the problem of flash memory reliability, the currently widely adopted solution is to use a low-Density Parity-Check (L DPC) error correction mechanism, which has a strong error correction capability and can achieve high error rate error correction, specifically, the L DPC decoding is implemented by a belief propagation algorithm and is divided into hard decision decoding and soft decision decoding, the cell distribution shown in fig. 1 can employ hard decision decoding, each two adjacent voltage states are distinguished by using one reference voltage, the voltage of each cell is compared with three reference voltages respectively, the voltage state of each cell is determined, and voltage state information of each cell is obtained, the cell distribution shown in fig. 2 can employ soft decision decoding, each two adjacent voltage states are distinguished by using three reference voltages, the region between two adjacent voltage states is divided into sub-regions of a higher degree, the voltage and the voltage state of each cell are determined by comparing with nine reference voltages, the state information of each cell is determined, it is known that the hard decision decoding efficiency is high, the required reading time is longer, but the fine-grain decoding time of the read error data can only be read when the adjacent decoding error decoding time is longer, and the error rate of the adjacent cells is higher, and the read error decoding efficiency is higher.
as shown in fig. 3, the voltage state distribution of the memory cells in the flash memory may be left-biased or right-biased, if the reference voltage can be set according to the offset condition of the voltage state, the reference voltage at this time is optimal, the error rate of the read data is reduced, and the decoding efficiency is improved, however, the actual offset condition of the voltage state cannot be determined at the time of data reading, and therefore the optimal reference voltage cannot be directly determined.
firstly, the number of memory elements in each voltage state needs to be recorded for the memory elements on each word line (W L), and the recording cost is high.
Disclosure of Invention
an object of the embodiments of the present application is to provide a data reading method and apparatus, so as to solve the problem that the read performance of a flash memory is affected because a conventional L DPC error correction mechanism requires a long read delay and a long decoding delay.
The purpose of the embodiment of the application is realized by the following technical scheme:
In a first aspect, a data reading method includes:
When the flash memory controller receives a reading instruction, loading a preset reference voltage on a page where data to be read are located, and acquiring first voltage state information of a storage element in the page where the data to be read are located; the flash memory controller decodes the data to be read according to the first voltage state information, and judges whether the program-erase frequency of the block to which the page of the data to be read belongs is smaller than a preset threshold value when the decoding fails, wherein the two specific conditions are as follows:
In the first case: when the programming erasing times are smaller than a preset threshold value, continuously loading a first left shift reference voltage on a page where the data to be read are located, and decoding the data to be read according to second voltage state information of a storage element in the page where the data to be read are located, wherein the first left shift reference voltage is smaller than the preset reference voltage;
In the second case: and when the programming and erasing times are larger than or equal to a preset threshold value, continuously loading a first right shift reference voltage on a page where the data to be read are located, and decoding the data to be read according to second voltage state information of a storage element in the page where the data to be read are located, wherein the first right shift reference voltage is larger than the preset reference voltage.
therefore, according to the main error type of the flash memory, namely, whether the error is a left bias error or a right bias error, when the left bias error is a main error, more left shift reference voltages are arranged on the left side of the preset reference voltage, and more right shift reference voltages are arranged on the right side, so that the redundant reference voltages on one side with lower error rate are reduced, and the L DPC decoding performance is improved.
It should be understood that the data to be read is stored in a plurality of pages, in the embodiment of the present application, only one page where the data to be read is located is taken as an example for description, and the processing methods of the pages where other data to be read are located are the same.
In a possible implementation manner, after the second voltage state information of the storage element in the page where the data to be read is obtained according to the first left shift reference voltage and the preset reference voltage and the data to be read is decoded, the method includes:
When the flash memory controller determines that decoding fails, a second left shift reference voltage is continuously loaded on a page where data to be read is located, and third voltage state information of a storage element in the page where the data to be read is obtained according to the first left shift reference voltage, the second left shift reference voltage and a preset reference voltage to decode the data to be read, wherein the second left shift reference voltage is smaller than the first left shift reference voltage;
Further, when the decoding fails again, the third left-shift reference voltage can be selected to be continuously loaded, or the first right-shift reference voltage can be loaded to attempt decoding.
After the second voltage state information of the memory cell in the data to be read is acquired according to the first right shift reference voltage and the preset reference voltage and decoded, the method comprises the following steps:
And when the flash memory controller determines that the decoding fails, continuously loading a second right shift reference voltage on a page where the data to be read is located, and decoding the data to be read according to the third voltage state information of the storage element in the data to be read, which is obtained according to the first right shift reference voltage, the second right shift reference voltage and a preset reference voltage, wherein the second right shift reference voltage is greater than the first right shift reference voltage.
Further, when the decoding fails again, the third right-shift reference voltage can be selected to be continuously loaded, or the first left-shift reference voltage can be loaded to attempt decoding.
In a possible implementation manner, an interval between the preset reference voltage and the first left shift reference voltage is equal to an interval between the first left shift reference voltage and the second left shift reference voltage;
The interval between the preset reference voltage and the first right shift reference voltage is equal to the interval between the first right shift reference voltage and the second right shift reference voltage.
The intervals here may also be chosen to be unequal.
It should be noted that the predetermined reference voltage, the first left shift reference voltage, the second left shift reference voltage, the third left shift reference voltage, the first right shift reference voltage, the second right shift reference voltage, and the third right shift reference voltage mentioned in the embodiments of the present application are all predetermined and are configured in the flash memory controller in advance.
in a possible implementation manner, the storage element in the page where the data to be read is located is a multi-level storage element mlc or a three-level storage element tlc.
In one possible implementation, after the flash memory controller receives the read command, the method includes:
And the flash memory controller determines the page of the data to be read according to the address of the page of the data to be read carried in the reading instruction.
In a second aspect, a data reading apparatus includes:
The device comprises an acquisition unit, a storage unit and a control unit, wherein the acquisition unit is used for loading a preset reference voltage on a page where data to be read is located when a reading instruction is received, and acquiring first voltage state information of a storage element in the page where the data to be read is located;
The first processing unit is used for decoding the data to be read according to the first voltage state information, and judging whether the programming and erasing times of a block to which a page where the data to be read belongs are smaller than a preset threshold value or not when the decoding fails;
When the programming and erasing times are smaller than the preset threshold value, continuously loading a first left shift reference voltage on a page where the data to be read are located, and acquiring second voltage state information of a memory cell in the page where the data to be read are located according to the first left shift reference voltage and the preset reference voltage to decode the data to be read, wherein the first left shift reference voltage is smaller than the preset reference voltage;
And when the programming and erasing times are larger than or equal to the preset threshold value, continuously loading a first right shift reference voltage on a page where the data to be read are located, and acquiring second voltage state information of a storage element in the page where the data to be read are located according to the first right shift reference voltage and the preset reference voltage to decode the data to be read, wherein the first right shift reference voltage is larger than the preset reference voltage.
In one possible implementation, the apparatus further includes:
The second processing unit is used for continuously loading a second left shift reference voltage on a page where the data to be read is located after the data to be read is decoded according to the first left shift reference voltage and the preset reference voltage and when the decoding fails, obtaining third voltage state information of a storage element in the page where the data to be read is located according to the first left shift reference voltage, the second left shift reference voltage and the preset reference voltage and decoding the data to be read, wherein the second left shift reference voltage is smaller than the first left shift reference voltage;
The second processing unit is further configured to, after the second voltage state information of the storage element in the data to be read is obtained according to the first right shift reference voltage and the preset reference voltage to decode the data to be read, when it is determined that decoding fails, continue to load a second right shift reference voltage on a page where the data to be read is located, and obtain third voltage state information of the storage element in the data to be read according to the first right shift reference voltage, the second right shift reference voltage and the preset reference voltage to decode the data to be read, where the second right shift reference voltage is greater than the first right shift reference voltage.
In a possible implementation manner, an interval between the preset reference voltage and the first left shift reference voltage is equal to an interval between the first left shift reference voltage and the second left shift reference voltage;
The interval between the preset reference voltage and the first right shift reference voltage is equal to the interval between the first right shift reference voltage and the second right shift reference voltage.
in a possible implementation manner, the storage element in the page where the data to be read is located is a multi-level storage element mlc or a three-level storage element tlc.
In one possible implementation, the apparatus further includes:
And the instruction analysis unit is used for determining the page of the data to be read according to the address of the page of the data to be read carried in the reading instruction after the flash memory controller receives the reading instruction.
In a third aspect, an embodiment of the present application provides a flash memory storage system including a host interface, a flash memory controller, a flash memory interface, and a flash memory.
The host interface is configured to receive an I/O request, and the flash memory controller is configured to write or read data in the flash memory through the flash memory interface according to the I/O request.
furthermore, 3 main modules in a flash memory controller of the flash memory storage system complete the coding and decoding process of the L DPC, wherein the coding and decoding process comprises an L DPC coding module, a reference voltage management module and an L DPC decoding module.
Drawings
Fig. 1 is a schematic diagram of hard decision decoding in the background art of the present application;
FIG. 2 is a diagram illustrating soft-decision decoding in the background art of the present application;
FIG. 3 is a diagram illustrating a flash error in the background art of the present application;
FIG. 4 is a diagram illustrating the number of memory cells corresponding to each voltage state counted during data writing in the background art of the present application;
FIG. 5 is a schematic diagram illustrating the determination of an optimal reference voltage in the background of the present application;
FIG. 6 is a diagram illustrating a structure of a flash block according to an embodiment of the present invention;
FIG. 7 is a diagram illustrating reference voltages required to be loaded for a read operation in an embodiment of the present application;
FIG. 8 is a schematic diagram illustrating an increase in reference voltage for a read operation in an embodiment of the present application;
FIG. 9 is a flowchart illustrating an overview of a data reading method according to an embodiment of the present application;
FIG. 10 is a schematic diagram of loading a reference voltage in an embodiment of the present application;
FIG. 11 is a schematic structural diagram of a flash memory system according to an embodiment of the present application;
Fig. 12 is a schematic structural diagram of a data reading apparatus in an embodiment of the present application.
Detailed Description
Embodiments of the present application are described below with reference to the accompanying drawings.
FIG. 6 is an organization structure of a flash block, and is composed of a plurality of memory cells, a row of memory cells is composed of W L, a column of memory cells is composed of a Bit line (B L), a W L0 contains one or more pages corresponding to the number of information bits stored by each memory Cell, for example, a Single-L1 evel Cell (S L C) stores 1-Bit information per memory Cell, one W L represents one page, and M L C stores 2-Bit information per memory Cell, and each W L contains two pages, respectively, Most Significant Bit (MSB) and least Significant Bit (L east Bit, L SB). the reading process of L SB is described below by taking M L C as an example.
As shown in FIG. 6, when it is required to read the data at W L, a voltage reference V is applied to W L to be read ref(reference voltage) wherein, when reading L SB, V refGet V bOn reading MSB, V refGet V first aGet V again cand the other W L applied voltage pass voltage V passthe corresponding sense amplifier (sense amplifier) under each B L can sense the voltage information of the cell read on this strip B L if the voltage in the cell is less than V refthen it is at B L with no current to the sense amplifier, otherwise if the voltage in the cell is greater than V refthen B L has current flowing to the sense amplifier, so that when one W L is read, the voltage V applied to the other W L passhigher than all cells to ensure that W L to be read is not disturbed, i.e., the voltage of a cell on W L that is not read is not higher than V passassume for example in FIG. 6 that L SB of W L is now to be read, setting V refA voltage of V b2.5V, and the other W L applied voltage is V passsince the 1 st, 2 nd and 4 th cell voltages on read W L are all higher than V refAnd the 3 rd cell voltage is lower than V refthen the voltage information of the memory cell in L SB is 0010.
Therefore, when a read operation is performed, the time required to determine the voltage state at which the cell voltage is located is proportional to the number of reference voltages to be applied. Taking FIG. 7 as an example, when reading MSB, V refGet V first aGet V again ctherefore, reading the MSB requires twice as much time as L SB.
taking read L SB as an example, if decoding succeeds, the read operation is completed, and if decoding fails, the read reference voltage needs to be added to the flash memory bLeft plus reference voltage V b1read L SB. now two reference voltages divide the cell voltage into 3 regions, 11,10 and 00 below the figure (at least 2 bits are needed to represent 3 regions). by reference voltage comparison, if the cell voltage is less than V b1The cell reads 11 if the cell voltage is greater than V b1Less than V bThe cell reads 10 if the cell voltage is greater than V bthe information read by the bin is 00. at this time, it is still 1 page (i.e. 1bit per bin) of data, but the information transmitted to the flash memory controller is twice as many as 1 page, i.e. 2 bits per bin, and the controller decodes the data according to the log-likelihood-ratio (LL R) value corresponding to the 2bit information, wherein,
the LL R value of the i-th bit (bi) is the probability that the bit is 0 (P (bi ═ 0)) divided by the probability that the bit is 1 (P (bi ═ 1)), and then logarithms are taken, where P (bi ═ 0) + P (bi ═ 1) ═ 1.
The read time becomes longer after increasing the reference voltage. Further, if the decoding is successful at this time, the read operation is completed, and if the decoding fails, the reference voltage needs to be increased continuously for the read operation. Therefore, the voltage of the memory cell is divided into more areas and represented by more bit information, and meanwhile, the decoding capability is stronger, and the decoding success probability is higher.
Therefore, the read latency occupied in the embodiment of the present application includes two parts: one part is the time for comparing with the reference voltage for multiple times, for example, 9 reference voltages are needed for comparison in fig. 2, and the reading time delay is longer compared with 3 reference voltages in fig. 1; the other part is that the increased sub-areas require more bits of information to distinguish and represent, for example, fig. 2 requires 4 bits to represent information, compared to 2 bits in fig. 1, so that the time for transferring the information from the flash memory chip to the flash memory controller is longer.
Errors in flash memory are largely classified into two categories: left shift error and right shift error. The left shift error is mainly caused by leakage generated by the flash memory along with the increase of the storage time, the charge in the flash memory is reduced, and the voltage state is shifted to the left. The main sources of the right shift error include read disturb, program disturb, etc. when performing read/write operations of the flash memory, it is easy to make the adjacent memory cells or other memory cells in a block additionally charge charges, and the voltage state is shifted to the right. The common denominator of these two types of errors is that they both increase with increasing Program/Erase cycles (P/E cycles), with smaller P/E cycles having smaller left shift errors and larger right shift errors, and larger P/E cycles having larger left shift errors and larger right shift errors. However, since the retention time is the main cause of flash memory errors, when the P/E cycle is small, the right shift error is small, if the flash memory error occurs, the left shift error is mainly the left shift error, and when the P/E cycle is large, if the flash memory error occurs, the right shift error is certainly included, and there may be a left shift error.
Based on the above analysis, referring to fig. 9, an embodiment of the present application provides a data reading method, including:
Step 900: when the flash memory controller receives a reading instruction, a preset reference voltage is loaded on a page where data to be read are located, and first voltage state information of a storage element in the page where the data to be read are located is obtained.
It should be understood that the data to be read is stored in a plurality of pages, in the embodiment of the present application, only one page where the data to be read is located is taken as an example for description, and the processing methods of the pages where other data to be read are located are the same.
it should be understood that the memory cell in the page where the data to be read is M L C or a tertiary memory cell (Trinary-L evencell, T L C).
for example, referring to fig. 9, when the memory cell is mlc, Vref is Vb when L SB is read, and Vref is Va and Vc when MSB is read, that is, the number of preset reference voltages is different for different pages.
Specifically, after the flash memory controller receives the read instruction, the flash memory controller determines the page where the data to be read is located according to the address of the page where the data to be read is located, which is carried in the read instruction.
Therefore, in step 900, the flash memory controller uses the obtained voltage status information of each memory cell in the page where the data to be read is located as the first voltage status information by loading the preset reference voltage.
Step 910: and the flash memory controller decodes the data to be read according to the first voltage state information, and judges whether the programming and erasing times of the block to which the page of the data to be read belongs are smaller than a preset threshold value when the decoding fails.
Specifically, the preset threshold value can be obtained by simulation calculation of an existing algorithm.
In step 910, the flash memory controller decodes the data to be read according to the first voltage status information, and the decoding method provided in the prior art is adopted.
When the flash memory controller deletes the determined decoding failure, i.e. the hard decision decoding failure, the reference voltage needs to be increased, and the decoding is attempted by adopting the soft decision decoding method. Compared with the prior art that the reference voltage is added on the left side or the right side of the current reference voltage, the P/E cycle is compared with the preset threshold value to determine which direction the reference voltage is added to first, so that the reading time delay and the decoding time delay are shortened, and the decoding is successful as soon as possible.
Step 920 a: when the program erasing times are smaller than the preset threshold value, the flash memory controller continuously loads a first left shift reference voltage on a page where the data to be read are located, and second voltage state information of a storage element in the page where the data to be read are obtained according to the first left shift reference voltage and the preset reference voltage to decode the data to be read, wherein the first left shift reference voltage is smaller than the preset reference voltage.
Step 920 b: and when the programming and erasing times are larger than or equal to a preset threshold value, continuously loading a first right shift reference voltage on a page where the data to be read are located, and decoding the data to be read according to second voltage state information of a storage element in the page where the data to be read are located, wherein the first right shift reference voltage is larger than the preset reference voltage.
It should be appreciated that the P/E cycle is recorded in the flash memory controller, and the flash memory implements wear leveling to record this information, so no additional overhead is required to record, and the reference voltage is set by determining the size of the P/E cycle compared to a preset threshold.
1) Assuming that the preset threshold is T PEAt P/E cycle < T PEAnd then, on the basis of accelerating the preset reference voltage, continuously loading the first left shift reference voltage to obtain more voltage state information aiming at the memory cell as second voltage state information.
Specifically, as shown in (a) of fig. 10 and (c) of fig. 10, when the right shift error in the flash memory is small, the reference voltage is preferentially increased to the left of the hard decoding reference voltage after the decoding failure. Because there are two cases here: a. the left shift error is small. The error rate of the flash data is small and the decoding can be correctly performed by only increasing a small reference voltage. b. The left shift error is large. In this case, the reference voltage is preferentially increased on the left side, so that more reference voltages are available on the left side, and the decoding efficiency is improved.
2) Assuming that the preset threshold is T PEWhen P/E cycle is not less than T PEAnd continuously loading the first right shift reference voltage on the basis of accelerating the preset reference voltage to obtain more voltage state information aiming at the memory cell as second voltage state information.
specifically, as shown in fig. 10 (b) and 10 (d), when the right shift error in the flash memory is large, the reference voltage is preferentially increased on the right side of the hard decoding reference voltage after the decoding failure, and there are two cases that a, the left shift error is small, and less reference voltage is needed on the left side.
Further, after the second voltage state information of the storage element in the page where the data to be read is located is obtained according to the first left shift reference voltage and the preset reference voltage, and the data to be read is decoded, when the flash memory controller determines that the decoding fails, the second left shift reference voltage is continuously loaded on the page where the data to be read is located, and the third voltage state information of the storage element in the page where the data to be read is obtained according to the first left shift reference voltage, the second left shift reference voltage and the preset reference voltage, wherein the second left shift reference voltage is smaller than the first left shift reference voltage.
The interval between the preset reference voltage and the first left shift reference voltage is equal to the interval between the first left shift reference voltage and the second left shift reference voltage. The interval between the preset reference voltage and the first left shift reference voltage is equal to the interval between the first left shift reference voltage and the second left shift reference voltage. The intervals here may also be chosen to be unequal.
Further, when the decoding fails again, the third left-shift reference voltage can be selected to be continuously loaded, or the first right-shift reference voltage can be loaded to attempt decoding.
Or after the second voltage state information of the storage element in the data to be read is acquired according to the first right shift reference voltage and the preset reference voltage, and the data to be read is decoded by the flash memory controller when the decoding fails, continuously loading the second right shift reference voltage on the page where the data to be read is located, and acquiring the third voltage state information of the storage element in the data to be read according to the first right shift reference voltage, the second right shift reference voltage and the preset reference voltage, wherein the second right shift reference voltage is greater than the first right shift reference voltage.
The interval between the preset reference voltage and the first right shift reference voltage is equal to the interval between the first right shift reference voltage and the second right shift reference voltage.
Further, when the decoding fails again, the third right-shift reference voltage can be selected to be continuously loaded, or the first left-shift reference voltage can be loaded to attempt decoding.
It should be noted that the predetermined reference voltage, the first left shift reference voltage, the second left shift reference voltage, the third left shift reference voltage, the first right shift reference voltage, the second right shift reference voltage, and the third right shift reference voltage mentioned in the embodiments of the present application are all predetermined and are configured in the flash memory controller in advance. The method provided by the embodiment of the application is only used for determining whether the reference voltage is added to the left side or the right side of the reference voltage after the decoding fails.
Table 1 shows a relationship between the number of times of decryption and the reference voltage configuration.
TABLE 1
Wherein N is k lAnd N k rThe number of reference voltages set to the left and right of the hard decision reference voltage between states k and k +1, respectively. Since the number of reference voltages between each two states is at most 7 (the maximum number supported in current flash memory), then N is k lAnd N k rThe maximum value is 3.
As shown in fig. 11, an embodiment of the present application provides a flash memory storage system including a host interface, a flash memory controller, a flash memory interface, and a flash memory.
The host interface is configured to receive an I/O request, the flash memory controller writes or reads data in the flash memory through the flash memory interface according to the I/O request, and the flash memory controller is configured to execute the method shown in fig. 9.
furthermore, 3 main modules in a flash memory controller of the flash memory storage system complete the coding and decoding process of the L DPC, wherein the coding and decoding process comprises an L DPC coding module, a reference voltage management module and an L DPC decoding module.
Referring to fig. 12, an embodiment of the present application provides a data reading apparatus 1200, including:
An obtaining unit 1210, configured to, when receiving a read instruction, load a preset reference voltage on a page where data to be read is located, and obtain first voltage state information of a storage element in the page where the data to be read is located;
The first processing unit 1220 is configured to decode the data to be read according to the first voltage state information, and determine whether the number of times of program erasing of a block to which a page where the data to be read belongs is smaller than a preset threshold value when the decoding fails;
When the programming and erasing times are smaller than the preset threshold value, continuously loading a first left shift reference voltage on a page where the data to be read are located, and acquiring second voltage state information of a memory cell in the page where the data to be read are located according to the first left shift reference voltage and the preset reference voltage to decode the data to be read, wherein the first left shift reference voltage is smaller than the preset reference voltage;
And when the programming and erasing times are larger than or equal to the preset threshold value, continuously loading a first right shift reference voltage on a page where the data to be read are located, and acquiring second voltage state information of a storage element in the page where the data to be read are located according to the first right shift reference voltage and the preset reference voltage to decode the data to be read, wherein the first right shift reference voltage is larger than the preset reference voltage.
In one possible implementation, the apparatus further includes:
The second processing unit 1230 is configured to, after the second voltage state information of the storage element in the page where the data to be read is obtained according to the first left shift reference voltage and the preset reference voltage and the data to be read is decoded, determine that decoding fails, continue to load a second left shift reference voltage on the page where the data to be read is located, and obtain third voltage state information of the storage element in the page where the data to be read is decoded according to the first left shift reference voltage, the second left shift reference voltage and the preset reference voltage, where the second left shift reference voltage is smaller than the first left shift reference voltage;
The second processing unit 1230 is further configured to, after the second voltage state information of the memory cell in the data to be read is obtained according to the first right shift reference voltage and the preset reference voltage to decode the data to be read, when it is determined that decoding fails, continue to load a second right shift reference voltage on a page where the data to be read is located, and obtain third voltage state information of the memory cell in the data to be read according to the first right shift reference voltage, the second right shift reference voltage and the preset reference voltage to decode the data to be read, where the second right shift reference voltage is greater than the first right shift reference voltage.
In a possible implementation manner, an interval between the preset reference voltage and the first left shift reference voltage is equal to an interval between the first left shift reference voltage and the second left shift reference voltage;
The interval between the preset reference voltage and the first right shift reference voltage is equal to the interval between the first right shift reference voltage and the second right shift reference voltage.
in a possible implementation manner, the storage element in the page where the data to be read is located is a multi-level storage element mlc or a three-level storage element tlc.
In one possible implementation, the apparatus further includes:
The instruction analysis unit 1240 is configured to determine, after the flash memory controller receives the read instruction, a page where the data to be read is located according to an address of the page where the data to be read is located, where the address is carried in the read instruction.
based on the above error characteristics of flash memory, the present application provides a data reading method and apparatus, as an L DPC optimization method, in the existing scheme, a reference voltage is set in the middle of an original adjacent state, when the reference voltage cannot correctly decode data, reference voltages are added on both sides of the original hard decoding reference voltage, and data is re-read and decoded.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While embodiments of the present application have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including the embodiments of the application and all alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various changes and modifications may be made in the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if such modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to encompass such modifications and variations.
Claims (10)
1. A data reading method, comprising:
When the flash memory controller receives a reading instruction, loading a preset reference voltage on a page where data to be read are located, and acquiring first voltage state information of a storage element in the page where the data to be read are located;
The flash memory controller decodes the data to be read according to the first voltage state information, and judges whether the programming and erasing times of a block to which a page where the data to be read belongs are smaller than a preset threshold value or not when the decoding fails;
When the programming and erasing times are smaller than the preset threshold value, continuously loading a first left shift reference voltage on a page where the data to be read are located, and acquiring second voltage state information of a memory cell in the page where the data to be read are located according to the first left shift reference voltage and the preset reference voltage to decode the data to be read, wherein the first left shift reference voltage is smaller than the preset reference voltage;
And when the programming and erasing times are larger than or equal to the preset threshold value, continuously loading a first right shift reference voltage on a page where the data to be read are located, and acquiring second voltage state information of a storage element in the page where the data to be read are located according to the first right shift reference voltage and the preset reference voltage to decode the data to be read, wherein the first right shift reference voltage is larger than the preset reference voltage.
2. The method as claimed in claim 1, wherein after the decoding of the data to be read according to the second voltage status information of the memory cell in the page where the data to be read is obtained from the first left-shift reference voltage and the preset reference voltage, the method comprises:
When the flash memory controller determines that decoding fails, a second left shift reference voltage is continuously loaded on a page where the data to be read is located, and third voltage state information of a storage element in the page where the data to be read is located is obtained according to the first left shift reference voltage, the second left shift reference voltage and the preset reference voltage to decode the data to be read, wherein the second left shift reference voltage is smaller than the first left shift reference voltage;
After the second voltage state information of the memory cell in the data to be read is obtained according to the first right shift reference voltage and the preset reference voltage to decode the data to be read, the method comprises the following steps:
And when the flash memory controller determines that the decoding fails, continuously loading a second right shift reference voltage on a page where the data to be read is located, and decoding the data to be read according to third voltage state information of a storage element in the data to be read, which is obtained according to the first right shift reference voltage, the second right shift reference voltage and the preset reference voltage, wherein the second right shift reference voltage is greater than the first right shift reference voltage.
3. The method of claim 2, wherein the preset reference voltage is spaced apart from the first left shift reference voltage by an interval equal to the first left shift reference voltage and the second left shift reference voltage;
The interval between the preset reference voltage and the first right shift reference voltage is equal to the interval between the first right shift reference voltage and the second right shift reference voltage.
4. the method of any of claims 1-3, wherein the memory cells in the page from which the data is to be read are multi-level memory cells MLC or tri-level memory cells TLC.
5. The method of any of claims 1-3, wherein after the flash memory controller receives the read command, comprising:
And the flash memory controller determines the page of the data to be read according to the address of the page of the data to be read carried in the reading instruction.
6. A data reading apparatus, comprising:
The device comprises an acquisition unit, a storage unit and a control unit, wherein the acquisition unit is used for loading a preset reference voltage on a page where data to be read is located when a reading instruction is received, and acquiring first voltage state information of a storage element in the page where the data to be read is located;
The first processing unit is used for decoding the data to be read according to the first voltage state information, and judging whether the programming and erasing times of a block to which a page where the data to be read belongs are smaller than a preset threshold value or not when the decoding fails;
When the programming and erasing times are smaller than the preset threshold value, continuously loading a first left shift reference voltage on a page where the data to be read are located, and acquiring second voltage state information of a memory cell in the page where the data to be read are located according to the first left shift reference voltage and the preset reference voltage to decode the data to be read, wherein the first left shift reference voltage is smaller than the preset reference voltage;
And when the programming and erasing times are larger than or equal to the preset threshold value, continuously loading a first right shift reference voltage on a page where the data to be read are located, and acquiring second voltage state information of a storage element in the page where the data to be read are located according to the first right shift reference voltage and the preset reference voltage to decode the data to be read, wherein the first right shift reference voltage is larger than the preset reference voltage.
7. The apparatus of claim 6, wherein the apparatus further comprises:
The second processing unit is used for continuously loading a second left shift reference voltage on a page where the data to be read is located after the data to be read is decoded according to the first left shift reference voltage and the preset reference voltage and when the decoding fails, obtaining third voltage state information of a storage element in the page where the data to be read is located according to the first left shift reference voltage, the second left shift reference voltage and the preset reference voltage and decoding the data to be read, wherein the second left shift reference voltage is smaller than the first left shift reference voltage;
The second processing unit is further configured to, after the second voltage state information of the storage element in the data to be read is obtained according to the first right shift reference voltage and the preset reference voltage to decode the data to be read, when it is determined that decoding fails, continue to load a second right shift reference voltage on a page where the data to be read is located, and obtain third voltage state information of the storage element in the data to be read according to the first right shift reference voltage, the second right shift reference voltage and the preset reference voltage to decode the data to be read, where the second right shift reference voltage is greater than the first right shift reference voltage.
8. The apparatus of claim 7, wherein the preset reference voltage is separated from the first left shift reference voltage by an interval equal to the first left shift reference voltage and the second left shift reference voltage;
The interval between the preset reference voltage and the first right shift reference voltage is equal to the interval between the first right shift reference voltage and the second right shift reference voltage.
9. the apparatus of any of claims 6-8, wherein the memory cells in the page of data to be read are multi-level memory cells MlC or tri-level memory cells TlC.
10. The apparatus of any of claims 6-8, further comprising:
And the instruction analysis unit is used for determining the page of the data to be read according to the address of the page of the data to be read carried in the reading instruction after the flash memory controller receives the reading instruction.
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| CN109871594B (en) * | 2019-01-28 | 2023-02-03 | 山东华芯半导体有限公司 | NAND Flash characteristic model establishing method |
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