CN105426316A - Quota control temperature based racetrack memory chip and control method therefor - Google Patents

Abstract

The invention discloses a track memory chip and a control method thereof for temperature control based on a quota. The track storage chip of the present invention includes: a substrate, a track storage bar, a filling layer, and a cooling device; the present invention sets a movement quota within a program running interval, so as to disperse hot spots in time; and stores a data block On multiple track storage bars that are not adjacent to each other, hotspots are dispersed spatially. The invention provides a set of control methods for the temperature rise of the race track memory due to mobile operation; the method of comprehensively considering the dispersion of hot spots in time and space can reduce the temperature rise of the chip as much as possible; the simulation shows that this The invented method results in a performance loss of only 5% on average.

Description

A racetrack memory chip with temperature control based on quota and its control method

technical field

The invention relates to race track storage technology, in particular to a race track memory chip and a control method thereof based on quota-based temperature control.

Background technique

Racetrack Memory, also known as domain wall memory, is a memory that stores data based on the magnetic domain wall movement characteristics of spin magnetic materials. Due to its ultra-high storage density and access speed, track storage is gradually becoming a research hotspot in the academic and industry circles. Raceway storage utilizes large numbers of magnetic domains stored on strips of magnetic material to store data. However, in order to support high-density storage, track storage introduces a new operation: shift. A racetrack memory strip (RS) is divided into multiple domains of equal length. The arrangement of the domains is called a domain sequence, and some access terminals are evenly distributed, and each access terminal is responsible for accessing a segment of domains. In order to access each domain in this segment of domains, it is necessary to move the domain left and right on the RS (only the domain moves relative to the RS, and the access terminal and the RS do not physically move), so that the domain to be accessed corresponds to the access terminal. In the prior art, the mobile operation is accomplished by the movement of the magnetic domain wall: driven by the spin current, the magnetic domain wall moves on the nanowire and finally stops at the pinning site. However, calculations and experiments have shown that the movement generates a lot of heat, which leads to changes in the temperature of the memory chip. A sharp increase in temperature will lead to changes in the electrical parameters of the track storage, drift in the moving speed of the magnetic domain wall, a decrease in the stability of the storage material, and even burnout of the storage material in severe cases. At present, none of the existing technologies can guarantee that the temperature of the track storage will not exceed the specified index during normal operation, and no technology can control its mobile density.

Contents of the invention

In order to overcome the deficiencies of the above-mentioned prior art, the present invention provides a quota-based temperature control method for track storage and mobile operations; through the method of the present invention, the track storage can be controlled by mobile operations without substantially affecting performance. The resulting temperature rise is controlled within a reasonable range.

An object of the present invention is to provide a track memory chip with quota-based temperature control.

The track storage chip based on quota control temperature of the present invention comprises: substrate, track storage bar, filling layer and heat dissipation device; Wherein, grow a plurality of parallel nanowires on the substrate as track storage bar; A filling layer is formed on the gap and on the filling layer; a cooling device is arranged on the filling layer; each track storage bar is divided into M domains to form a domain sequence, and N access terminals are evenly distributed on each track storage bar, and each access The terminal is responsible for accessing a segment of domains; the storage of a data block adopts the hotspot dispersal method, that is, a data block is stored in domains with the same domain coordinates in the domain sequence on k track storage bars, and the k track storage The bars are not adjacent to each other, and the collection of k track memory bars used to store a data block together forms a memory bar cluster (group); the position of the domain sequence in the track memory bar where each data block is located corresponds to a port Position register; according to the thermal conductivity of the chip, the number of storage track strips that can be accommodated by the area of the heat dissipation area is 1/β, then the number of track storage strips occupied by the same data block per unit area and the heat dissipation The ratio of the total number of magnetic stripes in the area is β, where M, N, k and 1/β are all natural numbers.

For M domains on a track storage bar, N access terminals are distributed. If M is a multiple of N, each access terminal accesses M/N domains. If M is not a multiple of N, each access terminal accesses M/N domains. N is rounded up, that is, [M/N].

The heat dissipation area is an area of the isothermal body, and the chip is usually a decoding array.

The substrate is made of single crystal silicon; the nanowires are made of crystalline silicon dioxide, which comes from natural oxidation of the silicon substrate; the filling layer is made of amorphous silicon dioxide.

Another object of the present invention is to provide a temperature control method for track memory chips based on quota control.

The temperature control method of the track memory chip based on the quota control temperature of the present invention comprises the following steps:

1) Data is stored in a hotspot decentralized manner: a data block is stored in domains with the same serial number in the domain sequences of k track storage bars, and these k track storage bars are not adjacent to each other. The collection of k track storage bars that store a data block together forms a storage bar cluster. According to the calculation of the thermal conductivity of the chip, the number of storage track bars that can be accommodated by the heat dissipation area is 1/β, and the unit The ratio of the number of track memory bars occupied by the same data block in the area to the total number of track memory bars in the cooling area is β;

2) At the beginning of a program running period (period), the controller sets the number of steps that can be moved within a program running period to set the movement "quota", and the ratio of the quota to the program running period is α;

3) When a request for accessing a data block arrives at the track memory, the request is decoded according to the accessed address to obtain the domain coordinates of the requested access address decoding. Each storage bar cluster has a port location register to indicate the access port and storage The relative position of the field sequence where the bar cluster is located, by comparing the value of the port position register with the field coordinates of the requested access address decoding, the distance to be moved is obtained;

4) The controller subtracts the moving quota overhead from the remaining quota. If the quota is sufficient, multiple track storage bars where the storage bar cluster is located can move in parallel to read data blocks; if not enough, the accessed data block will be is regarded as a frozen block, enter step 5);

5) check the mark bit in the label of the frozen block, if it is net (clean) data, the controller will set the effective data (valid) bit in the label of the frozen block as invalid, and return an invalidation data (miss) to the controller, The request can continue to initiate data requests to the next-level storage; if it is dirty (dirty) data, the controller will be blocked to wait for the start of the next program execution interval.

Wherein, in step 1), the heat dissipation area is an area of the isothermal body, and the chip is usually a decoding array. According to the number of bits of the data block, it is allocated to k track memory sticks, and each bit is allocated to one track memory stick. Calculate β according to the speed of heat conduction and the interval of heat generation.

In step 2), the controller is a logic control unit that controls the operation of the track memory. Quota is defined as the total number of steps that can be moved within a program running interval; a domain moves to an adjacent domain as one step. When the quota is exhausted, no more move operations can be performed unless entering the next program execution interval.

In order to control the temperature rise within a reasonable range (20 degrees Celsius), the product of α and β should not be greater than 1/40 to ensure thermal stability. The maximum number of steps (quota) that can be moved in a program running interval can be expressed as the ratio of α multiplied by the length of the program running interval and the time cost of moving one step.

There are two types of quotas: net data quotas and dirty data quotas. A request to access clean data can only use the net data quota, while a request to access dirty data uses the dirty data quota first, and the net data quota can be used when the dirty data quota is not enough. The sum of the net data quota and the dirty data quota is the same as the previous mobile quota, which ensures the consistency of temperature control. To simplify the expression, define the ratio of the dirty data quota to the total quota as γ. When γ is 1, the net data quota is 0, so all requests to access clean data cannot perform move operations; and when γ is 0, the dirty data quota is 0, and the optimization method degenerates into a simple method.

The invention sets a moving quota in a program running interval, so as to disperse the hotspots in time; and stores a data block in a plurality of non-adjacent track storage bars, so as to disperse the hotspots in space.

Advantages of the present invention:

The invention provides a set of control methods for the temperature rise of the track memory due to mobile operation; the method of comprehensively considering the dispersion of hot spots in time and space can reduce the temperature rise of the chip as much as possible; the simulation shows that the The invented method results in a performance loss of only 5% on average.

Description of drawings

Fig. 1 is the schematic diagram of the track memory chip based on quota control temperature of the present invention;

Fig. 2 is a schematic diagram of a storage method of a data block of a track memory chip based on quota control temperature of the present invention, wherein (a) is a schematic diagram without using a hotspot dispersion mode, and (b) is a schematic diagram with a hotspot dispersion mode;

FIG. 3 is a flow chart of the temperature control method of the track memory chip based on the quota control temperature of the present invention.

detailed description

The present invention will be further described through the embodiments below in conjunction with the accompanying drawings.

As shown in Figure 1, the track memory chip based on quota control temperature in this embodiment includes: a substrate 1, a track memory bar 2, a filling layer 3 and a heat sink 4; The nano wire is used as the track storage bar 2; the filling layer 3 is formed in the gap and above the nano wire; and the heat dissipation device 4 is arranged on the silicon dioxide. Silicon dioxide is formed on the substrate 1 using monocrystalline silicon, followed by packaging environment substrate 01 and PCB board 02; nanowire 2 is made of Co ₂₀ Fe ₆₀ B ₂₀ nanowire filling layer 3 is made of amorphous silicon dioxide; Between the filling layer 3 and the heat dissipation device 4 is heat dissipation silica gel.

The track memory chip is a physical concept, and the track memory is its logical concept.

In the working state, the heat of the memory strip is mainly generated by the current pulse inside the nanowire to move the magnetic domain wall under the Joule heating effect. While the heat is heating up the nanowire, it passes through the upper filling layer and the lower substrate. Diffusion, and then by the heat exchange between the outer layer of the chip and the heat sink, the heat is finally exported to the outside world.

Multiple bits can be stored on a track memory stick, but it is not efficient to store all the bits of the same data block on one track memory stick. Because this will cause the track memory bar to be moved and accessed multiple times. A relatively common and efficient data mapping method is to disperse a data block on multiple track memory sticks, and multiple track memory sticks move at the same time to read data in parallel. However, placing these track memory strips next to each other leads to localized hotspots, because the fewer magnetic strips that heat up per unit area, the less the nanowire layer temperature rises. Therefore, placing the track memory strips mapped to the same data block in the storage array can increase the heat dissipation area and reduce the temperature rise, as shown in Figure 2. Take the ratio of the number of magnetic stripes occupied by the same data block in a unit area to the total number of magnetic stripes in the area as β. According to the calculation of the thermal conductivity of the chip, the area that can be regarded as the same heat dissipation area can only accommodate 8 magnetic stripes. Therefore, set β to 1/8. Calculate β according to the speed of heat conduction and the heat generation interval, which is different in different cases. Here, β is simplified as the reciprocal of the distance +1 between the nearest two track storage bars in the same cluster.

In order to realize the control method of the present invention, this embodiment uses the race track memory as the last level cache in the CPU. This level of storage is usually set-associative, and each data block includes two parts: tag and data. All data in a group (set) share the group address and are distinguished by labels. Usually, the access of the last level cache is to compare the tags first, and then access the data after a hit. When a request arrives at the cache controller, the request is decoded according to the address it accessed and sent to the corresponding group. Multiple labels in the group are compared to determine whether a hit occurs. At the same time, the hit data needs to check the validity (validity) and consistency (coherence) status. The data storage of the present invention ensures that tag access does not require a move operation, therefore, comparing tags does not involve a move operation. If the access hits on a valid message, the track storage bar storing the data will be moved to the specified location, and then the corresponding data will be read and written accordingly. At this time, if the moving and reading and writing operations can be successfully completed, the cache execution of this request ends and can serve the next request. If the result is a miss (miss) or invalid data (invalid), the request will be sent to the next level of storage (main memory here), and the cache may block subsequent requests until the request is stored at the next level Finish. The cache controller controls the read operations of the track memory.

The temperature control method of the track storage chip based on the quota control temperature of this embodiment includes the following steps:

1) A 32-bit data block is stored in fields with the same serial number in the domain sequence of 32 track memory strips, and these 32 track memory strips are not adjacent to each other, calculated according to the thermal conductivity of the chip , the number of storage track bars that can be accommodated by the area of the heat dissipation area is 8, then the number of track storage bars occupied by the same data block per unit area is the same as the number of total track storage bars in the heat dissipation area The ratio of numbers is 1/8.

2) At the beginning of a program running interval, the cache controller sets the number of steps that can be moved within a program running interval to set the movement quota, and the ratio of the quota to the program running interval is α; the quota is divided into two types: net data quota and dirty data quota. Data quota, define the ratio of dirty data quota to total quota as γ.

3) When a request to access a data block arrives in the cache, the request is decoded according to the accessed address, and the domain coordinates of the requested access address decoding are obtained, and then sent to the corresponding group, and multiple tags in the group are compared to determine whether a hit occurs. The hit data needs to check the validity and consistency status; if the access hits on a valid information, go to step 4), if the result is a miss (miss) or the data is invalid (invalid), the request will be sent down In the first-level storage (main memory here), the cache may block subsequent requests until the request is completed in the next-level storage.

4) Each storage bar cluster has a port position register to indicate the relative position of the access port and the domain sequence where the storage bar cluster is located. By comparing the value of the port position register with the domain coordinates of the requested access address decoding, it is obtained that the port needs to be moved. distance.

5) The cache controller subtracts the moving quota overhead from the remaining quota. If the quota is sufficient, multiple track storage bars where the storage bar cluster is located can move in parallel to read data blocks; if not enough, the accessed data block Will be treated as a frozen block, go to step 6).

6) Check the tag position in the tag of the frozen block, if it is net data, the cache controller will set the effective data (valid) bit in the tag of the frozen block as invalid, and return an invalidation data (miss) of the cache controller, so that The request can continue to initiate a data request to the next-level storage; if it is dirty data, the cache controller will be blocked to wait for the start of the next interval.

Finally, it should be noted that the purpose of publishing the implementation is to help further understand the present invention, but those skilled in the art can understand that various replacements and modifications can be made without departing from the spirit and scope of the present invention and the appended claims. It is possible. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the protection scope of the present invention is subject to the scope defined in the claims.

Claims (10)

1. based on a racing track storage chip for quota control temperature, it is characterized in that, described racing track storage chip comprises: substrate, racing track memory stick, packed layer and heat abstractor; Wherein, at the parallel nano wire of Grown many as racing track memory stick; The gap of nano wire and above form packed layer; Packed layer arranges heat abstractor; Each racing track memory stick is divided into M territory, formative region sequence, and N number of access end that each racing track memory stick distributes equably, each access end is responsible for access one section of territory; The storage of a data block adopts focus dispersing mode, namely the territory that the territory coordinate during data block is dispersed on k racing track memory stick territory sequence is identical stores, and this k racing track memory stick is non-conterminous mutually, the set being used for jointly storing k racing track memory stick of a data block forms a memory stick bunch; The corresponding port position register in position of the territory sequence in the racing track memory stick at each data block place; According to the coefficient of heat conductivity of chip, the number of the storage racing track bar that the area obtaining heat dissipation region can hold is 1/ β, the ratio of the total magnetic stripe number in the number of the racing track memory stick then in unit area shared by same data block and heat dissipation region is β, and wherein, M, N, k and 1/ β are natural number.

2. racing track storage chip as claimed in claim 1, is characterized in that, to distribute N number of access end for M territory on a racing track memory stick, if M is the multiple of N, then each access end access M/N territory, if M is not the multiple of N, then each access end access M/N rounds, i.e. [M/N].

3. racing track storage chip as claimed in claim 1, it is characterized in that, described heat dissipation region is a panel region of isothermal body, is a decoding arrays in chip.

4. racing track storage chip as claimed in claim 1, is characterized in that, described substrate adopts monocrystalline silicon; Described nano wire adopts crystalline silicon dioxide, by silicon substrate autoxidation; Described packed layer adopts the silicon dioxide of amorphous state.

5. based on a temperature-controlled process for the racing track storage chip of quota control temperature, it is characterized in that, described control method comprises the following steps:

1) focus dispersing mode is adopted to store data: data block is dispersed on the identical territory of sequence number in the territory sequence on k racing track memory stick and stores, and this k racing track memory stick is non-conterminous mutually, the set being used for jointly storing k racing track memory stick of a data block forms a memory stick bunch, coefficient of heat conductivity according to chip calculates, the number of the storage racing track bar that the area obtaining heat dissipation region can hold is 1/ β, the number of the racing track memory stick then in unit area shared by same data block is β with the ratio of the number of the total racing track memory stick in heat dissipation region, wherein, k and 1/ β is natural number,

2) when a program traffic coverage starts, controller is arranged in a program traffic coverage can the step number setting mobile " quota " of movement, and the ratio of quota and program traffic coverage is α;

3) when the request of a visit data block arrives racing track storer, ask to decode according to the address of access, obtain the territory coordinate of request access address decoder, each memory stick bunch has a port position register to be used to refer to the relative position of the territory sequence at access port and memory stick bunch place, by the territory coordinate of the numerical value and request access address decoder that compare port position register, draw the distance needing movement;

4) controller deducts the quota expense of movement from remaining quota, if quota is enough, the movement that walks abreast of multiple racing track memory sticks at memory stick bunch place can perform read block; If not, that accessed data block will be taken as freezes block, enters step 5);

5) check the marker bit that freezes in the label of block, if it is net amount certificate, it is invalid that valid data position in the label freezing block is set to by controller, and return controller fail data, makes request can continue to store to next stage to initiate request of data; If dirty data, controller will get clogged, and waits for the beginning of next program traffic coverage.

6. control method as claimed in claim 5, is characterized in that, in step 1) in, according to the bits allocation of data block on k racing track memory stick, each bit is distributed on a racing track memory stick.

7. control method as claimed in claim 5, is characterized in that, in step 1) in, carry out calculating β according to the speed of heat conduction and heat production interval.

8. control method as claimed in claim 5, is characterized in that, in step 2) in, quota is defined as transportable total step number in a program traffic coverage; It is a step that a territory moves to adjacent territory; Quota in a program traffic coverage is expressed as α and is multiplied by the length of program traffic coverage and moves the ratio of the time overhead moved a step.

9. control method as claimed in claim 5, it is characterized in that, described quota is divided into two kinds: clean quota of data and dirty data quota.The request of an access net amount certificate can only use clean quota of data, and the request of accessing dirty data preferentially uses dirty data quota, can use clean quota of data when dirty data quota is inadequate.

10. control method as claimed in claim 5, it is characterized in that, α and β product is not more than 1/40, to ensure thermal stability.