CN105426316A - Quota control temperature based racetrack memory chip and control method therefor - Google Patents
Quota control temperature based racetrack memory chip and control method therefor Download PDFInfo
- Publication number
- CN105426316A CN105426316A CN201510782745.2A CN201510782745A CN105426316A CN 105426316 A CN105426316 A CN 105426316A CN 201510782745 A CN201510782745 A CN 201510782745A CN 105426316 A CN105426316 A CN 105426316A
- Authority
- CN
- China
- Prior art keywords
- racing track
- quota
- memory stick
- territory
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 27
- 230000017525 heat dissipation Effects 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000003860 storage Methods 0.000 claims description 38
- 239000002070 nanowire Substances 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 230000008569 process Effects 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 238000003491 array Methods 0.000 claims description 3
- 230000008014 freezing Effects 0.000 claims description 3
- 238000007710 freezing Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 239000003550 marker Substances 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 238000006701 autoxidation reaction Methods 0.000 claims description 2
- 229910021488 crystalline silicon dioxide Inorganic materials 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 239000006185 dispersion Substances 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 230000005381 magnetic domain Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000013506 data mapping Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000004519 grease Substances 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000696 magnetic material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000009987 spinning Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B33/00—Constructional parts, details or accessories not provided for in the other groups of this subclass
- G11B33/14—Reducing influence of physical parameters, e.g. temperature change, moisture, dust
- G11B33/1406—Reducing the influence of the temperature
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7201—Logical to physical mapping or translation of blocks or pages
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7209—Validity control, e.g. using flags, time stamps or sequence numbers
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Hall/Mr Elements (AREA)
Abstract
The invention discloses a quota control temperature based racetrack memory chip and a control method therefor. The racetrack memory chip comprises a substrate, racetrack memory strips, a filling layer and a heat dissipation apparatus. A mobile quota is set in a program running interval, so that hot spot dispersion is performed in time; and moreover, a data block is stored in the non-adjacent racetrack memory strips, so that hot spot dispersion is performed in space. The invention provides a control method for a temperature rise of a racetrack memory due to mobile operation. The method comprehensively considers hot spot diffusion in time and space, so that the temperature rise of the chip can be reduced as far as possible; and due to analog display, the performance loss caused by the method is only 5% averagely.
Description
Technical field
The present invention relates to racing track memory technology, particularly relate to a kind of racing track storage chip based on quota control temperature and control method thereof.
Background technology
Racing track storer (RacetrackMemory), is also called neticdomain wall storer (Domainwallmemory), is a kind of storer based on storing data from gyromagnetic material magnetic domain wall moving characteristic.Racing track stores due to the storage density of its superelevation and access speed, becomes the study hotspot of educational circles, industry at present just gradually.Racing track memory is stored in a large amount of magnetic domains on strip magnetic material to store data.But for supporting highdensity storage, racing track storage introduces new operation: mobile (shift).A racing track memory stick (RacetrackmemoryStripe, RS) is divided into multiple isometric territory, and the arrangement in territory is called territory sequence, and uniform some access ends of distribution, each access end is responsible for access one section of territory.For accessing each territory in this section of territory, needing territory to be moved left and right on RS (only have territory relative to the movement of RS, access end and RS physically do not move), making the territory of required access corresponding at access end place.In prior art, mobile operation relies on the movement of neticdomain wall: neticdomain wall, under spinning current drives, nano wire moves and finally stops at anchor region (pinningsite).But calculating and experiment all show, movement can produce amount of heat, thus causes the change of storage chip temperature.High temperature rising can cause racing track stored electricity parameter change, and magnetic domain wall moving speed is drifted about, and storage medium stability declines, and even causes storage medium to burn time serious.At present, prior art all can not ensure that racing track is stored in temperature when normally working and is no more than set quota, does not then have technology can control it and moves density.
Summary of the invention
In order to overcome above-mentioned the deficiencies in the prior art, the invention provides a kind of temperature-controlled process based on quota for the operation of racing track storing mobile; When substantially not affecting performance, racing track can be stored the temperature rising caused by mobile operation and controlling in rational scope by method of the present invention.
One object of the present invention is to provide a kind of racing track storage chip based on quota control temperature.
Racing track storage chip based on quota control temperature of the present invention comprises: substrate, racing track memory stick, packed layer and heat abstractor; Wherein, at the parallel nano wire of Grown many as racing track memory stick; The gap of nano wire and above form packed layer; Packed layer arranges heat abstractor; Each racing track memory stick is divided into M territory, formative region sequence, and N number of access end that each racing track memory stick distributes equably, each access end is responsible for access one section of territory; The storage of a data block adopts focus dispersing mode, namely the territory that the territory coordinate during data block is dispersed on k racing track memory stick territory sequence is identical stores, and this k racing track memory stick is non-conterminous mutually, the set being used for jointly storing k racing track memory stick of a data block forms a memory stick bunch (group); The corresponding port position register in position of the territory sequence in the racing track memory stick at each data block place; According to the coefficient of heat conductivity of chip, the number of the storage racing track bar that the area obtaining heat dissipation region can hold is 1/ β, the ratio of the total magnetic stripe number in the number of the racing track memory stick then in unit area shared by same data block and heat dissipation region is β, and wherein, M, N, k and 1/ β are natural number.
To distribute N number of access end for M territory on a racing track memory stick, if M is the multiple of N, then each access end access M/N territory, if M is not the multiple of N, then each access end is accessed on M/N and is rounded, i.e. [M/N].
Heat dissipation region is a panel region of isothermal body, a normally decoding arrays in chip.
Substrate adopts monocrystalline silicon; Nano wire adopts crystalline silicon dioxide, by silicon substrate autoxidation (nativeoxidation); Packed layer adopts the silicon dioxide of amorphous state.
Another object of the present invention is the temperature-controlled process providing a kind of racing track storage chip based on quota control temperature.
The temperature-controlled process of the racing track storage chip based on quota control temperature of the present invention, comprises the following steps:
1) focus dispersing mode is adopted to store data: data block is dispersed on the identical territory of sequence number in the territory sequence on k racing track memory stick and stores, and this k racing track memory stick is non-conterminous mutually, the set being used for jointly storing k racing track memory stick of a data block forms a memory stick bunch, coefficient of heat conductivity according to chip calculates, the number of the storage racing track bar that the area obtaining heat dissipation region can hold is 1/ β, the number of the racing track memory stick then in unit area shared by same data block is β with the ratio of the number of the total racing track memory stick in heat dissipation region,
2) when a program traffic coverage (period) starts, controller is arranged in a program traffic coverage can mobile " quota " (quota) of step number setting of movement, and the ratio of quota and program traffic coverage is α;
3) when the request of a visit data block arrives racing track storer, ask to decode according to the address of access, obtain the territory coordinate of request access address decoder, each memory stick bunch has a port position register to be used to refer to the relative position of the territory sequence at access port and memory stick bunch place, by the territory coordinate of the numerical value and request access address decoder that compare port position register, draw the distance needing movement;
4) controller deducts the quota expense of movement from remaining quota, if quota is enough, the movement that walks abreast of multiple racing track memory sticks at memory stick bunch place can perform read block; If not, that accessed data block will be taken as freezes block, enters step 5);
5) marker bit freezed in the label of block is checked, if it is clean (clean) data, it is invalid that valid data (valid) position in the label freezing block is set to by controller, and return controller fail data (miss), make request can continue to store to next stage to initiate request of data; If dirty (dirty) data, controller will get clogged, to wait for the beginning of next program traffic coverage.
Wherein, in step 1) in, heat dissipation region is a panel region of isothermal body, a normally decoding arrays in chip.According to the bits allocation of data block on k racing track memory stick, each bit is distributed on a racing track memory stick.Calculating β is carried out according to the speed of heat conduction and heat production interval.
In step 2) in, controller is the logic control element controlling racing track storage operation.Quota is defined as transportable total step number in a program traffic coverage; It is a step that a territory moves to adjacent territory.When quota is used up, except the next program traffic coverage of non-entry, more mobile operation can not be had again to be performed.
For control temperature rises above zone of reasonableness (20 degrees Celsius), α and β product should be not more than 1/40, to ensure thermal stability.In a program traffic coverage transportable maximum step number (quota) can be expressed as α be multiplied by the length of program traffic coverage with move the ratio of the time overhead moved a step.
Quota is divided into two kinds: clean quota of data and dirty data quota.The request of an access net amount certificate can only use clean quota of data, and the request of accessing dirty data preferentially uses dirty data quota, can use clean quota of data when dirty data quota is inadequate.Clean quota of data is identical with mobile quota before with the summation of dirty data quota, ensure that temperature controlled consistance.Simple for stating, the ratio of definition dirty data quota and total quota is γ.When γ is 1, clean quota of data is 0, and therefore the request of all access net amount certificates all can not perform mobile operation; And when γ is 0, dirty data quota is 0, optimization method deteriorates to straightforward procedure.
The present invention arranges mobile quota in a program traffic coverage, thus carries out focus dispersion from the time; Further, a data block is stored on mutual non-conterminous multiple racing track memory stick, from spatially carrying out focus dispersion.
Advantage of the present invention:
The invention provides the control method that a set of racing track storer causes temperature to rise because of mobile operation; Consider the method for time, focus dispersion spatially, can the temperature of reduction chip as much as possible raise; Simulative display, the performance loss that method of the present invention causes on average only has 5%.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the racing track storage chip based on quota control temperature of the present invention;
Fig. 2 is the schematic diagram of the storage mode of a data block of the racing track storage chip based on quota control temperature of the present invention, wherein, a (), for not adopting the schematic diagram of focus dispersing mode, (b) is the schematic diagram adopting focus dispersing mode;
Fig. 3 is the process flow diagram of the temperature-controlled process of the racing track storage chip based on quota control temperature of the present invention.
Embodiment
Below in conjunction with accompanying drawing, by embodiment, the present invention will be further described.
As shown in Figure 1, the racing track storage chip based on quota control temperature of the present embodiment comprises: substrate 1, racing track memory stick 2, packed layer 3 and heat abstractor 4; Wherein, many parallel nano wires are grown on substrate 1 as racing track memory stick 2; The gap of nano wire and above formed packed layer 3; Heat abstractor 4 is set on silica.Adopt on monocrystalline silicon at substrate 1 and form silicon dioxide, be followed successively by packaging environment substrate 01 and pcb board 02 below; Nano wire 2 adopts Co
20fe
60b
20nano wire packed layer 3 adopts the silicon dioxide of amorphous state; It is thermal grease between packed layer 3 and heat abstractor 4.
Racing track storage chip is a physical concept, and racing track storer is its logical concept.
During duty, the heat of racing track memory stick is mainly produced under joule heating effect by the current impulse of nano wire inside promotion magnetic domain wall moving, heat is while making nano wire heat up, spread through the packed layer on upper strata and the substrate of lower floor, and then by the heat exchange action between chip skin and heat radiator, finally heat is exported to the external world.
Racing track memory stick can store multiple bit, but all bit storage of same data block are not efficient on a racing track memory stick.Because this will cause racing track memory stick repeatedly move and access.A kind of more common efficient data mapping mode is dispersed on multiple racing track memory stick by a data block, and multiple racing track memory stick moves simultaneously, thus parallel read data.But these racing track memory stick placed adjacent can be caused hot localised points, because the magnetic stripe of unit area internal heat generation is fewer, then nano wire layer temperature rises fewer.Therefore, the racing track memory stick that have mapped same data block is placed respectively in storage array, can increasing heat radiation area, reduce temperature and raise, as shown in Figure 2.Using the ratio of the magnetic stripe number shared by data block same in unit area and the total magnetic stripe number in region as β.Coefficient of heat conductivity according to chip calculates, and the area that can regard as same heat dissipation region only can hold 8 magnetic stripes.Therefore, β is set to 1/8.Calculating β is carried out according to the speed of heat conduction and heat production interval, not identical under different situations, β is reduced to the inverse of the spacing+1 of two racing track memory sticks nearest in same bunch here.
For realizing control method of the present invention, the present embodiment is using racing track storer as the last level cache in CPU, and this grade of storage is generally group and is connected (set-associative), and each data block comprises label and data two parts.All data sharing group addresss in a group (set), and distinguished with label.Usually, the access of last level cache first compares label, visits again data after hit.When a request arrives cache controller, ask to decode according to the address of its access, thus be sent to corresponding group.In group, multiple label compares and determines whether to hit.Meanwhile, the data be hit need to check validity (validity) and consistance (coherence) state.Data of the present invention store and ensure that the access of label does not need mobile operation, therefore, compare label and do not relate to mobile operation.If access hit is on an effective information, the racing track memory stick storing data will be moved to assigned address, and corresponding data is performed corresponding read-write operation then.Now, if movement and read-write operation can complete smoothly, buffer memory performs this request to be terminated, and can be next request service.If result is miss (miss) or data invalid (invalid), request will be sent to next stage and be stored (being main memory) herein, be cached with and may block follow-up request, until this request completes in next stage storage.Cache controller controls the read operation of racing track storer.
The temperature-controlled process of the racing track storage chip based on quota control temperature of the present embodiment, comprises the following steps:
1) territory that the sequence number during the data block of 32 bits is dispersed on 32 racing track memory sticks territory sequence is identical stores, and these 32 racing track memory sticks are non-conterminous mutually, coefficient of heat conductivity according to chip calculates, the number of the storage racing track bar that the area obtaining heat dissipation region can hold is 8, then the number of the racing track memory stick in unit area shared by same data block is 1/8 with the ratio of the number of the total racing track memory stick in heat dissipation region.
2) when a program traffic coverage starts, cache controller to be arranged in a program traffic coverage and the step number of movement can to set mobile quota, and the ratio of quota and program traffic coverage is α; Quota is divided into two kinds: clean quota of data and dirty data quota, the ratio of definition dirty data quota and total quota is γ.
3) when the request of a visit data block arrives buffer memory, ask to decode according to the address of access, obtain the territory coordinate of request access address decoder, thus be sent to corresponding group, in group, multiple label compares and determines whether to hit, and the data be hit need to check validity and coherency state; If access hit is on an effective information, then enter step 4), if result is miss (miss) or data invalid (invalid), request will be sent to next stage and be stored (being main memory) herein, be cached with and may block follow-up request, until this request completes in next stage storage.
4) each memory stick bunch has a port position register to be used to refer to the relative position of the territory sequence at access port and memory stick bunch place, by the territory coordinate of the numerical value and request access address decoder that compare port position register, draw the distance needing movement.
5) cache controller deducts the quota expense of movement from remaining quota, if quota is enough, the movement that walks abreast of multiple racing track memory sticks at memory stick bunch place can perform read block; If not, that accessed data block will be taken as freezes block, enters step 6).
6) marker bit freezed in the label of block is checked, if it is net amount certificate, it is invalid that valid data (valid) position in the label freezing block is set to by cache controller, and return cache controller fail data (miss), makes request can continue to store to next stage to initiate request of data; If dirty data, cache controller will get clogged, to wait for next interval beginning.
It is finally noted that, the object publicizing and implementing mode is to help to understand the present invention further, but it will be appreciated by those skilled in the art that: without departing from the spirit and scope of the invention and the appended claims, various substitutions and modifications are all possible.Therefore, the present invention should not be limited to the content disclosed in embodiment, and the scope that the scope of protection of present invention defines with claims is as the criterion.
Claims (10)
1. based on a racing track storage chip for quota control temperature, it is characterized in that, described racing track storage chip comprises: substrate, racing track memory stick, packed layer and heat abstractor; Wherein, at the parallel nano wire of Grown many as racing track memory stick; The gap of nano wire and above form packed layer; Packed layer arranges heat abstractor; Each racing track memory stick is divided into M territory, formative region sequence, and N number of access end that each racing track memory stick distributes equably, each access end is responsible for access one section of territory; The storage of a data block adopts focus dispersing mode, namely the territory that the territory coordinate during data block is dispersed on k racing track memory stick territory sequence is identical stores, and this k racing track memory stick is non-conterminous mutually, the set being used for jointly storing k racing track memory stick of a data block forms a memory stick bunch; The corresponding port position register in position of the territory sequence in the racing track memory stick at each data block place; According to the coefficient of heat conductivity of chip, the number of the storage racing track bar that the area obtaining heat dissipation region can hold is 1/ β, the ratio of the total magnetic stripe number in the number of the racing track memory stick then in unit area shared by same data block and heat dissipation region is β, and wherein, M, N, k and 1/ β are natural number.
2. racing track storage chip as claimed in claim 1, is characterized in that, to distribute N number of access end for M territory on a racing track memory stick, if M is the multiple of N, then each access end access M/N territory, if M is not the multiple of N, then each access end access M/N rounds, i.e. [M/N].
3. racing track storage chip as claimed in claim 1, it is characterized in that, described heat dissipation region is a panel region of isothermal body, is a decoding arrays in chip.
4. racing track storage chip as claimed in claim 1, is characterized in that, described substrate adopts monocrystalline silicon; Described nano wire adopts crystalline silicon dioxide, by silicon substrate autoxidation; Described packed layer adopts the silicon dioxide of amorphous state.
5. based on a temperature-controlled process for the racing track storage chip of quota control temperature, it is characterized in that, described control method comprises the following steps:
1) focus dispersing mode is adopted to store data: data block is dispersed on the identical territory of sequence number in the territory sequence on k racing track memory stick and stores, and this k racing track memory stick is non-conterminous mutually, the set being used for jointly storing k racing track memory stick of a data block forms a memory stick bunch, coefficient of heat conductivity according to chip calculates, the number of the storage racing track bar that the area obtaining heat dissipation region can hold is 1/ β, the number of the racing track memory stick then in unit area shared by same data block is β with the ratio of the number of the total racing track memory stick in heat dissipation region, wherein, k and 1/ β is natural number,
2) when a program traffic coverage starts, controller is arranged in a program traffic coverage can the step number setting mobile " quota " of movement, and the ratio of quota and program traffic coverage is α;
3) when the request of a visit data block arrives racing track storer, ask to decode according to the address of access, obtain the territory coordinate of request access address decoder, each memory stick bunch has a port position register to be used to refer to the relative position of the territory sequence at access port and memory stick bunch place, by the territory coordinate of the numerical value and request access address decoder that compare port position register, draw the distance needing movement;
4) controller deducts the quota expense of movement from remaining quota, if quota is enough, the movement that walks abreast of multiple racing track memory sticks at memory stick bunch place can perform read block; If not, that accessed data block will be taken as freezes block, enters step 5);
5) check the marker bit that freezes in the label of block, if it is net amount certificate, it is invalid that valid data position in the label freezing block is set to by controller, and return controller fail data, makes request can continue to store to next stage to initiate request of data; If dirty data, controller will get clogged, and waits for the beginning of next program traffic coverage.
6. control method as claimed in claim 5, is characterized in that, in step 1) in, according to the bits allocation of data block on k racing track memory stick, each bit is distributed on a racing track memory stick.
7. control method as claimed in claim 5, is characterized in that, in step 1) in, carry out calculating β according to the speed of heat conduction and heat production interval.
8. control method as claimed in claim 5, is characterized in that, in step 2) in, quota is defined as transportable total step number in a program traffic coverage; It is a step that a territory moves to adjacent territory; Quota in a program traffic coverage is expressed as α and is multiplied by the length of program traffic coverage and moves the ratio of the time overhead moved a step.
9. control method as claimed in claim 5, it is characterized in that, described quota is divided into two kinds: clean quota of data and dirty data quota.The request of an access net amount certificate can only use clean quota of data, and the request of accessing dirty data preferentially uses dirty data quota, can use clean quota of data when dirty data quota is inadequate.
10. control method as claimed in claim 5, it is characterized in that, α and β product is not more than 1/40, to ensure thermal stability.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510782745.2A CN105426316B (en) | 2015-11-09 | 2015-11-09 | A kind of racing track storage chip and its control method based on quota control temperature |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510782745.2A CN105426316B (en) | 2015-11-09 | 2015-11-09 | A kind of racing track storage chip and its control method based on quota control temperature |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105426316A true CN105426316A (en) | 2016-03-23 |
| CN105426316B CN105426316B (en) | 2018-02-13 |
Family
ID=55504533
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510782745.2A Expired - Fee Related CN105426316B (en) | 2015-11-09 | 2015-11-09 | A kind of racing track storage chip and its control method based on quota control temperature |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105426316B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105868482A (en) * | 2016-04-07 | 2016-08-17 | 中国石油大学(北京) | Method and device for calculating depositional stage micro-amplitude palaeohigh |
| CN107239409A (en) * | 2017-05-08 | 2017-10-10 | 深圳大学 | A kind of significant data distribution method and its system based on temperature |
| WO2018205085A1 (en) * | 2017-05-08 | 2018-11-15 | 深圳大学 | Temperature-based important data allocation method and system therefor |
| CN109446018A (en) * | 2018-09-17 | 2019-03-08 | 至誉科技（武汉）有限公司 | The storage device of chip power-consumption adjusting is carried out based on environment temperature |
| CN110209374A (en) * | 2019-05-23 | 2019-09-06 | 浙江大学 | A kind of multiplier and its operating method based on racetrack memory |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8140739B2 (en) * | 2008-08-08 | 2012-03-20 | Imation Corp. | Flash memory based storage devices utilizing magnetoresistive random access memory (MRAM) to store files having logical block addresses stored in a write frequency file buffer table |
| CN103810119A (en) * | 2014-02-28 | 2014-05-21 | 北京航空航天大学 | Cache design method for reducing STT-RAM power consumption by utilizing temperature difference on three-dimensional integrated circuit chip |
| US8772889B2 (en) * | 2012-11-20 | 2014-07-08 | International Business Machines Corporation | Magnetic domain wall shift register memory device readout |
| CN104321823A (en) * | 2012-07-06 | 2015-01-28 | 国际商业机器公司 | Domain wall motion in perpendicularly magnetized wires having magnetic multilayers with engineered interfaces |
| CN102483947B (en) * | 2009-08-26 | 2015-04-01 | 国际商业机器公司 | Array architecture and operation for magnetic racetrack memory |
| CN104520825A (en) * | 2012-08-06 | 2015-04-15 | 高通股份有限公司 | Multi-core compute cache coherency with a release consistency memory ordering model |
| US9042151B2 (en) * | 2013-03-15 | 2015-05-26 | International Business Machines Corporation | Racetrack memory with electric-field assisted domain wall injection for low-power write operation |
-
2015
- 2015-11-09 CN CN201510782745.2A patent/CN105426316B/en not_active Expired - Fee Related
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8140739B2 (en) * | 2008-08-08 | 2012-03-20 | Imation Corp. | Flash memory based storage devices utilizing magnetoresistive random access memory (MRAM) to store files having logical block addresses stored in a write frequency file buffer table |
| CN102483947B (en) * | 2009-08-26 | 2015-04-01 | 国际商业机器公司 | Array architecture and operation for magnetic racetrack memory |
| CN104321823A (en) * | 2012-07-06 | 2015-01-28 | 国际商业机器公司 | Domain wall motion in perpendicularly magnetized wires having magnetic multilayers with engineered interfaces |
| CN104520825A (en) * | 2012-08-06 | 2015-04-15 | 高通股份有限公司 | Multi-core compute cache coherency with a release consistency memory ordering model |
| US8772889B2 (en) * | 2012-11-20 | 2014-07-08 | International Business Machines Corporation | Magnetic domain wall shift register memory device readout |
| US9042151B2 (en) * | 2013-03-15 | 2015-05-26 | International Business Machines Corporation | Racetrack memory with electric-field assisted domain wall injection for low-power write operation |
| CN103810119A (en) * | 2014-02-28 | 2014-05-21 | 北京航空航天大学 | Cache design method for reducing STT-RAM power consumption by utilizing temperature difference on three-dimensional integrated circuit chip |
Non-Patent Citations (3)
| Title |
|---|
| 何炎祥 等: "新型非易失性存储器架构的缓存优化方法综述", 《计算机研究与发展》 * |
| 孙广宇 等: "面向非易失内存的结构和系统级设计与优化综述", 《华东师范大学学报(自然科学版)》 * |
| 马晓萍 等: "磁热噪音下纳米铁磁线磁畴壁脱钉行为", 《科学通报》 * |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105868482A (en) * | 2016-04-07 | 2016-08-17 | 中国石油大学(北京) | Method and device for calculating depositional stage micro-amplitude palaeohigh |
| CN105868482B (en) * | 2016-04-07 | 2018-09-07 | 中国石油大学(北京) | A kind of deposition phase spends the projectional technique and device of palaeohigh a little |
| CN107239409A (en) * | 2017-05-08 | 2017-10-10 | 深圳大学 | A kind of significant data distribution method and its system based on temperature |
| WO2018205085A1 (en) * | 2017-05-08 | 2018-11-15 | 深圳大学 | Temperature-based important data allocation method and system therefor |
| CN107239409B (en) * | 2017-05-08 | 2020-12-29 | 深圳大学 | Temperature-based important data distribution method and system |
| CN109446018A (en) * | 2018-09-17 | 2019-03-08 | 至誉科技（武汉）有限公司 | The storage device of chip power-consumption adjusting is carried out based on environment temperature |
| CN110209374A (en) * | 2019-05-23 | 2019-09-06 | 浙江大学 | A kind of multiplier and its operating method based on racetrack memory |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105426316B (en) | 2018-02-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105426316A (en) | Quota control temperature based racetrack memory chip and control method therefor | |
| TWI520139B (en) | Data storage device and flash memory control method | |
| CN104516471B (en) | Method and device for managing power supply of storage system | |
| CN105930282B (en) | A kind of data cache method for NAND FLASH | |
| CN103493026B (en) | Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers | |
| WO2015169245A1 (en) | Data caching method, cache and computer system | |
| TW201945948A (en) | Accelerate data access in memory systems via data stream segregation | |
| CN107924375A (en) | Order for high-speed memory interface is arbitrated | |
| ATE422688T1 (en) | STRATEGIES FOR READING INFORMATION FROM A MASS STORAGE MEDIUM USING A CACHE MEMORY | |
| CN103810119B (en) | The temperature difference on sheet is utilized to reduce the cache design method of STT-MRAM power consumption | |
| CN106095342A (en) | Watt recording disc array construction method and the system of a kind of dynamically changeable long strip | |
| KR20160040274A (en) | Memory access processing method, apparatus, and system | |
| KR20130054141A (en) | Apparatus to manage efficient data migration between tiers | |
| CN106201348B (en) | The buffer memory management method and device of non-volatile memory device | |
| CN106294197A (en) | A kind of page frame replacement method towards nand flash memory | |
| CN107729268A (en) | A kind of memory expansion apparatus and method based on CAPI interfaces | |
| TW201935262A (en) | Memory access communications through message passing interface implemented in memory systems | |
| CN108319556B (en) | A kind of new memory prefetching control device and method towards refreshing | |
| CN104991743B (en) | Loss equalizing method applied to solid state hard disc resistance-variable storing device caching | |
| CN107526689A (en) | Read cache management | |
| CN104699424A (en) | Page hot degree based heterogeneous memory management method | |
| CN100428193C (en) | Data preacquring method for use in data storage system | |
| CN101800768B (en) | Gridding data transcription generation method based on storage alliance subset partition | |
| CN106775453A (en) | A kind of construction method for mixing storage array | |
| CN109240944A (en) | A kind of data read-write method based on variable length cache lines |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180213 |