CN105375917B - Frequency divider - Google Patents
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- CN105375917B CN105375917B CN201410773807.9A CN201410773807A CN105375917B CN 105375917 B CN105375917 B CN 105375917B CN 201410773807 A CN201410773807 A CN 201410773807A CN 105375917 B CN105375917 B CN 105375917B
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Abstract
Embodiment of the disclosure provides a kind of frequency divider.This 2NFrequency divider include remove 2 paths, receive input clock signal and including it is cascade it is N number of remove 2 allocator modules, wherein N be positive integer and minimum 1；And at least one feedback path, each feedback path includes cascade N number of latch module, each latch module includes the first receiving end and the second receiving end, is respectively used to receive by except the corresponding signal removed before and after 2 allocator modules in 2 paths；Each latch module further includes third receiving end, and for receiving control signal, which makes the 2 of feedback path output input clock signal1、22……2NAt least one of fractional frequency signal.It can be worked in higher frequency according to the frequency divider of the disclosure compared with traditional frequency divider, the clock output of multiple phase alignments can be provided, and shake is maintained into reduced levels while realizing widened frequency dividing ratio range.
Description
Cross reference to related applications
This application claims the U.S. Provisional Patent Application No.61/915 submitted on December 13rd, 2013,706 equity,
The entire disclosure is incorporated in this by reference.
Technical field
This disclosure relates to frequency divider, and in particular, to realize the 2 of multiple-channel outputNThe frequency divider of integral frequency divisioil.
Background technique
Fig. 1 depicts a kind of traditional 2NFraction frequency device.The input terminal of the frequency divider receives clock signal CKIN, and cascades
2NAllocator module chain generates the clock signal " DV2 " of different frequency, " DV4 " to " DV2N", and these pass through each point
Frequency device module (i.e. "/2 " module in Fig. 1) signal is selected by multiplexer (MUX).Optionally, output clock is defeated
Enter clock signal " CKIN " in d type flip flop (DFF) relocking." CKIN " signal is bypassed in the additional multiplexer of output end
To end.The frequency divider provides the 2 of two phase place alignmentNFrequency-dividing clock output.But due to divider chain and multiplexer electricity
Biggish time delay in road, the range for expanding the frequency dividing of the frequency divider are more difficult.If the d type flip flop of relocking is removed to expand point
Frequency range, output clock " CKOUT1 " and " CKOUT2 " will have bigger shake, and input clock extremely exports the delay of clock
Very big variation will be generated with the variation of pressure, volume, temperature (PVT) and frequency dividing ratio.
Summary of the invention
Embodiment of the disclosure is provided including the cascade frequency dividing for removing 2 allocator module chains and two feedback relocking paths
Device.Frequency divider according to the disclosure may include three main components: except 2 paths, feedback relocking path and front-end stage.
According to one aspect of the disclosure, a kind of frequency divider is provided.The frequency divider includes: to receive input except 2 paths
Clock signal and including it is cascade it is N number of remove 2 allocator modules, wherein N be positive integer and minimum 1；And at least one feedback
Path, each feedback path include cascade N number of latch module, each latch module includes that the first receiving end and second connects
Receiving end is respectively used to receive by except the corresponding signal removed before and after 2 allocator modules in 2 paths；Each lock
Storing module further includes third receiving end, and for receiving control signal, which makes feedback path output input clock letter
Number 21、22……2NAt least one of fractional frequency signal.
According to one embodiment of the disclosure, each can be with a corresponding latch module except 2 allocator modules
Form a grade.
According to the embodiment of the disclosure, it is preferable that each latch module may include d type flip flop and multiplexing
Device, wherein multiplexer includes the second receiving end, third receiving end and for receiving the latch module from next stage
4th receiving end of signal；And d type flip flop includes the first receiving end and for the first output end to upper level output signal,
And the signal of multiplexer of the d type flip flop reception from same level-one.
According to the embodiment of the disclosure, it is further preferred that each feedback path may include output module, this is defeated
Module includes front-end stage multiplexer out, and front-end stage multiplexer includes for directly receiving input clock signal
First front-end stage receiving end, the second front-end stage receiving end coupled with the first output end of the first order control signal for receiving
Third front-end stage receiving end and front-end stage output end for output frequency division signal.
According to another embodiment of the disclosure, each latch module may include latch, logical AND gate and logic
Or door, wherein logic sum gate includes the 4th reception of third receiving end and the signal for receiving the latch module from next stage
End；Logical AND gate includes the second receiving end, and logical AND gate receives the signal of the logic sum gate from same level-one；And it latches
Device includes the first receiving end and for the first output end to upper level output signal, and latch is received from same level-one
The signal of logical AND gate.
According to the embodiment of the disclosure, it is preferable that each feedback path may include output module, the output module
Including front-end stage logical AND gate and front-end stage logic sum gate, wherein front-end stage logic sum gate includes for receiving control signal
Three front-end stage receiving ends and the second front-end stage receiving end coupled with the first output end of the first order；And front-end stage logical AND
Door include the first front-end stage receiving end for directly receiving input clock signal and with the front-end stage for output frequency division signal
Output end coupling, and front-end stage logical AND gate receives the signal from front-end stage logic sum gate.
According to the embodiment of the disclosure, it is highly preferred that output module can be further in front-end stage logical AND gate with before
Hold between grade output end includes that front-end stage removes 2 allocator modules.
According to the embodiment of the disclosure, more preferably, every level-one removes 2 allocator modules and front-end stage except 2 frequency dividings
Device module can receive reset signal to be used for so that fractional frequency signal is aligned.
According to the embodiment of the disclosure, it is further preferred that output module further can remove 2 frequency dividers in front-end stage
It include front-end stage multiplexer between front-end stage output end, which directly receives input clock letter
Number.
It may include multiple feedback paths according to the further embodiment of the disclosure, and in multiple feedback paths
It at least include buffer between a pair, with every a pair of of latch mould in every level-one in two feedback paths for coupling this pair
Block.
According to the 2 of the disclosureNFrequency divider can work compared with traditional frequency divider in higher frequency, can provide multiple
The clock output of phase alignment, and shake is maintained into reduced levels while realizing widened frequency dividing ratio range.
Detailed description of the invention
Fig. 1 depicts a kind of traditional 2NFraction frequency device；
Fig. 2 is that there are two novel the 2 of phase alignment clock output for tool according to an embodiment of the present disclosureNThe signal of frequency divider
Figure；
Fig. 3 presents 2 of the present embodiment in Fig. 2NFrequency divider to " CKIN " divided by 2 and 4 when waveform；
Fig. 4 shows the 2 of configuration according to an embodiment of the present disclosure 50% duty ratio output clockNThe signal of frequency divider
Figure；
Fig. 5 presents shown in Fig. 42NThe waveform of frequency divider；
Fig. 6 shows extended example of the tool according to an embodiment of the present disclosure there are two phase alignment clock output；
Fig. 7 shows tool according to an embodiment of the present disclosure there are two clock output and has the example of 50% duty ratio；
Fig. 8 shows the example of "/2 " module according to an embodiment of the present disclosure with function of reset；
Fig. 9 presents the example waveform of " CKOUT1 (1) " and " CKOUT1 (2) " two kinds of original states；
Figure 10, which is shown, according to an embodiment of the present disclosure improves the speed of service and driving using NAND gate and buffer
The exemplary structure of ability；And
Figure 11 shows addition multiplexer according to an embodiment of the present disclosure to provide the frequency divider of 1 frequency dividing.
Specific embodiment
According to one embodiment, Fig. 2 shows tool, there are two novel the 2 of the clock output being alignedNThe schematic diagram of frequency divider.
It except 2 paths receive input clock signal CKIN, and may include several cascade 2 allocator modules 201,202,203 of removing (in Fig. 2
In be denoted as "/2 "), should except 2 frequency divider paths by input clock signal " CKIN " divided by 2,4,8 ... 2N, herein, N is
Positive integer and minimum 1.Meanwhile each of two feedback relocking paths path may each comprise several latch modules 211,
212,213,221,222,223, and being capable of output frequency division signal.As shown in Fig. 2, latch module 211,212,213,221,222,
223 may include that d type flip flop (" DFF " is denoted as in Fig. 2) and a multiplexer MUX (are labeled in Fig. 2
For " M ").The feedback relocking path is selectively provided by multiplexer MUX by control signal (by being described below) anti-
Feeder diameter, and the feedback signal is by d type flip flop relocking.
In addition, two locks corresponding with the feedback relocking path 1 and 2 that first is coupled except 2 allocator modules 201
Storing module 211,221 removes 2 allocator modules 201 with this first can be referred to as the first order together, and cascade with the first order
The second level, the third level etc. respectively include it is respective remove 2 frequency division modules 202,203 and corresponding two latch modules 212,222,
213,223.Before every level-one is handled signal except 2 allocator modules and later, except 2 paths are connected to two
Feed back respective latch module in relocking path.Specifically, the d type flip flop in certain level-one, in each feedback relocking path
The first receiving end receive by except the signal before the processing of 2 allocator modules, and the multichannel in each feedback relocking path is multiple
It is received with the second receiving end of device by removing the signal after 2 allocator modules are handled.Each feedback relocking road in every level-one
Latch module of the multiplexer in latch module in the same path that the 4th receiving end receives its next stage in diameter
Output (as exist).In addition, the multiplexer couples and transmits a signal to d type flip flop.The d type flip flop is defeated with first
Outlet, and treated signal is exported to two stages before or front-end stage in the first output (when the d type flip flop is in first
When grade).
In this embodiment, it can have a multiplexer conduct in each feedback relocking path in front-end stage
Front-end stage multiplexer, the front-end stage multiplexer have the first front-end stage receiving end for directly receiving input clock
Signal also has the second front-end stage receiving end with the processed letter in the feedback relocking path for receiving the corresponding first order
Number and output frequency division clock signal.
Multiplexer in each grade can have third receiving end and front-end stage multiplexer can have
Three front-end stage receiving ends, be adjusted so as to the frequency dividing ratio to the feedback path for connecing suspension control signal.Each point
Frequency ratio controls signal (i.e. control signal) " C1 [N:1] " and " C2 [N:1] " and selects feedback clock signal from next stage or local level.
C [N:1] represents the control signal value from N grades to the 1st grade successively, and C [N:0] is then represented from N grades to front-end stage successively
Control signal value, the collection of such control signal value are combined into the number that a column are indicated with 0 or 1.If having selected next stage clock,
It will be latched (because local level clock frequency is higher) by local level clock, which increase time sequence allowance and reduce output clock
Shake.The clock same frequency that feedback output clock signal " FB1 " and " FB2 " have and selected by " C1 [N:1] " and " C2 [N:1] "
Rate.Frequency dividing ratio controls signal " C1 [0] " and " C2 [0] " and " CKIN " is switched to " CKOUT1 " and " CKOUT2 ".
It should be noted that although Fig. 2 illustrates only tool, there are two feedback relocking path and the particular implementations of three grades
Example, however the disclosure is not intended to limit the quantity in feedback relocking path and grade.Any disclosure that can be realized is intended to require to protect
The configuration mode of shield may be considered that be covered by the scope of the present disclosure.
Fig. 3 is 2 of the present embodiment in Fig. 2NFrequency divider to " CKIN " divided by 2 and 4 when waveform diagram.Except 2 divider units
It is triggered in the rising edge of input clock.Therefore DV2=CKIN/2, DV4=DV2/2 and DV8=DV4/2 and so on.
Frequency dividing ratio control signal " C1 [N:0] " is " 00 ... 010 " (i.e. C1 [1]=1) and " C2 [N:0] " is " 00 ... 100 " (i.e. C2
[2]=1).In this embodiment, " DV2 " is selected at " feedback relocking path 1 " feedback and " DV4 " is selected at " feedback weight
Path 2 " is locked to feed back.It is uncorrelated in the case that frequency dividing ratio controls signal " C1 [N:2] " and " C2 [N:3] "." DV4 " is at " DV2 "
Rising edge by d type flip flop output (301) be " N2 ".Signal " N1 " and the rising edge of " N2 " at " CKIN " pass through d type flip flop
It is " CKOUT1 " and " CKOUT2 " with MUX output (302).So output clock " CKOUT1 " and " CKOUT2 " will exist naturally
Rising edge aligns.Because low speed signal can by the input clock institute relocking of adjacent higher speed clock and end, the present embodiment
2NFrequency divider can work compared with traditional frequency divider in higher frequency.The frequency divider has more high scalability and is easy to cloth
Office.
In another embodiment, Fig. 4 shows the 2 of configuration 50% duty ratio output clockNFrequency divider.Similar to Fig. 2
The embodiment shown is discribed, equally has except 2 paths and feedback relocking path, and except each except 2 points on 2 paths
Latch module 411,412 on its corresponding each feedback relocking path of frequency device module 401,402 forms a grade.It can be with
The higher frequency work of one embodiment in compared with Fig. 2.It is noted, however, that although Fig. 4 is illustrated only with one
The specific embodiment of a feedback relocking path and two grades, however the disclosure is not intended to limit feedback relocking path and grade
Quantity.Any disclosure that can be realized is intended to claimed configuration mode and may be considered that covered by the scope of the present disclosure
Lid.
2 frequency dividers should be removed by input clock signal " CKIN " divided by 2,4 ... 2N.The feedback relocking path is according to control signal
Feedback path is selectively provided, and passes through latch (being denoted as " L " in Fig. 4) relocking feedback signal.In the implementation
In example, each latch module 411,412 may include a logic sum gate, a logical AND gate and a latch.It is specific and
Speech, in certain level-one, the first receiving end for feeding back the latch in relocking path, which receives, to be passed through except before the processing of 2 allocator modules
Signal, and the second receiving end for feeding back logical AND gate in relocking path receives after except the processing of 2 allocator modules
Signal.The logic sum gate in the latch module in feedback relocking path in every level-one has third receiving end to divide for receiving
Frequency ratio controls signal, also has the 4th receiving end with the latch module in the same path for receiving next stage (for example, phase
For the second level latch module 412 of first order latch module 411) output (as exist).Logic sum gate coupling and by signal
It is transmitted to logical AND gate.The logical AND gate then exports signal to latch, and the latch have the first output end with
For exporting signal to previous stage or front-end stage (when the latch is in the first order).
In this embodiment, front-end stage can have a front-end stage logic sum gate, a front-end stage logical AND gate and
One front-end stage removes 2 frequency dividers.When the front-end stage logical AND gate has the first front-end stage receiving end with for directly receiving input
Clock signal.The front-end stage logic sum gate has second of the processed signal in the feedback relocking path for receiving the first order
Front-end stage receiving end, and the front-end stage logic sum gate can have third front-end stage receiving end for connecing suspension control signal.
The front-end stage logic sum gate couples and transmits a signal to front-end stage logical AND gate.Finally, in one example, signal is in front end
Grade output end can be removed 2 frequency dividers using the front-end stage to be used for duty cycle correction to 50% before exporting.Alternatively, preceding
End grade logical AND gate can also be coupled directly with the front-end stage output end for output frequency division signal without introducing the front-end stage except 2
Frequency divider.
Frequency dividing ratio controls signal (i.e. control signal) " C [N:0] " and selects feedback clock signal from next stage or local level.
If having selected next stage clock, it will be latched by local level clock, which increase time sequence allowances, improve speed and drop
Low output clock jitter.Feedback output clock signal " FB0 " has frequency identical with selected clock.When " FB0 " in Fig. 4
Clock has " Tin/Tout " duty ratio (period that Tin and Tout are respectively CKIN and CKOUT).Front-end stage frequency divider is by " CK2X "
Divided by 2 and clock duty cycle is corrected to 50%.If the duty ratio for not requiring 50% in the design, in the front-end stage
Do not need 2NFrequency divider and directly export " FB0 " or " CKIN ".
Fig. 5 presents shown in Fig. 42NThe waveform of frequency divider.It is assumed that C [N:0]=00...100 (i.e. C [2]=1), selection
DV4 is fed back and " CK2X ", " FB0 " and " DV4 " frequency having the same." CKOUT " is " CKIN " divided by 8 and has 50%
Duty ratio.In the same manner, if C [N:0]=00...001 (i.e. C [0]=1), CKOUT=CKIN/2；If C
[N:0]=00...010 (i.e. C [1]=1), then CKOUT=CKIN/4.
Fig. 6 shows the extended example according to the tool of an embodiment of the present disclosure there are two phase alignment clock output.Two
A output clock " CKOUT1 " and " CKOUT2 " has the different frequency dividing ratios controlled by " C1 [N:0] " and " C2 [N:0] ".As " C1
[0] " when being 1, " CKIN " will be directly output to " CKOUT1 " by logical AND gate (AND).On the other hand, when " C1 [0] " is 0
When, then " FB1_0 " will to export clock " CKOUT1 " with more low jitter again by logical gate operations by " CKIN ".It can
To extend frequency dividing ratio simply by adding in " removing 2 frequency divider paths " and feedback latch module except 2 frequency dividers.Because
" CKOUT1 " and " CKOUT2 " be both selected from it is identical remove 2 allocator modules 601,602,603, they will be naturally by phase alignment
(rising and falling edges).However, in this case, exporting clock " CKOUT1 " and " CKOUT2 " duty ratio not being 50%.
Fig. 7 shows according to the tool of an embodiment of the present disclosure the example for there are two clock output and having 50% duty ratio.
Unlike example as shown in Figure 6, the example of Fig. 7 introduces respectively before two clock outputs and removes 2 allocator modules
710,720, " CK1_2X " and " CK2_2X " divided by 2 and can be corrected clock duty cycle to 50%.However, because preceding
Two in the grade of end are removed 2 allocator modules 710,720 and may be different original state, so " CKOUT1 " and " CKOUT2 " phase
Position may not be alignment.Therefore reset signal must be used to ensure that multi-clock output phase in this case is in alignment with.
In order to solve the exemplary alignment issues of Fig. 7, Fig. 8 shows the showing except 2 allocator modules with function of reset
Example.When RST signal is high, all 2 allocator modules of removing force in the state of determination output phase to be in alignment with.Fig. 9 is shown
The waveform example of the case where two kinds of original states are presented " CKOUT1 (1) " and " CKOUT1 (2) ".Export clock " CKOUT1
(2) " failing edge is aligned with " CKOUT2 ", but " CKOUT1 (1) " is not aligned therewith.Owns "/2 " unit in reset signal
The rising edge of " RST " is forced to be in low, and " CKOUT1 " and " CKOUT2 " failing edge are aligned.By in each output clock
A phase inverter (not shown) is added before, it is easy to really make to export rising edge clock alignment.
The quantity of output clock with different frequency dividing ratios can be extended by adding the quantity of feedback path.However,
Except the driving capability in 2 frequency divider paths is limited." DV2 ", " DV4 " ... clock load will be increased by adding feedback path quantity,
It reduces maximum operation frequency.Figure 10, which gives, adds buffer 1040 between feedback path to improve driving capability and work
The multi output 2 of speedNFrequency divider.Further, NAND gate (NAND) can be used to substitution or door (OR) and realize such as Fig. 8 institute
The structure of the faster speed and more small area shown.
These as Fig. 7, Fig. 8 or Figure 10 configure 2NFrequency divider needs front-end stage multiplexer to carry out bypass input clock.
As shown in figure 11, when " BP " or " BP2 " of front-end stage multiplexer 1110,1120 is when front-end module is " 1 ", in Figure 11
2 presentedNFrequency divider is by input clock divided by 1.
Pass through the introduction gone out given in above description and relevant drawings, many modifications of the disclosure described herein
It will be recognized by disclosure those skilled in the relevant art with other embodiment.Therefore, it should be understood that, the disclosure
Embodiment is not limited to disclosed specific embodiment, and modification and other embodiment are intended to be included in this
Within scope of disclosure.In addition, although above description and relevant drawings are in certain example combination forms of component and/or function
Example embodiment is described under background, it will be appreciated that, component can be provided by alternate embodiment
And/or the different combinations of function are without departing from the scope of the present disclosure.On this point, for example, with explicitly described above
Other combining forms of different component and/or function be also expected within the scope of the present disclosure.Although here
Using concrete term, but they are only used with general and descriptive meaning and are not intended to and are limited.
Claims (8)
1. a kind of frequency divider, comprising:
Except 2 paths, receive input clock signal and including it is cascade it is N number of remove 2 allocator modules, wherein N is positive integer and most
Small is 1；And
At least one feedback path, each at least one described feedback path includes cascade N number of latch module, each institute
Stating N number of latch module includes the first receiving end and the second receiving end, is respectively used to receive by described except corresponding in 2 paths
Except the signal before and after 2 allocator modules；
Each described described N number of latch module further includes third receiving end, and for receiving control signal, the control signal makes
It obtains at least one described feedback path and exports the 2 of the input clock signal1、22……2NAt least one of fractional frequency signal；
Wherein each described N number of removes 2 allocator modules and the corresponding one N number of latch module forms a grade；
Wherein each described N number of latch module includes d type flip flop and multiplexer, wherein the multiplexer includes institute
State the second receiving end, the third receiving end and the signal for receiving the latch module from next stage the 4th receives
End；And
The d type flip flop includes first receiving end and for the first output end to upper level output signal, and the D
The signal of the multiplexer of the trigger reception from same level-one.
2. frequency divider according to claim 1, wherein each at least one described feedback path includes output module, institute
Stating output module includes front-end stage multiplexer, and the front-end stage multiplexer includes described defeated for directly receiving
The the first front-end stage receiving end for entering clock signal, the second front-end stage receiving end coupled with first output end of the first order,
Front-end stage output for receiving the third front-end stage receiving end of the control signal and for exporting the fractional frequency signal
End.
3. frequency divider according to claim 1, wherein each described N number of latch module includes latch, logical AND gate
And logic sum gate, wherein
The logic sum gate includes the 4 of the third receiving end and the signal for receiving the latch module from next stage
Receiving end；
The logical AND gate includes second receiving end, and the logical AND gate receive the logic from same level-one or
The signal of door；And
The latch includes first receiving end and for the first output end to upper level output signal, and the lock
The signal of the logical AND gate of the storage reception from same level-one.
4. frequency divider according to claim 3, wherein each at least one described feedback path includes output module, institute
Stating output module includes front-end stage logical AND gate and front-end stage logic sum gate, wherein
The front-end stage logic sum gate includes the third front-end stage receiving end and and the first order for receiving the control signal
First output end coupling the second front-end stage receiving end；And
The front-end stage logical AND gate include the first front-end stage receiving end for directly receiving the input clock signal and with
Front-end stage output end for exporting the fractional frequency signal couples, and the front-end stage logical AND gate receives and comes from the front end
The signal of grade logic sum gate.
5. frequency divider according to claim 4, wherein the output module further the front-end stage logical AND gate with
It include that front-end stage removes 2 allocator modules between the front-end stage output end.
6. frequency divider according to claim 5, wherein every level-one removes 2 allocator modules and front-end stage except 2 frequency dividers
Module receives reset signal to be used for so that the fractional frequency signal is aligned.
7. frequency divider according to claim 6, wherein the output module further the front-end stage except 2 frequency dividers with
It include front-end stage multiplexer between the front-end stage output end, the front-end stage multiplexer directly receives the input
Clock signal.
8. frequency divider according to any one of the preceding claims, including multiple feedback paths, and the multiple anti-
It include buffer between at least a pair in feeder diameter, for coupling in every level-one in described pair of two feedback paths
Every a pair of latch module.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201361915706P | 2013-12-13 | 2013-12-13 | |
| US61/915,706 | 2013-12-13 |
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| CN105375917A CN105375917A (en) | 2016-03-02 |
| CN105375917B true CN105375917B (en) | 2019-01-29 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10303200B2 (en) * | 2017-02-24 | 2019-05-28 | Advanced Micro Devices, Inc. | Clock divider device and methods thereof |
| US20190379359A1 (en) * | 2018-06-08 | 2019-12-12 | Nxp B.V. | Frequency division circuitry and methods |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102959866A (en) * | 2010-07-01 | 2013-03-06 | 高通股份有限公司 | Parallel path frequency divider circuit |
| CN103026623A (en) * | 2010-07-27 | 2013-04-03 | 飞思卡尔半导体公司 | Latch circuit, flip-flop circuit and frequency divider |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100719310B1 (en) * | 2005-09-23 | 2007-05-17 | 한국과학기술원 | SET/RESET latch circuit, schmitt trigger circuit and ?-type flip flop circuit based on MOBILE and frequency divider circuit using SET/RESET latch circuit |
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2014
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102959866A (en) * | 2010-07-01 | 2013-03-06 | 高通股份有限公司 | Parallel path frequency divider circuit |
| CN103026623A (en) * | 2010-07-27 | 2013-04-03 | 飞思卡尔半导体公司 | Latch circuit, flip-flop circuit and frequency divider |
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| CN105375917A (en) | 2016-03-02 |
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