CN105355614A - Pre-packaging single chip and preparation process thereof - Google Patents

Pre-packaging single chip and preparation process thereof Download PDF

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Publication number
CN105355614A
CN105355614A CN201510835539.3A CN201510835539A CN105355614A CN 105355614 A CN105355614 A CN 105355614A CN 201510835539 A CN201510835539 A CN 201510835539A CN 105355614 A CN105355614 A CN 105355614A
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chip
packaged
packaged single
pin
molybdenum sheet
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CN201510835539.3A
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CN105355614B (en
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刘文广
温家良
张朋
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State Grid Corp of China SGCC
Smart Grid Research Institute of SGCC
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State Grid Corp of China SGCC
Smart Grid Research Institute of SGCC
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

The invention provides a pre-packaging single chip and a preparation process thereof. The pre-packaging single chip comprises a shell, a large molybdenum plate and a small molybdenum plate positioned at two sides of a chip, and bonding wires and pins arranged at side surfaces of the chip. The preparation process of the pre-packaging single chip includes following steps: 1) the chip is connected with the large molybdenum plate and the small molybdenum plate arranged at two sides in a sintering or welding manner, 2) a grid electrode and an emitter electrode of the chip are provided with the bonding wires connected with the pins in a corresponding manner; and 3) packaging is realized. According to the pre-packaging single chip, performance tests can be conveniently conducted, the pollution and damage to the chip by the environment are avoided, the performance of the chip is not affected, the qualified pre-packaging chip after the test can be assembled to a high-power device by directly employing a crimping or welding manner, and standardized production is facilitated.

Description

A kind of pre-packaged single-chip and preparation technology thereof
Technical field
The present invention relates to power semiconductor device technical field, be specifically related to a kind of pre-packaged single-chip and preparation technology thereof.
Background technology
The compression joint type IGBT (insulated gate bipolar transistor) that industry, information, new forms of energy, medical science, traffic, military affairs and aviation field are applied has higher reliability because of it, be convenient to series connection, and show short circuit failure mode when device failure, be also widely used in the fields such as intelligent grid.
The impact of temperature on device performance is most important, and high temperature not only can affect the electrology characteristic of device, more can have a strong impact on its fatigue life.In device running, temperature can affect the thermal stress of chip internal, this may cause the damage of chip, there are some researches prove that the fatigue life of electronic device exponentially declines with the rising of temperature, therefore must consider thermal design in device layout process simultaneously, to facilitate heat to shed rapidly, reduce the temperature of chip.
Existing main flow compression joint type IGBT is two kinds of products that ABB AB and WESTCODE company produce respectively, and its feature is respectively:
The compression joint type IGBT structure chips downside of ABB AB and substrate are sintered together, opposite side is crimping structure, and contact with upper end cover eventually through folded spring structure, but also just because of the existence of folded spring, make the capacity of heat transmission of chip upper side very poor, heat can only be derived by downside substantially, is unfavorable for heat radiation.
The compression joint type IGBT structure of WESTCODE company has multiple module, realizes big current and high-power by the mode of the multiple module of parallel connection.Each module chips upper and lower sides two sides is crimping structure, until upper and lower end cap, the advantage of this structure is that chip can realize two-side radiation, and chip upper and lower surface has intimate equal heat to derive.But the contact aspect between parts is more, because the Contact of different interface is not intact, be mixed into air in gap, the thermal conductivity of air is lower, can cause very large contact heat resistance like this.According to the literature, contact heat resistance accounts for 20%-50% proportion in overall thermal resistance, so the thermal resistance of this kind of structural entity thermal resistance and ABB is more or less the same.
In addition, realize the big current of power device and high-power, must by the mode of multiple chip in parallel, and need before chip parallel connection to carry out performance test to it, in existing structure, before integral device encapsulation, chip is all exposed in the middle of air, carries out unavoidably polluting chip or damaging in test process to it.
Summary of the invention
The object of this invention is to provide a kind of pre-packaged single-chip and preparation technology thereof, for the deficiencies in the prior art, chip is after pre-packaged, carry out performance test to it again, just avoid pollution and damage that environment causes chip, the multiple chips after pre-packaged are connected by drive plate, then overall package, the integrated of chip and driving can be realized better, to reduce under operating state each chip by the otherness of electric current, thus the better overall performance playing device.
To achieve these goals, the present invention takes following technical scheme:
A kind of pre-packaged single-chip, described pre-packaged single-chip comprises shell, is positioned at the size molybdenum sheet on chip two sides, the key of its side and line and pin.
First preferred version of described pre-packaged single-chip, described key and line are the line that pin corresponding with the grid on chip and emitter is respectively connected.
Second preferred version of described pre-packaged single-chip, the grid on described chip is directly connected with pin with emitter.
3rd preferred version of described pre-packaged single-chip, described sheathing material is engineering plastics.
4th preferred version of described pre-packaged single-chip, the pin exposed of described pre-packaged chip, size molybdenum sheet part exposes.
5th preferred version of described pre-packaged single-chip, described size molybdenum sheet comparatively case surface height 0.5mm respectively.
A kind of preparation technology of described pre-packaged single-chip comprises the steps:
1) be connected with the size molybdenum sheet sintered or chip and two sides arrange by welding manner respectively;
2) grid of chip arranges the bonding line that be connected corresponding to pin respectively with on emitter;
3) encapsulate.
First optimal technical scheme of the preparation technology of described pre-packaged single-chip, described step 2) grid of chip and emitter arrange pin respectively.
The described application of pre-packaged single-chip in device package.
With immediate prior art ratio, the present invention has following beneficial effect:
1) pre-packaged single-chip of the present invention can carry out performance test easily, avoid pollution and damage that environment causes chip, and can not impact its performance, pre-packaged chip qualified after tested can directly adopt the mode of crimping or welding to be assembled into high power device, is convenient to standardized production;
2) pre-package structure of the present invention is convenient to chip and is connected with drive plate, can realize the driving in multi-chip situation better, reduces the otherness of each chip current distribution in high power device, thus the ability to work of effective boost device;
3) pre-packaged chip upper and lower surface sintering, reduces thermal-conduction resistance, simultaneously because chip and molybdenum plate direct sintering, and both similar thermal expansion coefficient, thermal stress reduces, and increases operational reliability;
4) the present invention is equally applicable to the encapsulation of diode.
Accompanying drawing explanation
Fig. 1: single chip architecture figure of the present invention;
Fig. 2: single-chip vertical view of the present invention;
Fig. 3: single-chip end view of the present invention;
Fig. 4: the pre-packaged single chip architecture figure of the present invention;
Fig. 5: the pre-packaged single-chip vertical view of the present invention;
Fig. 6: the pre-packaged single-chip end view of the present invention;
Fig. 7: single chip architecture figure of the present invention (substituting bonding line and pin with long pin);
Fig. 8: the pre-packaged chip application of the present invention is in the structure chart of device;
Wherein: 1 large molybdenum sheet; 2 chips; 3 little molybdenum sheets; 4 keys and line; 5 pins; 6 shells; 7 long pins; 8 pre-packaged chips; 9 device upper end covers; 10 device outer cases; 11 device bottom end covers; 12 drive plates.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in detail.Described embodiment is exemplary, is intended to for explaining the present invention, and can not be interpreted as limitation of the present invention.
Embodiment 1
A kind of pre-packaged single-chip, described pre-packaged single-chip comprises large molybdenum sheet, igbt chip and the little molybdenum sheet that lamination from bottom to up distributes, and the side key corresponding with igbt chip grid and emitter and line and pin, as shown in Figure 1, Figure 2 and Figure 3, finally by the package casing of engineering plastics by pre-packaged for chip entirety, wherein pin exposed and large and small molybdenum sheet part expose, and large and small molybdenum sheet comparatively case surface exceeds 0.5mm, as shown in Figure 4, Figure 5 and Figure 6.
The preparation technology of pre-packaged single-chip comprises the steps:
1) sintering connects chip and the large and small molybdenum sheet in two sides;
2) grid of chip and emitter arrange key and line respectively, and connect with corresponding pin;
3) encapsulate.
Chip after pre-packaged is connected with drive plate after performance test is qualified, then package power device, and chip connects as shown in Figure 8.Technique wherein by welding between large and small molybdenum sheet with device end cap realizes being connected, and pre-packaged chip pin and drive plate are by being welded to connect.
Embodiment 2
A kind of pre-packaged single-chip, described pre-packaged single-chip comprises large molybdenum sheet, igbt chip and the little molybdenum sheet that lamination from bottom to up distributes, and side and igbt chip grid and emitter corresponding pin, as shown in Figure 7, finally by the package casing of engineering plastics by pre-packaged for chip entirety, wherein pin exposed and large and small molybdenum sheet part expose, and large and small molybdenum sheet comparatively case surface exceeds 0.5mm.
The preparation technology of pre-packaged single-chip comprises the steps:
1) sintering connects chip and the large and small molybdenum sheet in two sides;
2) grid of chip and emitter arrange pin respectively;
3) encapsulate.
Chip after pre-packaged is connected with drive plate after performance test is qualified, and encapsulation power device as shown in Figure 8, sinter between large and small molybdenum sheet wherein and device end cap, pre-packaged chip pin is connected in contact pin mode with drive plate.
Above embodiment is only in order to illustrate that technical scheme of the present invention is not intended to limit; those of ordinary skill in the field are to be understood that; can modify to the specific embodiment of the present invention with reference to above-described embodiment or equivalent to replace, these do not depart from any amendment of spirit and scope of the invention or equivalently to replace within the claims that all awaits the reply in application.

Claims (9)

1. a pre-packaged single-chip, is characterized in that, described pre-packaged single-chip comprises shell, is positioned at the size molybdenum sheet on chip two sides, the key of its side and line and pin.
2. pre-packaged single-chip according to claim 1, is characterized in that, described key and line are the line that pin corresponding with the grid on chip and emitter is respectively connected.
3. pre-packaged single-chip according to claim 2, is characterized in that, the grid on described chip is connected with pin with emitter.
4. pre-packaged single-chip according to claim 1, is characterized in that, described sheathing material is engineering plastics.
5. pre-packaged single-chip according to claim 1, is characterized in that, the pin exposed of described pre-packaged chip, and size molybdenum sheet part exposes.
6. pre-packaged single-chip according to claim 5, is characterized in that, described size molybdenum sheet comparatively case surface height 0.5mm respectively.
7. a preparation technology for pre-packaged single-chip according to claim 1, is characterized in that, described preparation technology comprises the steps:
1) be connected with the size molybdenum sheet sintered or chip and two sides arrange by welding manner respectively;
2) grid of chip arranges the bonding line that be connected corresponding to pin respectively with on emitter;
3) encapsulate.
8. the preparation technology of pre-packaged single-chip according to claim 7, is characterized in that, described step 2) grid of chip and emitter arrange pin respectively.
9. the application of pre-packaged single-chip according to claim 7 in device package.
CN201510835539.3A 2015-11-26 2015-11-26 Pre-packaged single chip and preparation process thereof Active CN105355614B (en)

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Cited By (1)

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Publication number Priority date Publication date Assignee Title
CN109524291A (en) * 2017-09-18 2019-03-26 株洲中车时代电气股份有限公司 A kind of production method and tooling for power electronics unit

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CN102194865A (en) * 2011-05-11 2011-09-21 江阴市赛英电子有限公司 High-power insulated gate bipolar translator (IGBT) flat pressed and connected packaging structure
CN202025761U (en) * 2011-05-04 2011-11-02 锦州市锦利电器有限公司 Crimping type controlled silicon chip structure
CN105070700A (en) * 2015-08-09 2015-11-18 广东百圳君耀电子有限公司 Fabrication and package methods of high-efficiency heat-conduction semiconductor chip
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US20030132511A1 (en) * 2002-01-16 2003-07-17 Gerbsch Erich William Electrically isolated and thermally conductive double-sided pre-packaged component
CN2569299Y (en) * 2002-09-19 2003-08-27 张溪 Power type electronic element chip
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