CN105336678A - Formation method for interconnecting structure - Google Patents
Formation method for interconnecting structure Download PDFInfo
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- CN105336678A CN105336678A CN201410381338.6A CN201410381338A CN105336678A CN 105336678 A CN105336678 A CN 105336678A CN 201410381338 A CN201410381338 A CN 201410381338A CN 105336678 A CN105336678 A CN 105336678A
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Abstract
The invention provides a formation method for an interconnecting structure. The formation method comprises the steps of forming a dielectric layer on a semiconductor substrate; and then forming a silicon oxide masking layer on the dielectric layer for forming a hard mask, wherein the step of forming the silicon oxide masking layer is carried out by the steps of forming a tetraethyl orthosilicate layer on the dielectric layer firstly; then performing oxygen plasma processing on the tetraethyl orthosilicate layer to enable the oxygen plasma to react with the tetraethyl orthosilicate layer to form the silicon oxide masking layer. The carbon content in the silicon oxide layer formed by the technology is obviously reduced, so that the shortcoming that the consume rate of the silicon oxide masking layer is obviously less than that of the dielectric layer caused by the carbon atoms in a cleaning process for the through holes by a wet method after the through holes are formed by the subsequent dielectric layer is overcame, the flatness of the overall side wall of the openings formed in the hard mask and the through holes in the dielectric layer is effectively improved, therefore, the filling performance of the conductive materials subsequently filled to the through holes is improved, and the performance of a formed conductive plug is further improved.
Description
Technical field
The present invention relates to technical field of semiconductors, especially relate to a kind of formation method of interconnection structure.
Background technology
Along with semiconductor technology evolves, the integrated level of semiconductor device constantly increases, and feature sizes of semiconductor devices (CriticalDimension, CD) is more and more less.
And along with the reduction gradually of feature sizes of semiconductor devices, it is increasing that the RC of interconnection structure postpones the impact of (RCdelay) problem on semiconductor device.The K value reducing interconnection structure dielectric layer material effectively reduces the method for RC late effect.In recent years, at the back segment preparation technology (BackEndofTheLine of semiconductor device, BEOL) in, low-K dielectric constant (LowK, LK) material (K < 3) and ultralow K dielectric constant (UltraLowK, ULK) material becomes the mainstay material of dielectric layer gradually, and along with semiconductor device development demand, the K value of the dielectric layer material adopted constantly reduces.
Fig. 1 and Fig. 2 is the formation process schematic diagram of existing interconnection structure, and the formation process of interconnection structure comprises:
Shown in figure 1, after forming dielectric layer 11 on the substrate 10, described dielectric layer 11 forms low-K dielectric mask layer 12 according to this, with tetraethyl orthosilicate (Tetraethyl0rthosilicate, TEOS) be silicon oxide layer 13 that reacting gas (TEOS-based) is formed, and metallic mask layer 14 (as taken titanium nitride as material), after etching described low-K dielectric mask layer 12, silicon oxide layer 13 and metallic mask layer 14 form hard mask 15, with described hard mask 15 for dielectric layer described in mask etching 11 forms through hole 16.
Then with reference to shown in figure 2, described hard mask 15 forms conductive material layer 17, described conductive material layer 17 fills full described through hole 16, thus forms conductive plunger in dielectric layer 11.
But find that in actual mechanical process the poor-performing of the conductive plunger formed by prior art cannot meet the demand for development of semiconductor technology, how improving conductive plunger performance is the problem that those skilled in the art need solution badly for this reason.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of interconnection structure, to improve the performance of the conductive plunger be formed in dielectric layer.
For solving the problem, the formation method of interconnection structure provided by the invention comprises:
Substrate is provided;
Form dielectric layer on the substrate;
Described dielectric layer is formed tetraethyl orthosilicate layer;
Carry out oxygen plasma treatment to described tetraethyl orthosilicate layer, described oxygen plasma and described tetraethyl orthosilicate layer react and form silicon oxide mask layer;
Described silicon oxide mask layer forms metallic mask layer;
Etch described metallic mask layer and silicon oxide mask layer, form hard mask;
With described hard mask for dielectric layer described in mask etching, in described dielectric layer, form through hole;
Filled conductive material in described through hole, to form conductive plunger.
Alternatively, the amount of carrying out to described tetraethyl orthosilicate layer the oxygen that oxygen plasma treatment adopts is greater than the amount of the tetraethyl orthosilicate adopted when forming tetraethyl orthosilicate layer.
Alternatively, carrying out oxygen plasma treatment oxygen used with the amount of substance ratio of tetraethyl orthosilicate used during formation tetraethyl orthosilicate layer is 1:5 ~ 1:50.
Alternatively, the method forming tetraethyl orthosilicate layer is chemical vapour deposition technique.
Alternatively, the flow forming tetraethyl orthosilicate in the step of tetraethyl orthosilicate layer is less than or equal to 200mg/min.
Alternatively, the synthesis speed forming tetraethyl orthosilicate layer in the step of tetraethyl orthosilicate layer is
Alternatively, the thickness of described tetraethyl orthosilicate layer is
Alternatively, the step that described tetraethyl orthosilicate layer carries out oxygen plasma treatment is comprised: pass into the oxygen that flow is 10000 ~ 20000sccm.
Alternatively, the step forming tetraethyl orthosilicate layer comprises: air pressure is 0.1 ~ 10torr, and power is 100 ~ 5000W, and the flow of tetraethyl orthosilicate is 10 ~ 150mg/min;
Comprise the step that described tetraethyl orthosilicate layer carries out oxygen plasma treatment: air pressure is 0.1 ~ 10torr, power is 100 ~ 5000W, and the flow of oxygen is 15000 ~ 20000sccm.
Alternatively, before the described metallic mask layer of formation, the formation method of described interconnection structure comprises:
Repeat the step forming described tetraethyl orthosilicate layer and described tetraethyl orthosilicate layer is carried out to oxygen plasma treatment, to form silicon oxide mask layer.
Alternatively, step 1 ~ 6 time forming tetraethyl orthosilicate layer and carry out oxygen plasma treatment are performed, to form silicon oxide mask layer.
Alternatively, oxygen plasma treatment is carried out to described tetraethyl orthosilicate layer, comprises with the step forming silicon oxide mask layer: the content forming carbon atom is less than or equal to 1.0 × 10
18the silicon oxide mask layer of individual atoms per cubic centimeter.
Alternatively, form through hole in described dielectric layer after, in described through hole before filled conductive material, the formation method of described interconnection structure also comprises carries out wet clean step to through hole.
Alternatively, before described dielectric layer is formed silicon oxide mask layer, the formation method of described interconnection structure is also included on described dielectric layer and forms low-K dielectric mask layer, and the K value of described low-K dielectric mask layer is less than or equal to 3;
Etch described metallic mask layer and silicon oxide mask layer, the step forming hard mask comprises:
Etch described metallic mask layer, silicon oxide mask layer and low-K dielectric mask layer, to form hard mask.
Compared with prior art, technical scheme of the present invention has the following advantages:
After formation dielectric layer, the step that dielectric layer is formed silicon oxide mask layer comprises, first on dielectric layer, form tetraethyl orthosilicate layer, afterwards oxygen plasma treatment is carried out to described tetraethyl orthosilicate layer, oxygen plasma and tetraethyl orthosilicate layer are reacted, forms silicon oxide layer.Compared in prior art based on tetraethyl orthosilicate formed silicon oxide layer, the present invention first forms tetraethyl orthosilicate layer, afterwards with tetraethyl orthosilicate layer described in oxygen plasma treatment, tetraethyl orthosilicate and oxygen plasma precursor reactant is made to form silica, the carbon atom of oxygen plasma more easily and in tetraethyl orthosilicate layer reacts and forms carbon dioxide (or carbon monoxide) simultaneously, thus the carbon atom shifted in original tetraethyl orthosilicate layer, carbon content in the silica that effective reduction is formed, thus at subsequent etching silicon oxide layer, dielectric layer and form through hole in dielectric layer after, in the process of wet-cleaned through hole, effective alleviation makes the wear rate of silicon oxide mask layer be significantly less than the phenomenon of dielectric layer because of carbon atom, improve the wear rate of silicon oxide mask layer, make the wear rate of silicon oxide mask layer and dielectric layer close, and then the bump defects easily occurred at dielectric layer through-hole side wall can be reduced, the through-hole side wall entirety in the opening of described hard mask and dielectric layer is made to have good evenness, effectively can improve the filling capacity of follow-up electric conducting material of filling in described through hole, to improve the performance of the conductive plunger of follow-up formation.
Accompanying drawing explanation
Fig. 1 and Fig. 2 is the structural representation of a kind of conductive plunger of prior art formation method;
Fig. 3 is the semiconductor device schematic diagram of existing conductive plunger formation method after etch media layer forms through hole;
Fig. 4 ~ Figure 15 is the structural representation of formation method one embodiment of interconnection structure of the present invention;
Figure 16 and 17 is structural representations of another embodiment of formation method of interconnection structure of the present invention.
Embodiment
As stated in the Background Art, in the last part technology of existing semiconductor device, the poor-performing of the conductive plunger formed in dielectric layer.Analyze its reason, shown in figure 3, etch media layer is to be formed in the technique of through hole, and the hard mask 15 on dielectric layer comprises low-K dielectric mask layer 12, take tetraethyl orthosilicate as the silicon oxide layer 13 that formed of reacting gas (TEOS-based) and metallic mask layer 14.Wherein, through hole is formed at etch media layer, and in the process of follow-up cleaning through hole, silicon oxide layer 13 above through hole 16 inwall easily in described dielectric layer 11 forms protruding 18, follow-up in through hole during filled conductive material, described protruding 18 filling effects affecting electric conducting material, form the defects such as space in the electric conducting material in through hole 16, and then affect the performance of conductive plunger of follow-up formation.
Further analysis etch media layer forms protruding reason: all can doped with the carbon atom of high level in the silica that existing employing tetraethyl orthosilicate is formed, the hardness that carbon atom improves silica and the difficulty be etched, therefore at etch media layer and carry out in the process of wet-cleaned through hole, carbon atom in silicon oxide layer 13 can reduce the wear rate of silicon oxide layer 13, the consumption of silicon oxide layer 13 is made to be significantly less than the consumption of the metallic mask layer 14 above oxide layer 13, also be less than the consumption of low-K dielectric mask layer 12 below silicon oxide layer 13 and dielectric layer 11, thus form protruding 18 in silicon oxide layer 13 position because silicon oxide layer 13 consumption is less.
For this reason, the invention provides a kind of formation method of interconnection structure, comprising:
After forming dielectric layer on a semiconductor substrate, described dielectric layer forms silicon oxide layer, the forming step of described silicon oxide layer comprises: first on dielectric layer, form tetraethyl orthosilicate layer, afterwards, oxygen plasma treatment is carried out to described tetraethyl orthosilicate layer, oxygen plasma and described tetraethyl orthosilicate layer are reacted, to form silicon oxide mask layer; Afterwards, described silicon oxide layer forms metallic mask layer, and etch described metallic mask layer and silicon oxide layer forms hard mask, and with described hard mask for mask etching dielectric layer, form through hole in dielectric layer after, filled conductive material in through hole, to form conductive plunger.
Compared in prior art based on tetraethyl orthosilicate formed silicon oxide layer, the present invention first forms tetraethyl orthosilicate layer, afterwards with tetraethyl orthosilicate layer described in oxygen plasma treatment, tetraethyl orthosilicate layer and oxygen plasma precursor reactant is made to form silica, the carbon atom of oxygen plasma more easily and in tetraethyl orthosilicate layer reacts and forms carbon dioxide (or carbon monoxide) simultaneously, shift the carbon atom in original tetraethyl orthosilicate layer, thus the carbon content effectively reduced in the silica formed, and then in subsequent etching, in silicon oxide layer and dielectric layer process, and formed in the process of the wet-cleaned through hole after through hole in dielectric layer, alleviating makes the wear rate of silicon oxide mask layer be significantly less than the phenomenon of dielectric layer because of carbon atom, improve the wear rate of silicon oxide mask layer, make the wear rate of silicon oxide mask layer and dielectric layer close, effective improvement is formed at the evenness of the opening in described hard mask and the through-hole side wall entirety in dielectric layer, and then improve the filling capacity of follow-up electric conducting material of filling in described through hole, to improve the performance of the conductive plunger formed.
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Embodiment 1
Fig. 4 ~ Figure 15 is the structural representation of formation method one embodiment of interconnection structure of the present invention.
The formation method of the interconnection structure that the present embodiment provides comprises:
Shown in first reference diagram 4, provide substrate 20.
In the present embodiment, described substrate 20 comprises: Semiconductor substrate.Or described substrate 20 comprises Semiconductor substrate and is formed in Semiconductor substrate or the semiconductor components and devices of semiconductor substrate surface.
Described Semiconductor substrate is silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator (SOI) substrate, germanium on insulator (GOI) substrate, glass substrate or other III-V substrates, and described semiconductor substrate materials does not limit protection scope of the present invention.
Described substrate 20 is formed the first insulating barrier 21 and the second insulating barrier 22 according to this.
In the present embodiment, described first insulating barrier 21 can be used as diffusion impervious layer, follow-up formation dielectric layer, and form interconnection structure in dielectric layer after, described first insulating barrier 21 can suppress the metallic atom in interconnection structure to spread in semiconductor base.
The material of described first insulating barrier 21 is the silica (NDC) of nitrating, and the material of described second insulating barrier 22 is low-K dielectric material, as the silica (SiOCH) of carbon dope (C) and hydrogen (H).The formation process of described first insulating barrier 21 and the second insulating barrier 22 is chemical vapour deposition (CVD) (ChemicalVaporDeposition, CVD).
Low-K dielectric material mostly is based on existing dielectric layer, poor with NDC material adhesion, described first insulating barrier 21 is formed by the second insulating barrier 22 of low-K dielectric material, for improving the bond strength between the first insulating barrier 21 and the dielectric layer of follow-up formation.
Afterwards, described second insulating barrier 21 forms dielectric layer 23.
In the present embodiment, the material of described dielectric layer 23 is low-K dielectric material (K value is less than 3) or ultralow K dielectric material (K value is less than 2.6).Follow-uply formed after interconnection structure in described dielectric layer 23, low-K dielectric material can effectively reduce the parasitic capacitance of interconnection structure, thus reduces RC delays (RCDelay) effect occurred when signal transmits in interconnection structure.
Alternatively, in the present embodiment, described dielectric layer 23 adopts ultralow K dielectric material, as the silica of the carbon dope of loose structure.
In conjunction with reference to figure 5 ~ Figure 10, described dielectric layer 23 forms layer of hard mask material, etch described layer of hard mask material afterwards and form hard mask.Described layer of hard mask material comprises silicon oxide mask layer 26, and is positioned at the metallic mask layer on described silicon oxide mask layer 26.
Particularly, as shown in Figure 5, in the present embodiment, described layer of hard mask material also comprises low-K dielectric mask layer.Before form silicon oxide mask layer 26 on described dielectric layer 23, the formation method of described interconnection structure also comprises: on described dielectric layer 23, form low-K dielectric material layer, in order to form low-K dielectric mask layer 24, the material of described low-K dielectric mask layer is low-K dielectric material.The follow-up adhesion improving described dielectric layer 23 and silicon oxide mask 26 of described low-K dielectric mask layer.
In conjunction with reference to figure 5 and Fig. 6, in the present embodiment, the formation process of described silicon oxide mask layer 26 comprises:
First on described low-K dielectric material layer 24, form the first tetraethyl orthosilicate layer (TEOS layer) 251, again oxygen plasma treatment is carried out to described first tetraethyl orthosilicate layer 251 afterwards, oxygen plasma and described first tetraethyl orthosilicate layer 251 are reacted, to form the first silicon oxide mask layer 261.
Tetraethyl orthosilicate and oxygen is directly passed into compared to existing, make oxygen and tetraethyl orthosilicate reaction with the method forming silica, in the present invention, first form the first tetraethyl orthosilicate layer, afterwards oxygen plasma treatment technique is carried out to described first tetraethyl orthosilicate layer, tetraethyl orthosilicate and oxygen plasma precursor reactant form silica, oxygen plasma also reacts with the carbon atom in tetraethyl orthosilicate layer and forms carbon dioxide (or carbon monoxide) simultaneously, shift the carbon atom in original tetraethyl orthosilicate layer, carbon content in the first silicon oxide mask layer 261 that effective reduction is formed.
In the present embodiment, the formation process of described first tetraethyl orthosilicate layer 251 is chemical vapour deposition (CVD) (ChemicalVaporDeposition, CVD).
If described first tetraethyl orthosilicate layer 251 is blocked up, be unfavorable for that follow-up oxygen plasma and the first tetraethyl orthosilicate layer 251 react.In the present embodiment, the thickness of described first tetraethyl orthosilicate layer 251 is
In addition, in the first tetraethyl orthosilicate layer 251 forming process, if the flow of the tetraethyl orthosilicate passed into is excessive, synthesis speed is too fast, be unfavorable for the THICKNESS CONTROL of the first tetraethyl orthosilicate layer 251, also can reduce the uniformity of the first tetraethyl orthosilicate layer 251 each several part thickness of formation simultaneously.The flow of tetraethyl orthosilicate is less than or equal to 200mg/min.
In the present embodiment, the concrete technological parameter forming the first tetraethyl orthosilicate layer 251 comprises: control air pressure is 0.1 ~ 10torr, and power is 100 ~ 5000W, and the flow of tetraethyl orthosilicate is 10 ~ 150mg/min.
In the present embodiment, the synthesis speed of described first tetraethyl orthosilicate layer 251 is chosen as
can ensure that the first tetraethyl orthosilicate layer 251 has comparatively uniform thickness.
In the present embodiment, the amount of the first tetraethyl orthosilicate that the amount of carrying out the oxygen that oxygen plasma treatment adopts to described first tetraethyl orthosilicate layer 251 adopts when being greater than formation first tetraethyl orthosilicate layer 251, thus provide enough oxygen plasmas and the first tetraethyl orthosilicate layer fully to react, thus reduce the carbon content in the silicon oxide mask layer of follow-up formation.
Alternatively, described first tetraethyl orthosilicate layer being carried out to the volume of oxygen plasma treatment oxygen used, is 5:1 ~ 50:1 with the amount of substance ratio (mol ratio) of 251 tetraethyl orthosilicate used during formation first tetraethyl orthosilicate layer.
In the present embodiment, the concrete technology that described first tetraethyl orthosilicate layer carries out oxygen plasma treatment is comprised: in plasma producing apparatus, pass into oxygen, it is 100 ~ 5000W that power controls, the flow of oxygen is 10000 ~ 20000sccm, is chosen as 15000 ~ 20000sccm further.
In the present embodiment, in the first silicon oxide mask layer 26 formed by above-mentioned technique, the content of carbon atom is less than or equal to 1.0 × 10
18individual atoms per cubic centimeter.
Alternatively, shown in figure 7, after the described first silicon oxide mask layer 261 of formation, repeat the technique of above-mentioned formation first tetraethyl orthosilicate layer 251, described first silicon oxide mask layer 261 forms the second tetraethyl orthosilicate layer 252; Afterwards, shown in figure 8, again carry out oxygen plasma treatment technique, make described second tetraethyl orthosilicate layer 252 with oxygen plasma precursor reactant to form silicon oxide mask layer 262.
The formation process of described second tetraethyl orthosilicate layer 252, and follow-up employing oxygen plasma treatment technique makes described second tetraethyl orthosilicate layer 252 and oxygen plasma precursor reactant form the technique of silica, resemble process with above-mentioned first tetraethyl orthosilicate layer 251 and the first silicon oxide mask layer 261, does not repeat them here.
Shown in figure 9, after the described silicon oxide mask layer 262 of formation, on described silicon oxide mask layer 262, form the 3rd tetraethyl orthosilicate layer again, and oxygen plasma treatment technique is carried out to described 3rd tetraethyl orthosilicate layer, form the 3rd silicon oxide mask layer 263.
In the present embodiment, described first silicon oxide mask layer 261, silicon oxide mask layer 262 and the 3rd silicon oxide mask layer 263 form final silicon oxide mask layer 26.
It should be noted that, in other embodiments except the present embodiment, by repeating above-mentioned first formation tetraethyl orthosilicate layer and carrying out the step 2 time of oxygen plasma treatment, or be greater than 3 times, thus superposition forms the silica of sandwich construction, form the suitable silicon oxide mask layer 26 of thickness until final.The tetraethyl orthosilicate layer of so each formation thinner thickness, makes in follow-up oxygen plasma treatment technique, and oxygen fully can react with the tetraethyl orthosilicate layer of thinner thickness, to improve the performance of the final silicon oxide mask layer 26 formed.Alternatively, step 2 ~ 6 time forming tetraethyl orthosilicate layer and carry out oxygen plasma treatment can be performed, thus form the silicon oxide mask layer of 2 ~ 6 Rotating fields.
In the present embodiment, alternatively, the thickness of the final silicon oxide mask layer 26 formed is
Then with reference to shown in Figure 10, after the described silicon oxide mask layer 26 of formation, described silicon oxide mask layer 26 forms metallic mask layer 27.
In the present embodiment, described metallic mask layer 27 is titanium nitride (TiN) layer, and formation process is CVD.
In conjunction with reference to shown in Figure 11, described metallic mask layer 27 forms photoresist mask 25, and with described photoresist mask 25 be metallic mask layer described in mask etching 27, silicon oxide mask layer 26 and low-K dielectric material layer 24, form hard mask.Described hard mask comprises metallic mask layer 271, silicon oxide mask layer 36 and low-K dielectric material layer 241 after etching.
In the present embodiment, the technique etching described metal mask material layer 24, silicon oxide mask layer 26 and low-K dielectric material layer 24 is dry etching.Described dry etch process specifically can with carbon tetrafluoride (CF4) and hydrogen (H
2) mist be dry etching agent.
Then with reference to shown in Figure 12, with described hard mask for dielectric layer described in mask etching 23, first insulating barrier 21 and the second insulating barrier 22, in described dielectric layer 23, form through hole 28, described through hole 28 exposes described substrate 20, follow-up in order to form conductive plunger.
The technique etching described dielectric layer 23, first insulating barrier 21 and the second insulating barrier 22 is this area maturation process, does not repeat them here.
Carbon content in the silicon oxide mask layer 26 adopting the present embodiment to be formed is less, when thus effectively improve etch media layer 23, the wear rate ratio of silicon oxide mask layer 26 and dielectric layer 23, thus the wear rate of silicon oxide mask layer 26 and dielectric layer 23 can be made suitable, and then form protruding defect above the through-hole side wall decreasing described dielectric layer 23.
At the described through hole 28 of formation, and after removing described photoresist mask 28, carry out wet clean step, during to remove etching described dielectric layer 23, residue in the etch by-products in described through hole 28, with reduce follow-up to filled conductive material in described through hole 28 to form conductive plunger time, be entrained in the etch by-products in electric conducting material, reduce etch by-products to the performance impact of conductive plunger.
In the present embodiment, described wet clean step adopts the hydrofluoric acid solution (DHF) of dilution as cleaning agent.Particularly, in the hydrofluoric acid solution of described dilution, the volume ratio of hydrofluoric acid and water is about 1:300.
Wherein, the hydrofluoric acid solution of the dilution of above-mentioned concentration can guarantee that described etch by-products has higher elimination efficiency, also reduces simultaneously and damages described dielectric layer 23.
As mentioned above, in employing the present embodiment, the formation process of silicon oxide mask layer 26 effectively can reduce the carbon content in oxide layer 26, make the wear rate of silicon oxide mask layer 36 and dielectric layer 23 in wet cleaning processes suitable, thus, wet-cleaned can be reduced above the sidewall of the through hole 28 of described dielectric layer 23, form protruding 18 defects, thus improve the performance of the conductive plunger formed after filled conductive material in described through hole 28.
With reference to shown in Figure 13, after described wet clean step, in described metallic mask layer 271, and diffusion impervious layer 29 is formed on the opening of described hard mask and through hole 28 sidewall of dielectric layer 23 and bottom.
In the present embodiment, the material of described diffusion impervious layer 29 is tantalum nitride (TaN), and formation process is CVD.
In other embodiments of the invention; the material of described diffusion impervious layer 29 also can be tantalum (Ta) etc.; formation method is physical vapour deposition (PVD) (PhysicalVaporDeposition; PVD) etc., the material of described diffusion impervious layer 29 and formation method do not limit protection scope of the present invention.
Compared to existing technique, in the present embodiment, after wet clean process, significantly protruding 18 defects are not had above through hole 28 inwall in described dielectric layer 23, thus effectively can reduce the spallation problems of the diffusion impervious layer 29 covered on through hole 28 inwall, thus effectively can improve the adhesion of described diffusion impervious layer 29 and dielectric layer 23.
Afterwards, remove the diffusion impervious layer bottom described through hole 28, retain the diffusion impervious layer 29 of described through hole 28 sidewall, expose described substrate 20.
With reference to shown in Figure 14, described diffusion impervious layer 29 forms conductive material layer 30, and in the present embodiment, the material of described conductive material layer 30 is metallic copper.Described conductive material layer 30 fills full described through hole 28.
With reference to shown in Figure 15, adopt the techniques such as cmp (CMP), remove the conductive material layer above described substrate 20 and hard mask, expose described substrate 20 surface, conductive material layer surface in described through hole 28 is flushed with described dielectric layer 23 surface, in described dielectric layer 22, forms conductive plunger 31.
Compared to the silicon oxide layer formed by existing technique, in the present embodiment, carbon content in described silicon oxide mask layer 26 obviously reduces, thus when such as etch media layer, and in wet cleaning processes, improve the wear rate of silicon oxide mask layer 36, make the wear rate of silicon oxide mask layer 36 and dielectric layer 23 close, thus the sidewall that can reduce through hole 28 forms the structures such as protruding, and then improve described conductive material layer 30 and be filled in filling capacity in described through hole 28, the space that effective minimizing is formed in described conductive material layer 30, to improve described conductive plunger 31 performance.
Embodiment 2
Participate in Figure 16 and 17, illustrate the structural representation of another embodiment of formation method of interconnection structure of the present invention.
The formation method of the interconnection structure of the present embodiment and Fig. 4 repeat no more to something in common embodiment illustrated in fig. 15, and its difference is:
In the present embodiment, described in the silicon oxide mask layer be formed on described low-K dielectric mask layer 24 be single layer structure, forming step comprises:
With reference to Figure 16, first on described low-K dielectric material layer 24, form tetraethyl orthosilicate layer 361, again oxygen plasma treatment is carried out to described tetraethyl orthosilicate layer 361 afterwards, oxygen plasma and described tetraethyl orthosilicate layer 361 are reacted, to form silicon oxide mask layer 362.
In order to reduce the carbon atom in described silicon oxide mask layer 362, the flow of oxygen in oxygen plasma treatment can be improved, and the process conditions such as time of oxygen plasma treatment, oxygen plasma and tetraethyl orthosilicate layer 361 are fully reacted, thus the carbon atom shifted efficiently in original tetraethyl orthosilicate layer 361, effectively reduce the carbon content in the silicon oxide mask layer 362 formed.The present embodiment can reduce the complexity of technological process.
After the described silicon oxide mask layer 362 of formation, directly can form metallic mask layer 37 on described silicon oxide mask layer 362, carry out the technique such as etch media layer, filled conductive material more afterwards, to form interconnection structure, the step of these subsequent techniques is similar to the aforementioned embodiment, does not repeat them here.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (14)
1. a formation method for interconnection structure, is characterized in that, comprising:
Substrate is provided;
Form dielectric layer on the substrate;
Described dielectric layer is formed tetraethyl orthosilicate layer;
Carry out oxygen plasma treatment to described tetraethyl orthosilicate layer, described oxygen plasma and described tetraethyl orthosilicate layer react and form silicon oxide mask layer;
Described silicon oxide mask layer forms metallic mask layer;
Etch described metallic mask layer and silicon oxide mask layer, form hard mask;
With described hard mask for dielectric layer described in mask etching, in described dielectric layer, form through hole;
Filled conductive material in described through hole, to form conductive plunger.
2. the formation method of interconnection structure as claimed in claim 1, is characterized in that,
The amount of carrying out the oxygen that oxygen plasma treatment adopts to described tetraethyl orthosilicate layer is greater than the amount of the tetraethyl orthosilicate adopted when forming tetraethyl orthosilicate layer.
3. the formation method of interconnection structure as claimed in claim 2, is characterized in that, carrying out oxygen plasma treatment oxygen used with the amount of substance ratio of tetraethyl orthosilicate used during formation tetraethyl orthosilicate layer is 1:5 ~ 1:50.
4. the formation method of interconnection structure as claimed in claim 1, is characterized in that, the method forming tetraethyl orthosilicate layer is chemical vapour deposition technique.
5. the formation method of interconnection structure as claimed in claim 4, is characterized in that, the flow forming tetraethyl orthosilicate in the step of tetraethyl orthosilicate layer is less than or equal to 200mg/min.
6. the formation method of interconnection structure as claimed in claim 1, is characterized in that, the synthesis speed forming tetraethyl orthosilicate layer in the step of tetraethyl orthosilicate layer is
7. the formation method of interconnection structure as claimed in claim 1, it is characterized in that, the thickness of described tetraethyl orthosilicate layer is
8. the formation method of interconnection structure as claimed in claim 1, is characterized in that, comprise the step that described tetraethyl orthosilicate layer carries out oxygen plasma treatment: pass into the oxygen that flow is 10000 ~ 20000sccm.
9. the formation method of the interconnection structure as described in claim 5 or 8, is characterized in that, the step forming tetraethyl orthosilicate layer comprises: air pressure is 0.1 ~ 10torr, and power is 100 ~ 5000W, and the flow of tetraethyl orthosilicate is 10 ~ 150mg/min;
Comprise the step that described tetraethyl orthosilicate layer carries out oxygen plasma treatment: air pressure is 0.1 ~ 10torr, power is 100 ~ 5000W, and the flow of oxygen is 15000 ~ 20000sccm.
10. the formation method of interconnection structure as claimed in claim 1, is characterized in that, before the described metallic mask layer of formation, the formation method of described interconnection structure comprises:
Repeat the step forming described tetraethyl orthosilicate layer and described tetraethyl orthosilicate layer is carried out to oxygen plasma treatment, to form silicon oxide mask layer.
The formation method of 11. interconnection structures as claimed in claim 1, is characterized in that, performs step 1 ~ 6 time forming tetraethyl orthosilicate layer and carry out oxygen plasma treatment, to form silicon oxide mask layer.
The formation method of 12. interconnection structures as claimed in claim 1, is characterized in that, carry out oxygen plasma treatment, comprise with the step forming silicon oxide mask layer described tetraethyl orthosilicate layer: the content forming carbon atom is less than or equal to 1.0 × 10
18the silicon oxide mask layer of individual atoms per cubic centimeter.
The formation method of 13. interconnection structures as claimed in claim 1, is characterized in that, form through hole in described dielectric layer after, in described through hole before filled conductive material, the formation method of described interconnection structure also comprises carries out wet clean step to through hole.
The formation method of 14. interconnection structures as claimed in claim 1, it is characterized in that, before described dielectric layer is formed silicon oxide mask layer, the formation method of described interconnection structure is also included on described dielectric layer and forms low-K dielectric mask layer, and the K value of described low-K dielectric mask layer is less than or equal to 3;
Etch described metallic mask layer and silicon oxide mask layer, the step forming hard mask comprises:
Etch described metallic mask layer, silicon oxide mask layer and low-K dielectric mask layer, to form hard mask.
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| US6287961B1 (en) * | 1999-01-04 | 2001-09-11 | Taiwan Semiconductor Manufacturing Company | Dual damascene patterned conductor layer formation method without etch stop layer |
| US20060105568A1 (en) * | 2004-11-12 | 2006-05-18 | Shen Jin M | Plasma treatment for surface of semiconductor device |
| US20100068875A1 (en) * | 2008-09-15 | 2010-03-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Double treatment on hard mask for gate n/p patterning |
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2014
- 2014-08-05 CN CN201410381338.6A patent/CN105336678B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6287961B1 (en) * | 1999-01-04 | 2001-09-11 | Taiwan Semiconductor Manufacturing Company | Dual damascene patterned conductor layer formation method without etch stop layer |
| US20060105568A1 (en) * | 2004-11-12 | 2006-05-18 | Shen Jin M | Plasma treatment for surface of semiconductor device |
| US20100068875A1 (en) * | 2008-09-15 | 2010-03-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Double treatment on hard mask for gate n/p patterning |
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