CN105335261A - Design method for testing BIT in server equipment - Google Patents
Design method for testing BIT in server equipment Download PDFInfo
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- CN105335261A CN105335261A CN201510894886.3A CN201510894886A CN105335261A CN 105335261 A CN105335261 A CN 105335261A CN 201510894886 A CN201510894886 A CN 201510894886A CN 105335261 A CN105335261 A CN 105335261A
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Abstract
The invention discloses a design method for testing BIT in server equipment. A server is divided into two layers of a module level site replaceable unit (LRU) and a chip level functional circuit according to a complete machine and a unit in the aspect of a system structure, and each functional unit can perform testing independently; the functional units of the server are mainly connected through a network cable, and the voltage, the temperature and the work state of the units can be monitored and managed through a management unit. The method is divided into three steps of distributed type testing and acquisition management, information state concentrated processing, and display and operation according to a framework structure. The design method has high fault diagnosis capacity and can isolate faults to the units (LRU); full testing can be performed, equipment reliability and safety are guaranteed by testing all possible faults of a covered equipment circuit system, and equipment reliability and testability are greatly improved.
Description
Technical field
The present invention relates to and reinforce server and technical field of measurement and test, be specifically related to a kind of server apparatus built-in test BIT method for designing, devise a kind of built-in test method for designing of server, substantially increase reliability and the testability of equipment.
Background technology
In server application, high reliability request airborne equipment, on-board equipment, mobile unit, as satellite, airship and naval ship, do not allow to break down.In order to ensure the reliability of equipment and system, generally all require that equipment has higher trouble diagnosibility, and can by fault isolation to each unit (LRU); And can fully test, reliability and the security of equipment is guaranteed by all contingent faults of Test coverage circuitry system.
In order to realize above-mentioned technical requirement, server must be carried out distinguishing hierarchy and design from system architecture, function two aspect to testability design, just consider the demand of test performance at the beginning of design comprehensively, by stratification detection and the fault isolation of chip-scale BIT, module level BIT and System-Level BIT, improve the reliability of equipment.
Built-in test BIT(Built-InTest) be a kind of important technology that can significantly improve system testing and diagnosis capability, be one of important technical realizing Testability Design.Describe the definition of built-in test technology, feature, classification, design content and design cycle etc., illustrate the development course of built-in test technology, and the new trend of testability technology is inquired into and looked forward to.
BIT refers to the automatic test capability of detection that system and device interior provide, isolated fault, refer to that system headrig just can complete functional check to system, subsystem or equipment, fault diagnosis and treatment and performance test without external test facility, it is the new development of On-line measurement technology.
Summary of the invention
The technical problem to be solved in the present invention is: provide a kind of magnetic-type wicket, can meet EMC Requirements, and simultaneously simple and reliable for structure, processing cost is low, installs also more for convenience.
Ruggedized computer wicket is usually after wicket is closed, requirement can keep certain snap-in force to the shielding material playing sealing and electromagnetic screen, this snap-in force makes encapsulant generation elastic deformation, thus fill surface of contact gap, play the effect of sealing (waterproof) and conduction continuous (electromagnetic compatibility).
The technical solution adopted in the present invention is:
A kind of server apparatus built-in test BIT method for designing, described server is two levels according to complete machine and dividing elements in system architecture: module level Field Replaceable Unit LRU and chip-scale functional circuit, and each functional unit can independently be tested; Connect mainly through network cable between each functional unit of server, by administrative unit, monitor and managment is carried out to the voltage of each unit, temperature and duty thereof;
Described method is divided into three grades by framed structure: distributed testing and acquisition process, information state focus on, show and operate, and implementation procedure is as follows:
The first order, distributed testing and acquisition process: by self-test and Acquisition Circuit, directly embed in each unit (LRU) and realize;
The second level, information state focus on, by the acquisition process circuit of complete machine, administrative unit is by the status information such as management bus (mode such as network, serial ports) Real-time Collection self-test and the temperature measured by acquisition process circuit, voltage, Key Circuit test point characteristic signal;
The third level, display and operation: the information state of complete machine is undertaken showing and processing by the aobvious control terminal be inlaid in administrative unit; And the state of complete machine is externally issued by supervising the network.
Described first order distributed testing and acquisition process process, self-test and Acquisition Circuit, the each unit of direct embedding (LRU), built-in test BIT circuit reads each functional circuit sensor information by IPMB, carry out TDI input by chip JTAG mouth and TDO is compared with the standard value of write register, judge that whether chip is normal, fault alarm, fault diagnosis and fault handling function are provided, thus improve unit reliability;
Wherein: IPMBIntelligentPlatformManagementBUS, Intelligent Platform Management Bus is the general name of two groups of redundancy I2C buses of each FRU backboard communication of the telecommunications computing platform that ATCA (AdvancedTelecomComputingArchitecture) is advanced;
The chip with JTAG mouth has following JTAG pinout:
TCK---test clock inputs;
TDI---test data inputs, and data input JTAG mouth by TDI;
TDO---test data exports, and data are exported from JTAG mouth by TDO;
TMS---test pattern is selected, and TMS is used for arranging JTAG mouth and is in certain specific test pattern.
Described method test process adopts the mechanism of continuous monitoring, continuous detecting in systems in which.Some fault may not influential system work, automatically disappears sometimes, although and some faults can not damage equipment, if stopped not in time, system can cannot normally work, and therefore need to take immediate measure, otherwise fault is by damage equipment.
Described method is when realizing fault detection capability, and for each detection module designs a failure counter, Counter Value is initialized as 0, and when functional module detects primary fault, failure counter adds 1.Enter next sense cycle, if failure vanishes, then failure counter subtracts 1, when counting reaches threshold value, carries out fault alarm, thus reaches the effect reducing false alarm rate.
Beneficial effect of the present invention is:
The present invention has higher trouble diagnosibility, and can by fault isolation to each unit (LRU); And can fully test, guaranteed reliability and the security of equipment by all contingent faults of Test coverage circuitry system, substantially increase reliability and the testability of equipment.
Accompanying drawing explanation
Fig. 1 is server system structure composition schematic diagram;
Fig. 2 is computing unit BIT circuit diagram;
Fig. 3 is complete machine built-in test BIT circuit diagram;
Fig. 4 is BIT FB(flow block).
Embodiment
With reference to the accompanying drawings, by embodiment, the present invention is further described:
Embodiment 1:
A kind of server apparatus built-in test BIT method for designing, described server is two levels according to complete machine and dividing elements in system architecture: module level Field Replaceable Unit LRU and chip-scale functional circuit, as shown in Figure 1, wherein the second layer is the Field Replaceable Unit (LRU) of server, and each functional unit can independently be tested; Connect mainly through network cable between each functional unit of server, by administrative unit, monitor and managment is carried out to the voltage of each unit, temperature and duty thereof;
As shown in Figure 3, described method is divided into three grades by framed structure: distributed testing and acquisition process, information state focus on, show and operate, and implementation procedure is as follows:
The first order, distributed testing and acquisition process: by self-test and Acquisition Circuit, directly embed in each unit (LRU) and realize;
The second level, information state focus on, by the acquisition process circuit of complete machine, administrative unit is by the status information such as management bus (mode such as network, serial ports) Real-time Collection self-test and the temperature measured by acquisition process circuit, voltage, Key Circuit test point characteristic signal;
The third level, display and operation: the information state of complete machine is undertaken showing and processing by the aobvious control terminal be inlaid in administrative unit; And the state of complete machine is externally issued by supervising the network.
Embodiment 2:
On the basis of embodiment 1, first order distributed testing described in the present embodiment and acquisition process process, self-test and Acquisition Circuit, the each unit of direct embedding (LRU), for computing unit, built-in test BIT circuit as shown in Figure 2, built-in test BIT circuit reads each functional circuit sensor information by IPMB, carry out TDI input by chip JTAG mouth and TDO is compared with the standard value of write register, judge that whether chip is normal, fault alarm, fault diagnosis and fault handling function are provided, thus improve unit reliability.
Wherein: IPMBIntelligentPlatformManagementBUS, Intelligent Platform Management Bus is the general name of two groups of redundancy I2C buses of each FRU backboard communication of the telecommunications computing platform that ATCA (AdvancedTelecomComputingArchitecture) is advanced;
The chip with JTAG mouth has following JTAG pinout:
TCK---test clock inputs;
TDI---test data inputs, and data input JTAG mouth by TDI;
TDO---test data exports, and data are exported from JTAG mouth by TDO;
TMS---test pattern is selected, and TMS is used for arranging JTAG mouth and is in certain specific test pattern.
Embodiment 3:
On the basis of embodiment 1 or 2, described in the present embodiment, method test process adopts the mechanism of continuous monitoring, continuous detecting in systems in which.Some fault may not influential system work, automatically disappears sometimes, although and some faults can not damage equipment, if stopped not in time, system can cannot normally work, and therefore need to take immediate measure, otherwise fault is by damage equipment.
Embodiment 4:
On the basis of embodiment 3, described in the present embodiment, method is when realizing fault detection capability, and for each detection module designs a failure counter, Counter Value is initialized as 0, and when functional module detects primary fault, failure counter adds 1.Enter next sense cycle, if failure vanishes, then failure counter subtracts 1, when counting reaches threshold value, carries out fault alarm, thus reaches the effect reducing false alarm rate.
BIT test flow chart as shown in Figure 4.
Above embodiment is only for illustration of the present invention; and be not limitation of the present invention; the those of ordinary skill of relevant technical field; without departing from the spirit and scope of the present invention; can also make a variety of changes and modification; therefore all equivalent technical schemes also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.
Claims (4)
1. a server apparatus built-in test BIT method for designing, it is characterized in that: described server is two levels according to complete machine and dividing elements in system architecture: module level Field Replaceable Unit LRU and chip-scale functional circuit, and each functional unit can independently be tested; Connect mainly through network cable between each functional unit of server, by administrative unit, monitor and managment is carried out to the voltage of each unit, temperature and duty thereof;
Described method is divided into three grades by framed structure: distributed testing and acquisition process, information state focus on, show and operate, and implementation procedure is as follows:
The first order, distributed testing and acquisition process: by self-test and Acquisition Circuit, directly embed in each unit LRU and realize;
The second level, information state focus on, and by the acquisition process circuit of complete machine, administrative unit is by the self-test of management bus Real-time Collection and the status information measured by acquisition process circuit;
The third level, display and operation: the information state of complete machine is undertaken showing and processing by the aobvious control terminal be inlaid in administrative unit; And the state of complete machine is externally issued by supervising the network.
2. a kind of server apparatus built-in test BIT method for designing according to claim 1, it is characterized in that: described first order distributed testing and acquisition process process, built-in test BIT circuit reads each functional circuit sensor information by IPMB, carry out TDI input by chip JTAG mouth and TDO is compared with the standard value of write register, judge that whether chip is normal, fault alarm, fault diagnosis and fault handling function are provided.
3. a kind of server apparatus built-in test BIT method for designing according to claim 1 and 2, is characterized in that: described method test process adopts the mechanism of continuous monitoring, continuous detecting in systems in which.
4. a kind of server apparatus built-in test BIT method for designing according to claim 3, it is characterized in that: described method is when realizing fault detection capability, for each detection module designs a failure counter, Counter Value is initialized as 0, when functional module detects primary fault, failure counter adds 1; Enter next sense cycle, if failure vanishes, then failure counter subtracts 1, when counting reaches threshold value, carries out fault alarm.
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106546850A (en) * | 2016-10-30 | 2017-03-29 | 中国电子科技集团公司第二十九研究所 | A kind of SRU fault recognition method and devices based on detection thermal station |
| CN107451030A (en) * | 2017-07-19 | 2017-12-08 | 山东超越数控电子有限公司 | A kind of server machine built-in test system and method |
| CN107729276A (en) * | 2017-09-24 | 2018-02-23 | 中国航空工业集团公司洛阳电光设备研究所 | A kind of method that classification built-in test is realized using boundary scan technique |
| CN108667753A (en) * | 2018-05-03 | 2018-10-16 | 济南浪潮高新科技投资发展有限公司 | A kind of exchange management method and device with redundancy feature |
| CN109116835A (en) * | 2018-09-05 | 2019-01-01 | 中国船舶重工集团公司第七〇九研究所 | A kind of feature card test method peculiar to vessel and device |
| CN109783286A (en) * | 2018-12-28 | 2019-05-21 | 中国科学院长春光学精密机械与物理研究所 | Built-in test method, test device and terminal device and storage medium |
| CN109901380A (en) * | 2017-12-11 | 2019-06-18 | 上海航空电器有限公司 | Application circuit and method based on the redundancy design of hardware mediation on power system processor |
| CN110297737A (en) * | 2019-07-10 | 2019-10-01 | 北京汽车股份有限公司 | The fault diagnosis test method and device of multiple-channel output chip |
| CN113255867A (en) * | 2021-05-21 | 2021-08-13 | 北京银联金卡科技有限公司 | Anti-counterfeiting design method of hierarchical high-reliability chip |
| CN113742941A (en) * | 2021-09-16 | 2021-12-03 | 北京航空航天大学 | Complex equipment system testability modeling platform based on hierarchical analysis of system structure |
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Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106546850B (en) * | 2016-10-30 | 2018-11-27 | 中国电子科技集团公司第二十九研究所 | A kind of SRU fault confirmation method and device based on detection thermal station |
| CN106546850A (en) * | 2016-10-30 | 2017-03-29 | 中国电子科技集团公司第二十九研究所 | A kind of SRU fault recognition method and devices based on detection thermal station |
| CN107451030A (en) * | 2017-07-19 | 2017-12-08 | 山东超越数控电子有限公司 | A kind of server machine built-in test system and method |
| CN107729276A (en) * | 2017-09-24 | 2018-02-23 | 中国航空工业集团公司洛阳电光设备研究所 | A kind of method that classification built-in test is realized using boundary scan technique |
| CN109901380A (en) * | 2017-12-11 | 2019-06-18 | 上海航空电器有限公司 | Application circuit and method based on the redundancy design of hardware mediation on power system processor |
| CN108667753A (en) * | 2018-05-03 | 2018-10-16 | 济南浪潮高新科技投资发展有限公司 | A kind of exchange management method and device with redundancy feature |
| CN109116835A (en) * | 2018-09-05 | 2019-01-01 | 中国船舶重工集团公司第七〇九研究所 | A kind of feature card test method peculiar to vessel and device |
| CN109783286A (en) * | 2018-12-28 | 2019-05-21 | 中国科学院长春光学精密机械与物理研究所 | Built-in test method, test device and terminal device and storage medium |
| CN109783286B (en) * | 2018-12-28 | 2021-03-19 | 中国科学院长春光学精密机械与物理研究所 | Built-in test method, test device, terminal equipment and storage medium |
| CN110297737A (en) * | 2019-07-10 | 2019-10-01 | 北京汽车股份有限公司 | The fault diagnosis test method and device of multiple-channel output chip |
| CN113255867A (en) * | 2021-05-21 | 2021-08-13 | 北京银联金卡科技有限公司 | Anti-counterfeiting design method of hierarchical high-reliability chip |
| CN113255867B (en) * | 2021-05-21 | 2024-07-12 | 北京银联金卡科技有限公司 | Anti-counterfeiting design method for hierarchical high-reliability chip |
| CN113742941A (en) * | 2021-09-16 | 2021-12-03 | 北京航空航天大学 | Complex equipment system testability modeling platform based on hierarchical analysis of system structure |
| CN113742941B (en) * | 2021-09-16 | 2024-05-10 | 北京航空航天大学 | Complex equipment system testability modeling platform based on system structure layering analysis |
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