CN113255867A - Anti-counterfeiting design method of hierarchical high-reliability chip - Google Patents
Anti-counterfeiting design method of hierarchical high-reliability chip Download PDFInfo
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- 239000002184 metal Substances 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 238000012795 verification Methods 0.000 claims description 15
- 229910021332 silicide Inorganic materials 0.000 claims description 8
- 230000003287 optical effect Effects 0.000 claims description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000005516 engineering process Methods 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 230000006870 function Effects 0.000 description 15
- 238000010586 diagram Methods 0.000 description 6
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- 230000005012 migration Effects 0.000 description 4
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- 230000002427 irreversible effect Effects 0.000 description 2
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- 238000005299 abrasion Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/30—Authentication, i.e. establishing the identity or authorisation of security principals
- G06F21/31—User authentication
- G06F21/36—User authentication by graphic or iconic representation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/06009—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code with optically detectable marking
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Abstract
The invention discloses an anti-counterfeiting design method of a hierarchical high-reliability chip, which comprises the following steps: structurally dividing a chip into a high-reliability area and a common area, and arranging a fault isolation structure between the high-reliability area and the common area; the high-reliability region comprises a ROM module, wherein some circuit units in the ROM module are fused by using large current to form a plurality of fused blocks, and the plurality of fused blocks are coded; burning the confidential data into the fusing blocks in a programming mode according to the coding sequence, taking the confidential data as a unique identification code of the chip, and taking a fusing pattern formed by a plurality of fusing blocks as an anti-counterfeiting pattern of the chip; and authenticating the identification code and the anti-counterfeiting pattern. The invention is used in the anti-counterfeiting technical field, and can greatly improve the anti-counterfeiting performance and reliability of the chip.
Description
Technical Field
The invention relates to the technical field of anti-counterfeiting, in particular to an anti-counterfeiting design method of a hierarchical high-reliability chip.
Background
The special anti-counterfeiting chip for products such as commemorative coins, certificates, seals, cash carriers and the like needs to have high reliability (capable of resisting environmental factors such as deformation, humidity, static electricity and the like in daily life), long service life (the service life of the chip is longer than the service life of a protected product, the design service life is longer than 50 years and is preferably up to 100 years under a normal environment), and high safety (capable of resisting a known attack mode or resisting the attack cost which is far higher than the value (>1M RMB) of the protected product).
For security, the security risks of cracking application programs, stealing private data and the like, which are ubiquitous at present, pose great threats to users, enterprises and countries. If all the areas of the chip are upgraded to safe areas, the cost is high, and if all the areas of the chip are areas without safety protection, the safety level is low.
For reliability, if a chip with a large area is made into a high-reliability area, the cost is high, and the chip lacks practical value in the field with high requirement on the cost, if the chip does not have the high-reliability area at all, once the chip is interfered by external factors such as heat, high pressure, humidity and the like, internal important information is lost, the chip loses the function of the chip, and for the anti-counterfeiting field, the chip does not have the anti-counterfeiting check function any more, which is a serious defect for some products with long life cycle.
Disclosure of Invention
The invention aims to provide a hierarchical high-reliability chip anti-counterfeiting design method, aiming at solving the technical problem of improving the anti-counterfeiting performance of a chip.
In order to achieve the purpose, the invention adopts the following technical scheme:
a method for designing an anti-counterfeiting chip with high grade reliability comprises the following steps:
structurally dividing a chip into a high-reliability area and a common area, and arranging a fault isolation structure between the high-reliability area and the common area;
the high-reliability region comprises a ROM module, some circuit units in the ROM module are fused by using large current to form a plurality of fused blocks, and the plurality of fused blocks are coded;
burning secret data into the fusing blocks in a programming mode according to a coding sequence, taking the secret data as a unique identification code of a chip, and taking a fusing pattern formed by the fusing blocks as an anti-counterfeiting pattern of the chip;
authenticating the identification code and the anti-counterfeiting pattern;
wherein the high reliability region and the low reliability region are communicatively connected by an on-chip bus and share a clock and a power supply.
In one embodiment, a high current fusing metal/polysilicon technology is used to fuse metal/silicide in a circuit cell in the ROM to open the circuit cell.
In one embodiment, the two-dimensional pattern formed by the arrangement sequence and the arrangement form of the fuse blocks on the surface of the ROM module and the configuration of the fuse blocks is used as the anti-counterfeiting pattern.
In one embodiment, the secret data includes a burning sequence, UID information and check code information.
In one embodiment, the anti-counterfeiting check of the identification code is carried out through RFID or NFC; performing anti-counterfeiting verification on the anti-counterfeiting pattern in an optical reading mode; when both verify true, the chip is true.
In one embodiment, the high reliability region stores a production serial number, an encryption algorithm and a corresponding key.
In one embodiment, the high reliability region and the normal region are configured to: the high-reliability area can directly access the ordinary area, and the ordinary area needs to access the high-reliability area after the verification is successful.
The invention has the advantages that:
the anti-counterfeiting design method of the graded high-reliability chip provided by the invention can improve the anti-counterfeiting performance of the chip through the double anti-counterfeiting design of the identification code and the anti-counterfeiting pattern. The chip is divided into a high-reliability area and a common area based on the chip classification technology, fault isolation exists between the high-reliability area and the common area, and high reliability guarantee can be provided for application. The highly reliable region possesses a higher level of security and reliability than the normal environment, and reasonable costs can be achieved because the region area is not large.
Drawings
FIG. 1 is a schematic diagram of the main steps of an anti-counterfeit design method for a hierarchical high-reliability chip.
Fig. 2 is a schematic structural diagram of a hierarchical high-reliability chip.
Fig. 3 is a schematic diagram of a circuit unit.
FIG. 4 is a schematic diagram of a fuse block in a ROM module.
Detailed Description
Preferred embodiments of the present invention are described below with reference to the accompanying drawings. It should be understood by those skilled in the art that these embodiments are only for explaining the technical principle of the present invention, and are not intended to limit the scope of the present invention.
Referring to fig. 1, fig. 1 shows the main steps of a method for designing an anti-counterfeit of a hierarchical high-reliability chip. As shown in fig. 1, the anti-counterfeit design method of the hierarchical high-reliability chip provided by the present invention mainly comprises:
step S1: the chip is structurally divided into a high-reliability area and a common area, and a fault isolation structure is arranged between the high-reliability area and the common area.
Step S2: the high reliability region contains a ROM module, some circuit cells in the ROM module are fused with a large current to form a plurality of fuse blocks, and the plurality of fuse blocks are encoded.
Step S3: and burning the confidential data into the fusing blocks in a programming mode according to the coding sequence, taking the confidential data as a unique identification code of the chip, and taking the fusing pattern formed by the fusing blocks as an anti-counterfeiting pattern of the chip.
Step S4: and authenticating the identification code and the anti-counterfeiting pattern.
Referring to fig. 2, fig. 2 shows a schematic diagram of a hierarchical high-reliability chip. The high-reliability area of the chip is a core functional area of the whole chip, wherein the core functional area comprises functional modules of the core and information of the core. For example, in the field of anti-counterfeiting, secure and confidential information can be placed in a highly reliable area, such as a production serial number, an encryption algorithm, a corresponding key, and the like. Therefore, even if the circuit of the common area is damaged or the information is lost, the information of the high-reliability area is still reserved, and core functions such as sending a verification request through NFC can still be realized like providing verification information. Other specific modules can be stored in the high-reliability area and can be set according to actual requirements.
In the normal area of the chip, more functional modules other than the core function can be placed, that is, non-core functional modules, such as IO ports, exist in the normal area. The chip area occupied by the modules is often large, and when the external environment is changed drastically, the content may be lost, but the loss of the content does not affect the core function of the chip, and only the function of a part of peripheral devices is affected. For the anti-counterfeiting field, it is very important that the verification information can be provided even if some external peripheral functions are damaged.
The high-reliability area and the common area can be communicated with each other, the high-reliability area and the common area are in communication connection through an on-chip bus, and the high-reliability area and the common area share a clock and a power supply. The high-reliability area has higher authority level, the information stored in the high-reliability area is always required to be kept secret and needs to be stored for a long time, such as a production serial number, a UID (user identification device), a key required by an encryption algorithm and the like, and the information cannot be tampered by the module in the ordinary area but can be called. The authority level of the common area is lower, and the information in the common area can be modified and called by the high-reliability area. Namely, the high-reliability region and the normal region are configured as: the high-reliability area can directly access the ordinary area, and the ordinary area needs to access the high-reliability area after the verification is successful.
The high-reliability area and the common area can share a clock CLK and a power supply VCC, and simultaneously the high-reliability area and the common area communicate through an on-chip bus, and the high-reliability area and the common area have a double isolation mechanism of safety isolation and fault isolation. The safety isolation mechanism is characterized in that a module with richer functions operates in a common area, and a basic function module is arranged in a high-reliability area. When an operation request with authority of a common area needs to call a module in the high-reliability area, firstly, the module interacts with a verification module of the high-reliability area through a bus signal, and the module can be called after verification is successful. When an operation request that a common area does not have the calling authority attempts to call a module in the high-reliability area, the module cannot be called successfully, and the high-reliability area sets the memory area as a safe memory to refuse the access of the high-level operating system, so that the data in the high-reliability area is prevented from being leaked or tampered. And the high reliability of the high-reliability domain enables the high-reliability domain to have higher authority so that the high-reliability domain can randomly call the modules of the common domain and store the information and the like.
A fault isolation structure is arranged between the high-reliability area and the common area, when certain components in the common area are damaged due to changes of external environment factors such as temperature, humidity and the like in the processes of transportation, distribution, storage and the like, the high-reliability area is provided with a core function module which is not damaged due to high reliability, and data is normally stored due to long storage time, so that the anti-counterfeiting system can normally operate, and the anti-counterfeiting function is realized.
Through the arrangement, the compromise problem between cost and reliability protection can be solved, all areas of the chip are upgraded to high-reliability areas, the cost of the scheme is too high, if all the areas of the chip are low-reliability areas, the reliability is low, and the anti-counterfeiting task cannot be completed within a long life cycle, so that a method of only adopting a part of hardware to form the high-reliability areas is selected; the communication between the second high-reliability area and the common area is completed through a bus, and the second high-reliability area and the common area have different permission levels; the third high-reliability area and the common area have fault and safe isolation, and the function of preventing the important information of the core of the chip from being tampered can be well ensured.
After the technology is applied, the chip has rich functions when the chip normally runs, and the core information in the chip cannot be tampered by an attacker, so that the guarantee of high safety is provided. Even when the common area of the chip fails, the anti-counterfeiting function can still work because the high-reliability area has the core function. Because not all areas are made of highly reliable nature, there are cost-controllable, compressible advantages. And an attacker is difficult to copy the same type of chips, so that higher anti-counterfeiting degree is achieved.
Further, the high reliability region contains the ROM module, some circuit cells in the ROM module may be fused with a large current to form a plurality of fused blocks, and the plurality of fused blocks are encoded.
Specifically, after volume information and instruction information of each fuse block are obtained according to configuration requirements, a metal/silicide in a circuit unit in the ROM is fused (which may be a single metal/silicide or a plurality of adjacent metals/silicides) by means of fusing metal/polysilicon with a large current, so that the current circuit unit is open (which is a single metal/silicide or a plurality of adjacent metals/silicides), and a plurality of fuse blocks (each fuse block has the same or different volume) are obtained. The instruction information may specifically be: it is set that the circuit unit is blown when the command is 1 or high level, and the circuit unit is kept as it is when the command is 0 or low level.
Referring to fig. 3, a high level is applied to two ends of a metal fuse for a certain time, so that a large current is generated, under the action of large-current electromigration, metal atoms are subjected to the action of moving conductive electrons and migrate from a cathode to an anode along a crystal grain, the electron migration is increased along with the increase of current density, if the electromigration is severe, atoms migrated from the cathode are accumulated on an anode of a metal fuse chain, and at the moment, the atoms of the cathode form a cavity due to migration, so that metal/silicide connecting the anode and the cathode are deformed under the influence of the current, and the cathode and the anode are opened (disconnected), so that the corresponding resistance of a circuit unit is increased, the conductivity is deteriorated, further, the internally stored information is changed, and the purpose of storing data can be realized by the circuit structure after the opening.
Referring to FIG. 4, FIG. 4 is a schematic diagram of a fuse block in a ROM module. The size of the fusing block can be adjusted correspondingly according to actual needs. The volumes of the fusing blocks are the same or different. For example, taking 8bits as an example, the fusing block 1 can be formed by fusing one circuit unit; the fusing block 2 can be formed by fusing two adjacent circuit units; the fusing block 3 can be fused by a circuit unit to form a circuit unit with the same volume as that of the fusing block 1; the fusing block 4 can be formed by fusing three adjacent circuit units; the fusing block 5 can be fused by two adjacent circuit units to form a structure with the same volume as that of the fusing block 2; the fusing block 6 may be formed by fusing one circuit unit; the fusing block 7 can be formed by fusing five circuit units; the fusing block 8 can be formed by fusing four circuit units, so that the fusing blocks 1-8 with different volumes can be used as anti-counterfeiting characteristics, and the anti-counterfeiting purpose is realized.
For another example, the fuse block shown in fig. 4 may have the following changes after programming: only patterns appear on the surface of the fusing block 1; the surface of the fusing block 2 is only hollowed; the surface of the fusing block 3 is hollowed out and patterned; the surface of the fusing block 4 has no change; hollowing out with different shapes at the same position as the fusing block 2 appears on the surface of the fusing block 5; the surface of the fusing block 6 is provided with patterns with the same positions and different forms as those of the fusing block 1; the fusing block 7 is hollowed out and has another pattern with different shapes and different positions from the fusing blocks 2 and 5; the fusing block 8 has a plurality of new patterns and a new hollow, so that different positions and different patterns distributed on the fusing blocks 1-8 are used as anti-counterfeiting characteristics, and the anti-counterfeiting purpose is realized.
The individual fuse blocks are randomly arranged on the ROM. The circuit units are placed in an actual layout as basic units, the arrangement of the circuit units is not common linear arrangement, as shown in fig. 4, an outer square frame in the drawing is a ROM surface, small square frames represent the arrangement of 1bit to 8bit, the circuit units are arranged in a specific format in space, the arrangement rule is only known by a distributor of a unique identification code, so that a cracker is difficult to crack, confidentiality is achieved, and the copying difficulty is increased. In the production process of the whole chip, a plurality of bits are subjected to fusing and then are sequenced: the numbers in fig. 4 indicate the writing order of the UID and the check code, and the smaller the number, the earlier the writing order. If the plurality of fusing blocks are linearly arranged, information such as UID (user identification) and verification can be obtained in a visual mode for an attacker with optical equipment such as a microscope and an Xray, and the risk is caused to safety. After random arrangement (shown in the arrangement in fig. 4), irregular arrangement can be performed in a two-dimensional plane, the arrangement shape is arbitrary, and for a potential replicator, even if the arrangement of the circuit unit units in the chip can be observed, secret data cannot be obtained only by obtaining the arrangement mode, so that an attacker cannot crack the secret data.
Further, the secret data is programmed and written into the fusing blocks according to the coding sequence, the secret data is used as the unique identification code of the chip, and the fusing pattern formed by the fusing blocks is used as the anti-counterfeiting pattern of the chip. Specifically, the secret data includes a burning sequence, UID information, and check code information. And respectively burning the UID information and the check code information into different fuse blocks according to the coding sequence, so that the surfaces of the fuse blocks have different patterns and hollows. So that each fuse block has differently configured structural features thereon, and these structural features are irreversible. The two-dimensional pattern formed by the arrangement sequence and the arrangement form of the fusing blocks on the surface of the ROM module and the configuration of the fusing blocks is used as the anti-counterfeiting pattern.
The user authenticates the identification code and the anti-counterfeiting pattern. Performing anti-counterfeiting check on the identification code through RFID or NFC; performing anti-counterfeiting verification on the anti-counterfeiting pattern in an optical reading mode; when both verify true, the chip is true.
Because the migration process of the metal is irreversible, the metal migration device has the characteristic of only being programmed once, unique UID (user identification) and check code contents are written in a chip ROM (read only memory) in the processes before delivery and sale after chips of products such as commemorative coins, certificates, seals and cash are produced, the uniqueness of the serial number can be realized by utilizing the irreparable modification in the subsequent processes, and the serial number is difficult to decipher even if the serial number is observed in an optical mode. Even if a copier purchases the fuse device with heavy money, the electronic information stored inside the fuse block is unique, and the copier cannot interpret information such as the UID and the verification. And when the number of bits of the stored information is more, the more various the shapes of the formed graphs are, the more obvious the disorder is, and the higher the confidentiality and the anti-counterfeiting performance are.
Performing anti-counterfeiting verification through RFID (Radio Frequency Identification) or NFC (Near Field Communication); these security features have visual characteristics that enable the visual observation of the volumes of the fuse blocks 1-8, their arrangement, the shape of the pattern on each fuse block, structural features, and the volume of the fuse blocks by optical instruments. The consistency of the anti-counterfeiting chips is detected after the circuit units are identified in an optical reading mode, if the corresponding circuit units are seen below the X-RAY, the unique anti-counterfeiting information coding (fusing and burning process) of each chip is realized by adopting a metal OTP (One Time Programmable) fuse, and the anti-counterfeiting information can be obtained through image identification (pattern, structure and volume characteristics on each fusing block) after the consistency (fusing block arrangement) of the anti-counterfeiting chips is checked through FIB (focused ion beam) equipment, 3D-XRAY equipment and the like. The anti-counterfeiting data in the ROM cannot be modified, imitated and has no mechanical abrasion and pollution damage; a physical interface which is not directly opened to an end user is read, so that the safety of the anti-counterfeiting chip is ensured; besides the password protection of the label, the anti-counterfeiting data adopts a secret algorithm to realize the safety management of partial data.
So far, the technical solutions of the present invention have been described in connection with the preferred embodiments shown in the drawings, but it is easily understood by those skilled in the art that the scope of the present invention is obviously not limited to these specific embodiments. Equivalent changes or substitutions of related technical features can be made by those skilled in the art without departing from the principle of the invention, and the technical scheme after the changes or substitutions can fall into the protection scope of the invention.
Claims (7)
1. A method for designing an anti-counterfeiting chip with high grade reliability is characterized by comprising the following steps:
structurally dividing a chip into a high-reliability area and a common area, and arranging a fault isolation structure between the high-reliability area and the common area;
the high-reliability region comprises a ROM module, some circuit units in the ROM module are fused by using large current to form a plurality of fused blocks, and the plurality of fused blocks are coded;
burning secret data into the fusing blocks in a programming mode according to a coding sequence, taking the secret data as a unique identification code of a chip, and taking a fusing pattern formed by the fusing blocks as an anti-counterfeiting pattern of the chip;
authenticating the identification code and the anti-counterfeiting pattern;
wherein the high reliability region and the low reliability region are communicatively connected by an on-chip bus and share a clock and a power supply.
2. The method according to claim 1, wherein the metal/silicide in the circuit unit in the ROM is fused by a high current fusing metal/polysilicon technology to open the circuit unit.
3. The method according to claim 1, wherein a two-dimensional pattern formed by the arrangement sequence, arrangement form and fuse block configuration of the fuse blocks on the surface of the ROM module is used as the anti-counterfeiting pattern.
4. The method for designing an anti-counterfeit of a hierarchical high-reliability chip according to claim 1, wherein the secret data includes a programming order, UID information and check code information.
5. The method for designing an anti-counterfeit of a hierarchical high-reliability chip according to claim 1, wherein the anti-counterfeit verification of the identification code is performed by RFID or NFC; performing anti-counterfeiting verification on the anti-counterfeiting pattern in an optical reading mode; when both verify true, the chip is true.
6. The method according to claim 1, wherein the high-reliability region stores a production serial number, an encryption algorithm and a corresponding key.
7. The method for anti-counterfeit design of a hierarchical high-reliability chip according to claim 1, wherein the high-reliability region and the common region are configured to: the high-reliability area can directly access the ordinary area, and the ordinary area needs to access the high-reliability area after the verification is successful.
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| CN113255867B (en) | 2024-07-12 |
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