CN105323468A - Video acquiring and processing device for medical endoscope - Google Patents
Video acquiring and processing device for medical endoscope Download PDFInfo
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- CN105323468A CN105323468A CN201510387355.5A CN201510387355A CN105323468A CN 105323468 A CN105323468 A CN 105323468A CN 201510387355 A CN201510387355 A CN 201510387355A CN 105323468 A CN105323468 A CN 105323468A
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Abstract
The invention relates to a video acquiring and processing device for a medical endoscope. The video acquiring and processing device comprises a video acquiring chip, an image processing chip, a signal conversion chip and an image enhancement chip; the video acquiring chip sends acquired video data to the image processing chip to process; the signal conversion chip comprises a first signal conversion chip and a second signal conversion chip; the first signal conversion chip is used for converting a bt1120 signal into a lvds signal; the second signal conversion chip is used for converting the lvds signal into the bt1120 signal; the image processing chip sends a processed image signal to the first signal conversion chip; the first signal conversion chip sends the processed image signal to the second signal conversion chip; and the second signal conversion chip converts the signal and sends the converted signal to the image enhancement chip.
Description
Technical field
The present invention relates to a kind of video capture circuit, particularly a kind of video acquisition processing unit for medical endoscope.
Background technology
Endoscope is a kind of conventional medicine equipment, is become by flexible part, light source and an arrangement of mirrors head group.Through the natural hole of human body, or the minimal incision * that underwent operative is done enters in human body, during use, endoscope is imported the organ of preliminary examination, directly can spy on the change of relevant portion.
Wherein, the quality of picture quality directly affects the result of use of endoscope.Existing general use fujinon electronic video endoscope is observed.Electronic imaging element-CCD (charge coupled device) that common fujinon electronic video endoscope adopts size minimum, object in the chamber that will observe is imaged onto on CCD by small objective lens optical system, then as fibre bundle, the picture signal received is delivered on image processing system by leading, image after last output processing on a monitor, observes and diagnosis for doctor.But still there is the defect that power consumption is too high, image quality is clear not in existing CCD chip.
Meanwhile, existing general use fujinon electronic video endoscope is observed, and the treatment system image after observation being sent to outside connection carries out image procossing.But, during owing to carrying out IMAQ in human body, can due to a variety of causes of inside of human body, and cause occurring noise jamming, brightness cannot regulate or cause due to the color of light image to occur aberration automatically, so cause in the image procossing in later stage, being difficult to the image of rediscover, making doctor be difficult to identification when observing.
Summary of the invention
The invention reside in the shortcoming that overcomes prior art with not enough, the video acquisition processing unit of medical endoscope of a kind of high definition, low-power consumption, low-light (level) is provided.
The present invention is achieved through the following technical solutions: a kind of video acquisition processing unit of medical endoscope, comprises medical endoscope, optics adapter, camera and background host computer; Be provided with video acquisition treatment circuit and a signaling conversion circuit in described camera, described background host computer is provided with an Image Enhancement Circuit; The light transmission that endoscope conducts by described optics adapter, to described video acquisition treatment circuit, is carried out acquisition process and is sent to described signaling conversion circuit, and being sent to this Image Enhancement Circuit by this signaling conversion circuit;
Described optics adapter, comprises dop holder assembly, focusing ring, camera lens, protheca and nested; Described camera lens is high pass light quantity camera lens, and the leading edge of its this high pass light quantity camera lens is provided with focusing jack; The camera lens chamber suitable with high pass light quantity lens shape is provided with in described protheca, the position of its corresponding focusing jack is provided with focusing groove, and protheca is provided with protheca support lugn in the outside, front of focusing groove, described nested corresponding protheca support lugn is provided with nested support lugn, form passage of focusing between protheca support lugn with nested support lugn, this focusing passage is built-in is equipped with slip lens screw; Described focusing ring is set in protheca support lugn and nested support lugn is outside, and focusing ring is connected by the focusing jack of slip lens screw with high pass light quantity camera lens;
Described video acquisition treatment circuit comprises video capture processor and picture processing chip; Described signaling conversion circuit comprises signal conversion chip; Described Image Enhancement Circuit comprises image enhaucament chip; Described signal conversion chip comprises the first signal conversion chip be arranged in camera and the secondary signal conversion chip be arranged in background host computer; Described first signal conversion chip is used for bt1120 signal to be converted to lvds signal; Described secondary signal conversion chip is used for lvds signal to be converted to bt1120 signal;
Video data after collection is sent to picture processing chip and processes by described video capture processor;
Described signal conversion chip comprises the first signal conversion chip and secondary signal conversion chip; Described first signal conversion chip is used for bt1120 signal to be converted to lvds signal; Described secondary signal conversion chip is used for lvds signal to be converted to bt1120 signal;
Picture signal after process is sent to the first signal conversion chip by described picture processing chip, and is sent to secondary signal conversion chip by this first signal conversion chip; Described secondary signal conversion chip is sent to image enhaucament chip after being changed by signal.
Compared to prior art, the present invention, by increasing by a picture processing chip in camera lens part, processes the image gathered, main frame backstage increases an image enhaucament chip, carries out level image enhancing, makes the last image exported more clear.
First, in picture processing chip, be divided into multiple functional module, difference also by each functional module independence co-ordination, can realize low-power consumption, low-light (level), and can be the picture high definition more exported.Meanwhile, a white balance permanent circuit being set in this image processor further, for being fixed by this white balance parameter, without the need to operationally carrying out the adjustment of white balance, thus preventing the phenomenon of aberration interference.
Then, in image enhaucament chip, be also divided into multiple functional module, difference also by each functional module independence co-ordination, can realize the enhancing process to image.Meanwhile, an image border intensifier circuit is set in this image intensifier further, in order to strengthen the definition of image border.
In addition, in order to improve the stability of Signal transmissions, the present invention is by being first converted to lvds signal by bt1120 signal, thus stable transmission, and there is low noise ability.Then, be bt1120 signal by lvds signals revivification, thus ensure that the quality of the picture of follow-up play.
As a further improvement on the present invention, described video capture processor inside comprises: controller, driver, photoreceptor, sampler and follower;
---described controller, it sends triggering signal to driver for receiving outside triggering signal;
---described driver, it for receiving the triggering signal of controller, and drives photoreceptor work;
---described photoreceptor, this light signal for receiving extraneous light signal, and is converted to the signal of telecommunication by it;
---described sampler, the signal of telecommunication processed for carrying out sampling process to the signal of telecommunication of photoreceptor, and is sent to follower by it;
---described follower, it is for being converted to digital signal by this signal of telecommunication, line output of going forward side by side picture processing chip;
Described picture processing chip comprises: data sink, master controller, image processor, data logger;
---described data sink, it is for receiving outside view data;
---described master controller, it is for receiving outside triggering signal, and the operating state of the described data sink of corresponding control, image processor and data logger;
---described image processor, it is for processing image; Described image processor comprises a white balance permanent circuit, and it, for according to the parameter preset, carries out the fixed adjustment of white balance;
---described data logger, it is for exporting the view data after process;
Described first signal conversion chip comprises: controller, data reader, signal format converter, serializer, data logger;
---described controller, it is for receiving outside triggering signal, and the work of control data reader, signal format converter, serializer and data logger;
---described data reader, it for receiving outside bt1120 signal transmission, and is sent to signal format converter;
---described signal format converter, it for bt1120 vision signal being converted to the vision signal of lvds, and is sent to serializer;
---described serializer, it for parallel data is converted to serial data, and is sent to data logger;
---described data logger, for exporting lvds signal data to secondary signal conversion chip;
Described secondary signal conversion chip comprises: controller, data reader, signal format converter, deserializer, data logger;
---described controller, it is for receiving outside triggering signal, and the work of control data reader, signal format converter, deserializer and data logger;
---described data reader, it for the lvds video transfer signal of the first signal conversion chip, and is sent to signal format converter;
---described signal format converter, it for lvds vision signal being converted to the vision signal of bt1120, and is sent to deserializer;
---described deserializer, it for serial data is converted to parallel data, and is sent to data logger;
---described data logger, for bt1120 video signal data is exported;
Described image enhaucament chip comprises: data sink, controller, static memory, image intensifier, data logger and clock generator;
---described data sink, it is for receiving viewdata signal, and is sent to this image intensifier;
---described controller, it is for receiving outer triggering signal, and the operating state of corresponding control data receiver, image enhaucament itself and data logger;
---described static memory, it is for the driving data of memory image booster, to drive the work of this image intensifier;
---described image intensifier, it comprises an image border intensifier circuit; Described image border intensifier circuit is for strengthening the definition of image border;
---described data logger, it for receiving the view data after image intensifier process, and carries out data output;
---described clock generator, it is for being image enhaucament chip clocking.
As a further improvement on the present invention, described video capture processor also comprises a frequency multiplier, and its frequency for the triggering signal inputted outside carries out doubling process, then is sent to controller;
Described picture processing chip also comprises a frequency multiplier, and its frequency for the triggering signal inputted outside carries out doubling process, then is sent to master controller;
Described first signal conversion chip also comprises a phase-locked loop, is connected respectively, for unified integration clock signal with signal format converter and serializer;
Described secondary signal conversion chip also comprises a phase-locked loop, is connected respectively with signal format converter and serializer, for unified integration clock signal;
Described image enhaucament chip also comprises a de-noising processor; The viewdata signal that described data sink receives, is sent to de-noising processor and carries out noise reduction process, then be forwarded to image intensifier.
As a further improvement on the present invention, the image processor in described picture processing chip also comprises an exposure gain circuit, for increasing exposure gain size;
Described first signal conversion chip also comprises a clock data restorer, and it is connected with data reader, for recovering data from the distortion and noise of transmission channel;
Described secondary signal conversion chip also comprises a clock data restorer, and it is connected with data reader, for recovering data from the distortion and noise of transmission channel;
Described image enhaucament chip also comprises a dynamic memory; View data after described de-noising processor process, is first sent to dynamic memory and stores, then be forwarded to image intensifier.
As a further improvement on the present invention, described image processor also comprises an optical detection circuit and flash detection circuit, its brightness for detection image and flashing state, and result of detection is sent to exposure gain circuit;
Described image enhaucament chip also comprises a pixel self adaptation proofreading equipment; View data after process is first sent to described pixel self adaptation proofreading equipment by described image intensifier, carries out pixel and adapts to check and correction, then be sent to data logger by this pixel self adaptation proofreading equipment.
As a further improvement on the present invention, described video capture processor outside is provided with: for receive supply power voltage power port, for outputting video signal video signal port, for export row field signal row field signal port, for receiving reference voltage electricity reference signal port and frequently for receiving the clock signal port of external timing signal;
Described picture processing chip outside is provided with: for receive supply power voltage power port, for receive picture signal receiver port, for outputting video signal video signal port, for export row field signal row field signal port, for receive external timing signal clock signal port, store the data receiver port and of data for receiving the PORT COM of external communication order for receiving;
Described first signal conversion chip outside is provided with: described center processing chip exterior is provided with: for receive supply power voltage power port, for receive bt1120 vision signal receiver port, for exporting the video signal port of lvds vision signal and the row field signal port for exporting row field signal;
Described secondary signal conversion chip outside is provided with: described center processing chip exterior is provided with: for receive supply power voltage power port, for receiving the receiver port of lvds vision signal and the video signal port for exporting bt1120 vision signal;
Described image enhaucament chip exterior is provided with: for receive supply power voltage power port, for receive picture signal receiver port, for outputting video signal video signal port, for export row field signal row field signal port, for receiving the clock signal port of external timing signal and storing the data receiver port of data for receiving.
As a further improvement on the present invention, the power port of described video capture processor is circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity;
The power port of described picture processing chip is circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity.
As a further improvement on the present invention, the row field signal port of described video capture processor is circumscribed with one for providing the resistance of signal strength signal intensity.
As a further improvement on the present invention, the reference signal port of described video capture processor is circumscribed with the electric capacity as voltage electricity frequency reference data.
As a further improvement on the present invention, the external clock circuit of clock signal port of described video capture processor, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port by a debug circuit; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock shake chip power end with to be connected and between inductance and electric capacity; Described debug circuit is made up of resistance and electric capacity; One end of the resistance of this debug circuit is connected with the output of Zhong Zhen, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock signal port is connected between this resistance and electric capacity;
The external clock circuit of described picture processing chip clock signal port, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port by a debug circuit; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock shake chip power end with to be connected and between inductance and electric capacity; Described debug circuit is made up of resistance and electric capacity; One end of the resistance of this debug circuit is connected with the output of Zhong Zhen, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock signal port is connected between this resistance and electric capacity;
The external clock circuit of clock signal port of described image enhaucament chip, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity.
In order to understand better and implement, describe the present invention in detail below in conjunction with accompanying drawing.
Accompanying drawing explanation
Fig. 1 is the structural representation of the video acquisition processing unit for endoscope of the present invention.
Fig. 2 is the section of structure of optics adapter of the present invention.
Fig. 3 is chip connection diagram of the present invention.
Fig. 4 is the internal module connection diagram of video capture processor.
Fig. 5 is the outside port connecting circuit figure of video capture processor.
Fig. 6 is the circuit diagram that the power unit of video capture processor connects.
The voltage place in circuit figure of the 2.7V of Fig. 7 video capture processor.
Fig. 8 is the voltage place in circuit figure of the 1.8V of video capture processor.
Fig. 9 is the voltage place in circuit figure of the 1.2V of video capture processor.
Figure 10 is the partial enlarged drawing of the row field signal of video capture processor.
Figure 11 is the partial enlarged drawing of the reference signal port of video capture processor.
Figure 12 is the circuit diagram of the clock circuit of video capture processor.
Figure 13 is the circuit diagram of the configuration circuit of video capture processor.
Figure 14 is the internal module connection diagram of picture processing chip.
Figure 15 is the circuit module schematic diagram of the image processor of picture processing chip.
Figure 16 is the voltage segment circuit diagram of picture processing chip.
Figure 17 is the outside port circuit diagram of picture processing chip.
Figure 18 is the circuit diagram of the filter circuit of the 3.3V voltage of picture processing chip.
Figure 19 is the circuit diagram of the filter circuit of the 1.8V voltage of picture processing chip.
Figure 20 is the circuit diagram of the filter circuit of the 1.2V voltage of picture processing chip.
Figure 21 is the partial enlarged drawing of the receiver port of picture processing chip.
Figure 22 is the partial enlarged drawing of the video signal port of picture processing chip.
Figure 23 is the partial enlarged drawing of the row field signal port of picture processing chip.
Figure 24 is the schematic diagram of the clock circuit of picture processing chip.
Figure 25 is the schematic diagram of the memory circuit of picture processing chip.
Figure 26 is the partial enlarged drawing of the PORT COM of picture processing chip.
Figure 27 is the internal components connection diagram of the first signal conversion chip.
Figure 28 is the internal module connection diagram of secondary signal conversion chip.
Figure 29 is the outside port connection diagram of the first signal conversion chip.
Figure 30 is the close-up schematic view of the power port of the first signal conversion chip.
Figure 31 is the partial enlarged drawing of the receiver port of the first signal conversion chip.
Figure 32 is the partial enlarged drawing of the video signal port of the first signal conversion chip.
Figure 33 is the partial enlarged drawing of the row field signal port of the first signal conversion chip.
Figure 34 is the outside connecting circuit figure of secondary signal conversion chip.
Figure 35 is the partial enlarged drawing of the receiver port of secondary signal conversion chip.
Figure 36 is the partial enlarged drawing of the video signal port of secondary signal conversion chip.
Figure 37 is the partial enlarged drawing of the row field signal port of secondary signal conversion chip.
Figure 38 is the internal module connection diagram of image enhaucament chip.
Figure 39 is the outside connecting circuit figure of Part I of image enhaucament chip.
Figure 40 is the outside connecting circuit figure of Part II of image enhaucament chip.
Figure 41 is the circuit diagram of the filter circuit of pressure-stabilizing of the 3.3V voltage of image enhaucament chip.
Figure 42 is the power-switching circuit figure that the 3.3V of image enhaucament chip is converted to 1.8V.
Figure 43 is the power-switching circuit figure that the 3.3V of image enhaucament chip is converted to 1.2V.
Figure 44 is the partial enlarged drawing of the receiver port of image enhaucament chip.
Figure 45 a is the partial enlarged drawing of the video signal port Part I of image enhaucament chip.
Figure 45 b is the partial enlarged drawing of the video signal port Part II of image enhaucament chip.
Figure 46 is the circuit diagram of the clock circuit of image enhaucament chip.
Figure 47 is the partial enlarged drawing of the row field signal port of image enhaucament chip.
Embodiment
Refer to Fig. 1, it is the structural representation of video acquisition processing unit of the present invention.The invention provides a kind of video acquisition processing unit of medical endoscope, comprise medical endoscope, optics adapter, camera and background host computer; Be provided with video acquisition treatment circuit and a signaling conversion circuit in described camera, described background host computer is provided with an Image Enhancement Circuit; The light transmission that endoscope conducts by described optics adapter, to described video acquisition treatment circuit, is carried out acquisition process and is sent to described signaling conversion circuit, and being sent to this Image Enhancement Circuit by this signaling conversion circuit.
Refer to Fig. 2, it is the section of structure of optics adapter of the present invention.Described optics adapter 3, comprise dop holder assembly 31, focusing ring 32, camera lens, protheca 34, nested 35, slip lens screw 36, front seal glass 37 and rear seal glass 38, concrete structure is as follows:
Described camera lens is high pass light quantity camera lens 33, and the leading edge of its this high pass light quantity camera lens 33 is provided with focusing jack 331, and described high pass light quantity camera lens 33 is existing industrial high pass light quantity camera lens, and it specifically can adopt Japanese CBCComputarFALENS industrial lens HF series.
Described protheca 34 is connected with dop holder assembly 31, is provided with the camera lens chamber 343 suitable with high pass light quantity camera lens 33 shape in this protheca 34.Further, the position of protheca 34 correspondence focusing jack 331 is provided with focusing groove 342, and it is provided with protheca support lugn 341 in the outside, front of focusing groove 342.Described nested 35 are set in protheca 34 outside, and its corresponding protheca support lugn 341 is provided with nested support lugn 351, forms passage 30 of focusing between protheca support lugn 341 with nested support lugn 351, and this focusing passage is built-in is equipped with slip lens screw 36; Described focusing ring 32 is set in protheca support lugn 341 and nested support lugn 351 is outside, and focusing ring 32 is connected by the focusing jack 331 of slip lens screw 36 with high pass light quantity camera lens 33.The present invention adopts focusing ring 32 directly to realize by slip lens screw 36 pairs of high pass light quantity camera lenses locking of focusing, and focusing precisely flexibly, prevents existing traditional focusing mode from easily skidding and instability.
Further, in order to the embedded sealing realizing high pass light quantity camera lens 33 is installed, the present invention by the following technical solutions:
Described focusing ring 32 is provided with between protheca support lugn 341 and nested support lugn 351 sealing ring 391 that focuses.
Be provided with front seal glass 37 between described protheca and dop holder assembly, and be provided with front sealing ring 392 between this front seal glass 37 and dop holder assembly 31; The front portion of described protheca 34 is provided with for supporting Sealing shield ring 344 before front seal glass 27.
Described protheca 34 rear portion is provided with rear seal glass 38 with between rear portion in nested 35, and is provided with rear sealing ring 393 between this rear seal glass 38 with rear portion in nested 35; The rear portion of described protheca 34 is provided with the rear Sealing shield ring 345 for supporting rear seal glass.
The present invention is by passing through structural improvement, increase focusing ring sealing ring 391, front seal glass 37, front sealing ring 392, rear seal glass 38 and rear sealing ring 393, realize optics adapter to install the embedded sealing of high pass light quantity camera lens 33, effectively prevent camera lens from entering dust or water inlet is hazed.
Refer to Fig. 3, it is the chip connection diagram of invention.Described video acquisition treatment circuit comprises video capture processor 10 and picture processing chip 20; Described signaling conversion circuit comprises signal conversion chip 40; Described Image Enhancement Circuit comprises image enhaucament chip 50; Described signal conversion chip 40 comprises the first signal conversion chip 41 be arranged in camera and the secondary signal conversion chip 42 be arranged in background host computer; Described first signal conversion chip 41 is for being converted to lvds signal by bt1120 signal; Described secondary signal conversion chip 42 is for being converted to bt1120 signal by lvds signal;
Video data after collection is sent to picture processing chip 20 and processes by described video capture processor 10; Picture signal after process is sent to the first signal conversion chip 41 by described picture processing chip 20, and is sent to secondary signal conversion chip 42 by this first signal conversion chip 41; Described secondary signal conversion chip 42 is sent to image enhaucament chip 50 after being changed by signal.
Refer to Fig. 4, it is the internal module connection diagram of video capture processor.Described video capture processor 10 inside comprises: controller 11, driver 12, photoreceptor 13, sampler 14, follower 15 and frequency multiplier 16;
Described controller 11, it sends triggering signal to driver for receiving outside triggering signal;
Described driver 12, it for receiving the triggering signal of controller, and drives photoreceptor work;
Described photoreceptor 13, this light signal for receiving extraneous light signal, and is converted to the signal of telecommunication by it;
Described sampler 14, the signal of telecommunication processed for carrying out sampling process to the signal of telecommunication of photoreceptor, and is sent to follower by it;
Described follower 15, it is for being converted to digital signal by this signal of telecommunication, line output of going forward side by side.
Described frequency multiplier 16, its frequency for the triggering signal inputted outside carries out doubling process, then is sent to controller.Further, conveniently in the requirement of the frequency of utilization of video capture processor, the adjustment being realized frequency by frequency multiplier is amplified.
Please refer to Fig. 5, it is the outside port circuit diagram of video capture processor.In addition in order to adapt to the application of this video capture processor, be provided with in described video capture processor outside: the power port 101 for receiver voltage, the video signal port 102 for outputting video signal, for export row field signal row field signal port one 03, for receiving reference voltage electricity reference signal port one 04 frequently, for receiving the clock signal port 105 of external timing signal and the communication command port one 06 for receiving operate outside mode command.
Please refer to Fig. 6, it is the circuit diagram of the power unit of video capture processor.Concrete, the power unit in video capture processor adopts three kinds of voltages simultaneously, is respectively 2.7V, 1.8V, and 1.2V.
Please refer to Fig. 7-9, it is respectively the circuit diagram of 2.7V, 1.8V and 1.2V of video capture processor.Concrete, the input port 101 of three kinds of voltages of video capture processor is all circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity.Wherein, the voltage place in circuit of 2.7V and 1.8V comprises four electric capacity, and the voltage place in circuit of 1.2V comprises three electric capacity, to filter the interference signal of different frequency.
Refer to Figure 10, it is the interface enlarged drawing of row field signal.Further, described row field signal port one 03 is circumscribed with one for providing the resistance of signal strength signal intensity.By this row field signal, for controlling frequency and the order of video frequency output.Such as: the display frequency of vision signal on screen and DISPLAY ORDER can be controlled, can be from every line output under upper, also can be export from left to right.
Refer to Figure 11, it is the partial enlarged drawing of the reference signal port of video capture processor.Further, described reference signal port one 04 is circumscribed with the electric capacity as voltage electricity frequency reference data.In the present embodiment, described reference signal port has 7, the electric capacity of the external 1uF of each port.
Refer to Figure 12, it is the circuit diagram of the clock circuit of video capture processor.The external clock circuit of described clock signal port 105, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port by a debug circuit; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock shake chip power end with to be connected and between inductance and electric capacity; Described debug circuit is made up of resistance and electric capacity; One end of the resistance of this debug circuit is connected with the output of Zhong Zhen, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock signal port is connected between this resistance and electric capacity.
Refer to Figure 13, it is the circuit diagram of the configuration circuit of video capture processor.Further, described communication command port one 06, it is circumscribed with a mode of operation configuration circuit; Described configuration circuit is made up of two resistant series, and described communication command port is connected between two resistance.
Refer to Figure 14, it is the internal module connection diagram of picture processing chip.Described picture processing chip 20 comprises: data sink 21, master controller 22, image processor 23, data logger 24.
Described data sink 21, it is for receiving outside view data;
Described master controller 22, it is for receiving outside triggering signal, and the operating state of the described data sink of corresponding control, image processor and data logger;
Described image processor 23, it is for processing image.
Described data logger 24, it is for exporting the view data after process.
Further, described video capture processor also comprises a frequency multiplier 25, and its frequency for the triggering signal inputted outside carries out doubling process, then is sent to master controller 22.
Refer to Figure 15, it is the circuit module schematic diagram of the image processor of picture processing chip.Concrete, described image processor 23 comprises a Lens Shading Compensation circuit 231, optical detection circuit 232, flash detection circuit 233, exposure gain circuit 234 and white balance permanent circuit 235.
Described Lens Shading Compensation circuit 231, it compensates process for the shade produced by camera lens.
Described optical detection circuit 232 and flash detection circuit 233, its brightness for detection image and flashing state, and result of detection is sent to exposure gain circuit.
Described exposure gain circuit 234, for increasing exposure gain size.
Described white balance permanent circuit 235, it, for according to the parameter preset, carries out the fixed adjustment of white balance.
Please refer to Figure 16 and Figure 17, it is respectively voltage segment and other outside port circuit diagrams of the video capture processor of picture processing chip.In addition, in order to the application in order to adapt to this video capture processor, be provided with in described video capture processor outside further: for receive supply power voltage power port 201, for receive picture signal receiver port 202, for outputting video signal video signal port 203, for export row field signal row field signal port 204, for receive external timing signal clock signal port 205, for receive store data data receiver port 206 and one for receiving the PORT COM 207 of external communication order.
Refer to Figure 18-20, its power supply being respectively picture processing chip is the circuit diagram of 3.3V, 1.8V and 1.2V.Further, described power port 201 is circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity.Concrete, the external voltage of video capture processor of the present invention comprises: 3.3V, 1.8V and 1.2V tri-kinds.Wherein, 3.3V voltage place in circuit comprises 2 electric capacity, and 1.8V voltage place in circuit comprises 5 electric capacity, and the voltage place in circuit of 1.2V comprises 6 electric capacity, to filter the interference signal of different frequency respectively.
Refer to Figure 21, it is the partial enlarged drawing of the receiver port of picture processing chip.Described receiver port 202 comprises 8 pins, for receiving outside video signal.
Refer to Figure 22, it is the partial enlarged drawing of the video signal port of picture processing chip.Described video signal port 203 comprises the vision signal of two groups of different-formats, carries out doubleway output, plays in real time respectively to facilitate and records.
Refer to Figure 23, it is the partial enlarged drawing of the row field signal port of picture processing chip.Described row field signal port 204 is for controlling frequency and the order of video frequency output.Such as: the display frequency of vision signal on screen and DISPLAY ORDER can be controlled, can be from every line output under upper, also can be export from left to right.
Refer to Figure 24, it is the schematic diagram of the clock circuit of picture processing chip.The external clock circuit of described clock signal port 205, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port by a debug circuit; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock shake chip power end with to be connected and between inductance and electric capacity; Described debug circuit is made up of resistance and electric capacity; One end of the resistance of this debug circuit is connected with the output of Zhong Zhen, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock signal port is connected between this resistance and electric capacity.
Refer to Figure 25, it is the schematic diagram of the memory circuit of picture processing chip.Further, described data receiver port 206 is circumscribed with a memory circuitry, and it comprises a memory, is connected to the filter circuit of the voltage port of this memory, and is connected to the resistance of output port of this memory.
Refer to Figure 26, it is the partial enlarged drawing of the PORT COM of picture processing chip.Described PORT COM 207, for receiving the trigger command of external transmission, carries out work with what trigger this picture processing chip.
Refer to Figure 27, it is the internal components connection diagram of the first signal conversion chip.Described first signal conversion chip 41 comprises: controller 411, data reader 412, signal format converter 413, serializer 414, data logger 415, phase-locked loop 416 and clock data restorer 417;
Described controller 411, it is for receiving outside triggering signal, and the work of control data reader 412, signal format converter 413, serializer 414 and data logger 415;
Described data reader 412, it for receiving outside bt1120 signal transmission, and is sent to signal format converter;
Described signal format converter 413, it for bt1120 vision signal being converted to the vision signal of lvds, and is sent to serializer;
Described serializer 414, it for parallel data is converted to serial data, and is sent to data logger;
Described data logger 415, for exporting lvds signal data to secondary signal conversion chip.
Described phase-locked loop 416, is connected with signal format converter and serializer respectively, for unified integration clock signal.
Described clock data restorer 417, it is connected with data reader, for recovering data from the distortion and noise of transmission channel.
Refer to Figure 28, it is the internal module connection diagram of secondary signal conversion chip.Described secondary signal conversion chip 42 comprises: controller 421, data reader 422, signal format converter 423, deserializer 424, data logger 425, phase-locked loop 426 and clock data restorer 427;
Described controller 421, it is for receiving outside triggering signal, and the work of control data reader 422, signal format converter 423, deserializer 424 and data logger 425;
Described data reader 422, it for the lvds video transfer signal of the first signal conversion chip, and is sent to signal format converter;
Described signal format converter 423, it for lvds vision signal being converted to the vision signal of bt1120, and is sent to deserializer 424;
Described deserializer 424, it for serial data is converted to parallel data, and is sent to data logger;
Described data logger 425, for exporting bt1120 video signal data.
Described phase-locked loop 426, is connected with signal format converter and deserializer respectively, for unified integration clock signal.
Described clock data restorer 427, it is connected with data reader 222, for recovering data from the distortion and noise of transmission channel.
Refer to Figure 29, it is the outside port connection diagram of the first signal conversion chip.Described first signal conversion chip outside is provided with: described center processing chip exterior is provided with: for receive supply power voltage power port 3101, for receive bt1120 vision signal receiver port 3102, for exporting the video signal port 3103 of lvds vision signal and the row field signal port 3104 for exporting row field signal.
Please refer to Figure 30, it is the close-up schematic view of the power port of the first signal conversion chip.Described power port 3101 place is circumscribed with the electric capacity for filtering alternating current.
Refer to Figure 31, it is the partial enlarged drawing of the receiver port of the first signal conversion chip.Described receiver port 3102, it is connected with described data reader 31; Concrete, this receiver port includes 20 pins, for receiving the vision signal of outside bt1120.
Refer to Figure 32, it is the partial enlarged drawing of the video signal port of the first signal conversion chip.Described video signal port 3103 includes 4 output pins, and for exporting lvds vision signal, and this video signal port is connected with this data logger.
Refer to Figure 33, it is the partial enlarged drawing of the row field signal port of the first signal conversion chip.Described row field signal port 3104 includes a line signal output pin and a field signal output pin; Described row field signal port 3104 is for controlling frequency and the order of video frequency output.Such as: the display frequency of vision signal on screen and DISPLAY ORDER can be controlled, can be from every line output under upper, also can be export from left to right.
Refer to Figure 34, it is the outside connecting circuit figure of secondary signal conversion chip.Described secondary signal conversion chip outside is provided with: for receive lvds vision signal receiver port 3201, for exporting video signal port 3202 and the row field signal port 3203 of bt1120 vision signal.
Refer to Figure 35, it is the partial enlarged drawing of the receiver port of secondary signal conversion chip.Described receiver port 3201, it is connected with described data reader 321; Concrete, this receiver port includes 4 pins, for receiving the lvds vision signal that the first signal conversion chip exports.
Refer to Figure 36, it is the partial enlarged drawing of the video signal port of secondary signal conversion chip.Described video signal port 3202 includes 20 output pins, and for exporting bt1120 vision signal, and this video signal port is connected with this data logger.
Refer to Figure 37, it is the partial enlarged drawing of the row field signal port of secondary signal conversion chip.Described row field signal port 3203 includes a line signal output pin and a field signal output pin; Described row field signal port 3104 is for controlling frequency and the order of video frequency output.Such as: the display frequency of vision signal on screen and DISPLAY ORDER can be controlled, can be from every line output under upper, also can be export from left to right.
Refer to Figure 38, it is the internal module connection diagram of image enhaucament chip.Described image enhaucament chip 50 comprises: data sink 51, de-noising processor 52, dynamic memory 53, image intensifier 54, pixel self adaptation proofreading equipment 55, data logger 56, static memory 57, controller 58, vision signal multiplier 59, storage signal multiplier 510, clock generator 511.
Described data sink 51, it is for receiving viewdata signal, and is sent to de-noising processor 52;
The viewdata signal that described data sink 51 receives, is sent to de-noising processor 52 and carries out noise reduction process, then be forwarded to dynamic memory 53.
After the view data of described dynamic memory 53 after receiving de-noising processor 52 process, then be forwarded to image intensifier 54.
Described image intensifier 54, it comprises an image border intensifier circuit; Described image border intensifier circuit is for strengthening the definition of image border.Further, the view data after process is first sent to described pixel self adaptation proofreading equipment 55 by described image intensifier, carries out pixel and adapts to check and correction, then be sent to data logger 56 by this pixel self adaptation proofreading equipment 55.
Described data logger 56, it for receiving the view data after image intensifier process, and carries out data output;
Described static memory 57, it is for the driving data of memory image booster, to drive the work of this image intensifier;
Described controller 58, it is for receiving outer triggering signal, and the operating state of corresponding control data receiver, image enhaucament itself and data logger;
Described clock generator 511, it is for being image enhaucament chip clocking.Further, described clock generator, the clock signal of generation is sent to respectively vision signal multiplier 59 and storage signal multiplier 510, and by this vision signal multiplier 59, clock signal is sent to data sink, by this storage signal multiplier 510, clock signal is sent to dynamic memory and static memory.
Please refer to Figure 39 and Figure 40, it is respectively the outside connecting circuit figure of image enhaucament chip.
Further, described image enhaucament chip exterior is provided with: for receive supply power voltage power port, for receive picture signal receiver port 401, for outputting video signal video signal port 402, for receive external timing signal clock signal port 403, for exporting the row field signal port 404 of row field signal.
Concrete, in the present embodiment, the external voltage of described power port comprises 3.3V, 1.8V and 1.2V tri-kinds of voltages.Refer to Figure 41, it is the circuit diagram of the filter circuit of pressure-stabilizing of 3.3V voltage.Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity.
Refer to Figure 42-43, it is respectively the change-over circuit figure that power-switching circuit figure and 3.3V that 3.3V is converted to 1.8V is converted to 1.2V.In the present embodiment, by a power-switching circuit, the voltage of 3.3V is converted to respectively the voltage of 1.8V and 1.2V.Concrete, described power-switching circuit comprises a power conversion chip; The voltage of the input access 3.3V of described power conversion chip, output exports the voltage of 1.8V and 1.2V respectively, to power to image enhaucament chip.
Refer to Figure 44, it is the partial enlarged drawing of the receiver port of image enhaucament chip.Described receiver port 401 comprises 20 signal pins, is connected with the data sink 51 of inside, for receiving the picture signal of input.
Refer to Figure 45 a and 45b, it is respectively the Part I of the video signal port of image enhaucament chip and the partial enlarged drawing of Part II.Described video signal port 402 comprises 20 signal pins, and it is connected, for output image signal with inner data logger 56.
Refer to Figure 46, it is the circuit diagram of the clock circuit of image enhaucament chip.Further, the external clock circuit of described clock signal port 403, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity.
Refer to Figure 47, it is the partial enlarged drawing of the row field signal port of image enhaucament chip.Described row field signal port 404 comprises a row signal pins and a field signal pin.Described row field signal port 404 is for controlling frequency and the order of video frequency output.Such as: the display frequency of vision signal on screen and DISPLAY ORDER can be controlled, can be from every line output under upper, also can be export from left to right.
Below the course of work of video acquisition treatment circuit of the present invention is described:
S11: carry out circuit access according to above-mentioned requirement by the outside port of this video capture processor, picture processing chip, signal conversion chip and image enhaucament chip;
S12: when video capture processor is energized, first carries out multiplication by this frequency multiplier by input voltage frequency and regulates, to adapt to current operating frequency;
S13: described controller 11 sends triggering signal to driver 12, drives photoreceptor 13 to work by driver 12;
S14: when light is irradiated on photoreceptor 13, is converted to the signal of telecommunication by this photoreceptor 13 by light signal, and transfers to sampler 14;
S15: when sampler 14 receives the signal of telecommunication from photoreceptor 13, carries out sampling process to this signal of telecommunication, and the signal of telecommunication processed is sent to follower 15;
S16: finally by described follower 15, this signal of telecommunication is converted to digital signal, line output of going forward side by side is to picture processing chip 30.
S17: described data sink 21 receives outside view data;
S8: described image processor 23 pairs of images process.Specifically respectively by described Lens Shading Compensation circuit 231, the shade that camera lens produces is compensated process; By brightness and the flashing state of described optical detection circuit 232 and flash detection circuit 233 detection image, and result of detection is sent to exposure gain circuit; Then exposure gain size is increased by described exposure gain circuit 234.Last again by described white balance permanent circuit 35 according to default parameter, carry out the fixed adjustment of white balance.
S19: the view data after process carries out exporting the first signal conversion chip 41 to by described data logger 24.
S20: the data reader 412 of described first signal conversion chip receives the bt1120 signal transmission of picture processing chip output, and is sent to signal format converter;
S21: bt1120 vision signal is converted to the vision signal of lvds by described signal format converter 413, and is sent to serializer 414;
S22: parallel data is converted to serial data by described serializer 414, and is sent to data logger;
S23: described data logger 415, for exporting lvds signal data to secondary signal conversion chip.
S24: by the lvds video transfer signal of the data reader 422 in secondary signal conversion chip by the first signal conversion chip, and be sent to signal format converter;
S25: lvds vision signal is converted to the vision signal of bt1120 by described signal format converter 423, and is sent to deserializer;
S26: serial data is converted to parallel data by described deserializer 424, and is sent to data logger;
S27: described data logger 425 exports bt1120 video signal data to image enhaucament chip 50.
S28: receive outside view data by the data sink 51 of image enhaucament chip 50;
S29: described data sink 51, receives viewdata signal, and is sent to de-noising processor 52;
S30: described de-noising processor 52 carries out noise reduction process, then is forwarded to dynamic memory 53.
S31: after the view data of described dynamic memory 53 after receiving de-noising processor 52 process, then be forwarded to image intensifier 54.
S32: described image intensifier 54, it comprises an image border intensifier circuit; Described image border intensifier circuit strengthens the definition of image border.View data after process is first sent to described pixel self adaptation proofreading equipment 55 by described image intensifier.
S33: described pixel self adaptation proofreading equipment 55 carries out pixel and adapts to check and correction, then is sent to data logger 56.
S34: the view data after process exports by described data logger 56.
Compared to prior art, the present invention, by increasing by a picture processing chip in camera lens part, processes the image gathered, main frame backstage increases an image enhaucament chip, carries out level image enhancing, makes the last image exported more clear.
First, in picture processing chip, be divided into multiple functional module, difference also by each functional module independence co-ordination, can realize low-power consumption, low-light (level), and can be the picture high definition more exported.Meanwhile, a white balance permanent circuit being set in this image processor further, for being fixed by this white balance parameter, without the need to operationally carrying out the adjustment of white balance, thus preventing the phenomenon of aberration interference.
Then, in image enhaucament chip, be also divided into multiple functional module, difference also by each functional module independence co-ordination, can realize the enhancing process to image.Meanwhile, an image border intensifier circuit is set in this image intensifier further, in order to strengthen the definition of image border.
In addition, in order to improve the stability of Signal transmissions, the present invention is by being first converted to lvds signal by bt1120 signal, thus stable transmission, and there is low noise ability.Then, be bt1120 signal by lvds signals revivification, thus ensure that the quality of the picture of follow-up play.
The present invention is not limited to above-mentioned execution mode, if do not depart from the spirit and scope of the present invention to various change of the present invention or distortion, if these are changed and distortion belongs within claim of the present invention and equivalent technologies scope, then the present invention is also intended to comprise these changes and distortion.
Claims (10)
1. a video acquisition processing unit for medical endoscope, is characterized in that: comprise medical endoscope, optics adapter, camera and background host computer; Be provided with video acquisition treatment circuit and a signaling conversion circuit in described camera, described background host computer is provided with an Image Enhancement Circuit; The light transmission that endoscope conducts by described optics adapter, to described video acquisition treatment circuit, is carried out acquisition process and is sent to described signaling conversion circuit, being sent to this Image Enhancement Circuit by this signaling conversion circuit;
Described optics adapter, comprises dop holder assembly, focusing ring, camera lens, protheca and nested; Described camera lens is high pass light quantity camera lens, and the leading edge of its this high pass light quantity camera lens is provided with focusing jack; The camera lens chamber suitable with high pass light quantity lens shape is provided with in described protheca, the position of its corresponding focusing jack is provided with focusing groove, and protheca is provided with protheca support lugn in the outside, front of focusing groove, described nested corresponding protheca support lugn is provided with nested support lugn, form passage of focusing between protheca support lugn with nested support lugn, this focusing passage is built-in is equipped with slip lens screw; Described focusing ring is set in protheca support lugn and nested support lugn is outside, and focusing ring is connected by the focusing jack of slip lens screw with high pass light quantity camera lens;
Described video acquisition treatment circuit comprises video capture processor and picture processing chip; Described signaling conversion circuit comprises signal conversion chip; Described Image Enhancement Circuit comprises image enhaucament chip; Described signal conversion chip comprises the first signal conversion chip be arranged in camera and the secondary signal conversion chip be arranged in background host computer; Described first signal conversion chip is used for bt1120 signal to be converted to lvds signal; Described secondary signal conversion chip is used for lvds signal to be converted to bt1120 signal;
Video data after collection is sent to picture processing chip and processes by described video capture processor;
Picture signal after process is sent to the first signal conversion chip by described picture processing chip, and is sent to secondary signal conversion chip by this first signal conversion chip; Described secondary signal conversion chip is sent to image enhaucament chip after being changed by signal.
2. the video acquisition processing unit of medical endoscope according to claim 1, is characterized in that:
Described video capture processor inside comprises: controller, driver, photoreceptor, sampler and follower;
---described controller, it sends triggering signal to driver for receiving outside triggering signal;
---described driver, it for receiving the triggering signal of controller, and drives photoreceptor work;
---described photoreceptor, this light signal for receiving extraneous light signal, and is converted to the signal of telecommunication by it;
---described sampler, the signal of telecommunication processed for carrying out sampling process to the signal of telecommunication of photoreceptor, and is sent to follower by it;
---described follower, it is for being converted to digital signal by this signal of telecommunication, line output of going forward side by side picture processing chip;
Described picture processing chip comprises: data sink, master controller, image processor, data logger;
---described data sink, it is for receiving outside view data;
---described master controller, it is for receiving outside triggering signal, and the operating state of the described data sink of corresponding control, image processor and data logger;
---described image processor, it is for processing image; Described image processor comprises a white balance permanent circuit, and it, for according to the parameter preset, carries out the fixed adjustment of white balance;
---described data logger, it is for exporting the view data after process;
Described first signal conversion chip comprises: controller, data reader, signal format converter, serializer, data logger;
---described controller, it is for receiving outside triggering signal, and the work of control data reader, signal format converter, serializer and data logger;
---described data reader, it for receiving outside bt1120 signal transmission, and is sent to signal format converter;
---described signal format converter, it for bt1120 vision signal being converted to the vision signal of lvds, and is sent to serializer;
---described serializer, it for parallel data is converted to serial data, and is sent to data logger;
---described data logger, for exporting lvds signal data to secondary signal conversion chip;
Described secondary signal conversion chip comprises: controller, data reader, signal format converter, deserializer, data logger;
---described controller, it is for receiving outside triggering signal, and the work of control data reader, signal format converter, deserializer and data logger;
---described data reader, it for the lvds video transfer signal of the first signal conversion chip, and is sent to signal format converter;
---described signal format converter, it for lvds vision signal being converted to the vision signal of bt1120, and is sent to deserializer;
---described deserializer, it for serial data is converted to parallel data, and is sent to data logger;
---described data logger, for bt1120 video signal data is exported;
Described image enhaucament chip comprises: data sink, controller, static memory, image intensifier, data logger and clock generator;
---described data sink, it is for receiving viewdata signal, and is sent to this image intensifier;
---described controller, it is for receiving outer triggering signal, and the operating state of corresponding control data receiver, image enhaucament itself and data logger;
---described static memory, it is for the driving data of memory image booster, to drive the work of this image intensifier;
---described image intensifier, it comprises an image border intensifier circuit; Described image border intensifier circuit is for strengthening the definition of image border;
---described data logger, it for receiving the view data after image intensifier process, and carries out data output;
---described clock generator, it is for being image enhaucament chip clocking.
3. the video acquisition processing unit of medical endoscope according to claim 1, it is characterized in that: described video capture processor also comprises a frequency multiplier, its frequency for the triggering signal inputted outside carries out doubling process, then is sent to controller;
Described picture processing chip also comprises a frequency multiplier, and its frequency for the triggering signal inputted outside carries out doubling process, then is sent to master controller;
Described first signal conversion chip also comprises a phase-locked loop, is connected respectively, for unified integration clock signal with signal format converter and serializer;
Described secondary signal conversion chip also comprises a phase-locked loop, is connected respectively with signal format converter and serializer, for unified integration clock signal;
Described image enhaucament chip also comprises a de-noising processor; The viewdata signal that described data sink receives, is sent to de-noising processor and carries out noise reduction process, then be forwarded to image intensifier.
4. the image processing circuit of medical endoscope according to claim 1, is characterized in that: the image processor in described picture processing chip also comprises an exposure gain circuit, for increasing exposure gain size;
Described first signal conversion chip also comprises a clock data restorer, and it is connected with data reader, for recovering data from the distortion and noise of transmission channel;
Described secondary signal conversion chip also comprises a clock data restorer, and it is connected with data reader, for recovering data from the distortion and noise of transmission channel;
Described image enhaucament chip also comprises a dynamic memory; View data after described de-noising processor process, is first sent to dynamic memory and stores, then be forwarded to image intensifier.
5. the image processing circuit of medical endoscope according to claim 3, it is characterized in that: described image processor also comprises an optical detection circuit and flash detection circuit, its brightness for detection image and flashing state, and result of detection is sent to exposure gain circuit;
Described image enhaucament chip also comprises a pixel self adaptation proofreading equipment; View data after process is first sent to described pixel self adaptation proofreading equipment by described image intensifier, carries out pixel and adapts to check and correction, then be sent to data logger by this pixel self adaptation proofreading equipment.
6. the video acquisition processing unit of medical endoscope according to claim 1, is characterized in that: described video capture processor outside is provided with: for receive supply power voltage power port, for outputting video signal video signal port, for export row field signal row field signal port, for receiving reference voltage electricity reference signal port and frequently for receiving the clock signal port of external timing signal;
Described picture processing chip outside is provided with: for receive supply power voltage power port, for receive picture signal receiver port, for outputting video signal video signal port, for export row field signal row field signal port, for receive external timing signal clock signal port, store the data receiver port and of data for receiving the PORT COM of external communication order for receiving;
Described first signal conversion chip outside is provided with: described center processing chip exterior is provided with: for receive supply power voltage power port, for receive bt1120 vision signal receiver port, for exporting the video signal port of lvds vision signal and the row field signal port for exporting row field signal;
Described secondary signal conversion chip outside is provided with: described center processing chip exterior is provided with: for receive supply power voltage power port, for receiving the receiver port of lvds vision signal and the video signal port for exporting bt1120 vision signal;
Described image enhaucament chip exterior is provided with: for receive supply power voltage power port, for receive picture signal receiver port, for outputting video signal video signal port, for export row field signal row field signal port, for receiving the clock signal port of external timing signal and storing the data receiver port of data for receiving.
7. the video acquisition processing unit of medical endoscope according to claim 6, is characterized in that: the power port of described video capture processor is circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity;
The power port of described picture processing chip is circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity.
8. the video acquisition processing unit of medical endoscope according to claim 6, is characterized in that: the row field signal port of described video capture processor is circumscribed with one for providing the resistance of signal strength signal intensity.
9. the video acquisition processing unit of medical endoscope according to claim 6, is characterized in that: the reference signal port of described video capture processor is circumscribed with the electric capacity as voltage electricity reference data frequently.
10. the video acquisition processing unit of medical endoscope according to claim 6, is characterized in that: the external clock circuit of clock signal port of described video capture processor, and it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port by a debug circuit; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock shake chip power end with to be connected and between inductance and electric capacity; Described debug circuit is made up of resistance and electric capacity; One end of the resistance of this debug circuit is connected with the output of Zhong Zhen, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock signal port is connected between this resistance and electric capacity;
The external clock circuit of described picture processing chip clock signal port, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port by a debug circuit; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock shake chip power end with to be connected and between inductance and electric capacity; Described debug circuit is made up of resistance and electric capacity; One end of the resistance of this debug circuit is connected with the output of Zhong Zhen, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock signal port is connected between this resistance and electric capacity;
The external clock circuit of clock signal port of described image enhaucament chip, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity.
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| CN204863072U (en) * | 2015-06-30 | 2015-12-16 | 广东实联医疗器械有限公司 | Medical endoscope's video acquisition processing apparatus |
Cited By (1)
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| CN113110254A (en) * | 2021-05-20 | 2021-07-13 | 美钻石油钻采系统(上海)有限公司 | Oil gas signal processing and control system of ocean platform and communication device thereof |
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