CN105321942B - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN105321942B
CN105321942B CN201510274081.9A CN201510274081A CN105321942B CN 105321942 B CN105321942 B CN 105321942B CN 201510274081 A CN201510274081 A CN 201510274081A CN 105321942 B CN105321942 B CN 105321942B
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CN105321942A (zh
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廖文甲
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Anchorage Semiconductor Co ltd
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Delta Optoelectronics Inc
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/22—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
    • H03F1/223—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively with MOSFET's
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/546—A tunable capacitance being present in an amplifier circuit

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Abstract

本发明公开了半导体装置，包含第一晶体管与第二晶体管。第一晶体管包含第一电极、第二电极以及控制电极。第二电极用以接收第一预定电压。控制电极用以接收输入信号。第二晶体管包含第一电极、第二电极、控制电极以及控制垫。第二晶体管的第一电极用以接收第二预定电压。第二晶体管的第二电极电性耦接至第一晶体管的第一电极。控制垫设置于第二晶体管的第一电极与第二晶体管的控制电极之间，并用以接收第一调整信号。此半导体装置在电路使用上可被等效成一由两元件构成的串叠电路，上述串叠电路可提通过多个设置方式调整等效栅极‑漏极电容，因此可被广泛地利用于对导通损失有不同需求的应用上。

Description

半导体装置
技术领域
本发明涉及一种半导体装置，尤其涉及具有可调容值的串叠电路构成的半导体装置。
背景技术
近年来，对于能够提供高功率的功率电路的需求大幅上升。较高的功率能够让功率电路操作更加有效率。
功率晶体管能够承受高电压与高电流，故常被应用于功率电路中。然而，在制造过程中，在功率晶体管中会大致形成多个寄生电容。多个寄生电容将导致功率电路的导通损失。如此一来，功率电路的操作效率会下降。
发明内容
为了解决上述问题，本公开内容的一实施方式提出一种半导体装置。半导体装置包含第一晶体管与第二晶体管。第一晶体管包含第一电极、第二电极以及控制电极。第二电极用以接收第一预定电压。控制电极用以接收输入信号。第二晶体管包含第一电极、第二电极、控制电极以及控制垫。第二晶体管的第一电极用以接收第二预定电压。第二晶体管的第二电极电性耦接至第一晶体管的第一电极。控制垫设置于第二晶体管的第一电极与第二晶体管的控制电极之间，并用以接收第一调整信号。
本公开内容的另一实施方式提出一种半导体装置。半导体装置包含基板、高压晶体管、低压晶体管、第一端、第二端、第二端以及第四端。高压晶体管设置于基板上。高压晶体管包含第一源极电极、第一漏极电极、第一栅极电极以及场效电板，且场效电板设置于第一栅极电极与第一漏极电极之间。低压晶体管设置于基板上。低压晶体管包含第二源极电极、第二漏极电极以及第二栅极电极，且第二漏极电极电性耦接至第一源极电极。第一端耦接至第一漏极电极。第二端耦接至该第二源极电极。第三端耦接至第二栅极电极，以接收控制信号。第四端耦接至高压晶体管的场效电板，以控制半导体装置的容值。
综上所述，本公开内容所示的串叠电路构成的半导体装置，可利用数个设置方式调整等效栅极-漏极电容。因此，串叠电路可被广泛地利用于对导通损失有不同需求的应用上。
附图说明
为让本公开内容的上述和其他目的、特征、优点与实施例能更明显易懂，附图说明书附图的说明如下：
图1为根据一些类似技术所绘示的一种功率装置的示意图；
图2A为根据本公开内容的一实施例所绘示的一种串叠电路的剖面示意图；
图2B为根据本公开内容的一实施例所绘示的图2A中的串叠电路的等效栅极-漏极电容与调整信号的关系示意图；
图3为根据本公开内容的一实施例所绘示的一种串叠电路的剖面示意图；
图4为根据本公开内容的一实施例所绘示的一种串叠电路的剖面示意图；以及
图5为根据本公开内容的一实施例所绘示的一种串叠电路的剖面示意图。
附图标记说明：
100：功率装置
102：空乏型晶体管
104：增强型晶体管
Cgd、Cgd(0)：等效栅极-漏极电容
VG1：预期电压
VIN：输入信号
200、300、400、500：串叠电路
M1、M2：晶体管
G1、G2：栅极电极
D1、D2：漏极电极
S1、S2：源极电极
202、204：半导体层
206：基板
208：保护层
210：控制垫
V1、V2：预定电压
VA1、VA2：调整信号
VDS：电压
具体实施方式
下文举实施例配合附图说明书附图作详细说明，但所提供的实施例并非用以限制本发明所涵盖的范围，而结构操作的描述非用以限制其执行的顺序，任何由元件重新组合的结构，所产生具有均等功效的装置，皆为本发明所涵盖的范围。此外，附图仅以说明为目的，并未依照原尺寸作图。为使便于理解，下述说明中相同元件将以相同的符号标示来说明。
当一个元件被称为“在…上”时，它可泛指该元件直接在其他元件上，也可以是有其他元件存在于两者之中。相反地，当一个元件被称为“直接在”另一元件，它是不能有其他元件存在于两者的中间。如本文所用，词汇“和/或”包含了列出的关联项目中的一个或多个的任何组合。
另外，关于本文中所使用的“耦接”或“连接”，均可指二或多个元件相互直接作实体或电性接触，或是相互间接作实体或电性接触，也可指二或多个元件相互操作或动作。
关于本文中所使用的“第一”、“第二”、…等，并非特别指称次序或顺位的意思，也非用以限定本发明，其仅仅是为了区别以相同技术用语描述的元件或操作而已。
图1为根据一些类似技术所绘示的一种功率装置100的示意图。如图1所示，功率装置100包含空乏型晶体管102与增强型晶体管104。空乏型晶体管102串叠耦接至增强型晶体管104。在实际应用上，空乏型晶体管102的栅极电极为浮接或设置以接收预期电压VG1。增强型晶体管104的栅极电极设置以接收输入信号VIN，以进行后续操作。
如先前所述，多个寄生电容存在于功率装置100。举例而言，如图1所示，等效栅极-漏极电容Cgd大致形成于功率装置100，其容值可利用一些等效电容模型的分析推估而得。在实际应用中，功率装置100的切换损失与等效栅极-漏极电容Cgd相关。因此，等效栅极-漏极电容Cgd需要被调整以符合实际应用上的不同需求。
请参照图2A，图2A为根据本公开内容的一实施例所绘示的一种串叠电路200的剖面示意图。如图2A所示，串叠电路200包含晶体管M1与晶体管M2。晶体管M1包含栅极电极G1、漏极电极D1、源极电极S1与半导体层202。晶体管M2包含栅极电极G2、漏极电极D2、源极电极S2、半导体层204、基板206、保护层208以及控制垫210。
在本公开内容的各个实施例中，串叠电路200大致形成具有耐高压特性的合并式串叠晶体管。在一些实施例中，晶体管M1为低压晶体管，且晶体管M2为高压晶体管。于另一些实施例中，晶体管M1为增强型晶体管(也就是常闭型(normally-OFF)晶体管)，且晶体管M2为空乏型晶体管(也就是常通型(normally-ON)晶体管)。举例而言，半导体层202包含硅层，且半导体层204可由III族氮化物材料或任意的III-V族化合物组成。在一实施例中，半导体层204包含氮基半导体层，例如为堆叠于氮化镓层上的氮化铝镓层，且晶体管M2为具有高电子迁移率的晶体管(HEMT)。
于又一些实施例中，晶体管M1与晶体管M2包含任意种类的场效晶体管。各种类型的晶体管M1与晶体管M2皆应视为本公开内容所涵盖的范围。
详细而言，如图2A所示，栅极电极G1设置于源极电极S1与漏极电极D1之间，且栅极电极G2设置于源极电极S2与漏极电极D2之间。栅极电极G2、源极电极S2与漏极电极D2形成于半导体层204上，且半导体层204设置于基板206上。于一些实施例中，晶体管M2可整合地形成于基板206上。
如图2A所示，晶体管M1的栅极电极G1设置以接收输入信号VIN，晶体管M1的漏极电极D1电性耦接至晶体管M2的源极电极S2，且晶体管M1的源极电极S1用以接收预定电压V1。举例而言，在一些实施例中，晶体管M1的源极电极S1可接地以接收地电压。晶体管M2的漏极电极D2用以接收预定电压V2(例如为供应电压)。
于此实施例中，晶体管M2的栅极电极G2电性耦接至晶体管M1的源极电极S1。如此，当输入信号VIN处于低电压电平时，晶体管M1会被关断，负电压将会相应产生于晶体管M2的源极电极S2与栅极电极G2之间，以关断晶体管M2。如此一来，当输入信号VIN处于低电压电平时，串叠电路200能够被完全关闭。
再者，如图2A所示，保护层208设置于半导体层204上，以避免晶体管M2发生退化。于一些实施例中，保护层208是由二氧化硅、氮化硅等材料组成。
控制垫210设置于保护层208，并位于漏极电极D2与栅极电极G2之间。于各个实施例中，控制垫210包含场效电板，但不以此为限。在此实施例中，控制垫210用以接收调整信号VA1，以控制串叠电路200的容值。
相较于图1所示的功率装置100，额外的寄生电容(未绘示)会大致由控制垫210产生，且此额外的寄生电容与晶体管M2中的其他寄生电容可被调整信号VA1控制。经由此设置方式，串叠电路200的等效栅极-漏极电容Cgd可被调整信号VA1所调整。因此，串叠电路200可被广泛地应用于不同的应用中。
此外，在本公开内容的一些实施例中，晶体管M1与晶体管M2可形成于单一晶片上。举例而言，以整体来说，串叠电路200的第一端耦接至漏极电极D2，串叠电路200的第二端耦接至源极电极S1，串叠电路200的第三端耦接至栅极电极G1，且串叠电路200的第四端耦接至控制垫210。因此，预定电压V1、V2、输入信号VIN以及调整信号VA1可经由晶片的多个端点输入至串叠电路200中所对应的多个电极。或者，在本公开内容中的另一些实施例中，晶体管M1可形成于一晶片上，且晶体管M2可形成于另一晶片上，且前述两个晶片可封装于单一封装体内。此封装体包含金属基板、导线架、印刷电路板或类似物。经由此设置方式，串叠电路200能够被高度整合。
请参照图2B，图2B为根据本公开内容的一实施例所绘示的图2A中的串叠电路200的等效栅极-漏极电容CGD与调整信号VA1的关系示意图。
如图2B所示，图2B中的电压VDS为串叠电路200中的漏极电极D2与源极电极S1之间的电压。Cgd(0)为当电压VDS为0伏特时串叠电路200的等效栅极-漏极电容Cgd的容值。如图2B所示，等效栅极-漏极电容Cgd的容值可根据电压VDS而经由不同的调整信号VA1调整。举例来说，若串叠电路200的电压VDS约为20伏特，调整信号VA1可设置为低于0伏特以获得较低的等效栅极-漏极电容Cgd。或者，若串叠电路200的电压VDS约为20伏特，则调整信号VA1可设置为高于0伏特以获得较大的等效栅极-漏极电容Cgd。本领域技术人员可根据实际应用设置调整信号VA1的电压。
请参照图3，图3为根据本公开内容的一实施例所绘示的一种串叠电路300的剖面示意图。
相较于图2A中的串叠电路200，于此例中，串叠电路300中的基板206还电性耦接至控制垫210。因此，通过此设置方式，可达到不同范围容值的等效栅极-漏极电容Cgd。
请参照图4，图4为根据本公开内容的一实施例所绘示的一种串叠电路400的剖面示意图。
相较于串叠电路200，如图4所示，串叠电路400中的基板206还用以接收调整信号VA2。形成于基板206与源极电极S2之间的多个寄生电容、形成于基板206与漏极电极D2之间的多个寄生电容、形成于基板206与控制垫210之间的多个寄生电容可经由调整信号VA2控制。
换句话说，于此例中，串叠电路400的的等效栅极-漏极电容Cgd可同时经由调整信号VA1与调整信号VA2控制。因此，通过设置调整信号VA2，可达到不同范围容值的等效栅极-漏极电容Cgd。
请参照图5，图5为根据本公开内容的一实施例所绘示的一种串叠电路500的剖面示意图。
相较于前述的各实施例，如图5所示，串叠电路500的栅极电极G2电性耦接至控制垫210，而非源极电极S1。于此例中，通过施加调整信号VA1至栅极电极G2与控制垫210，晶体管M2的栅极电极G2与漏极电极D2之间的栅极-漏极电容(未绘示)可被调整。因此，通过此设置方式，串叠电路500中的等效栅极-漏极电容Cgd能够进一步地被调整。
图2A、图3、图4与图5中所示的控制垫210的结构或设置方式仅为例示。能够用来调整等效栅极-漏极电容CGD的控制垫210的各种设置方式或上述各实施例的组合，皆应视为本公开内容所涵盖的范围内。
综上所述，本公开内容所示的串叠电路可利用数个设置方式调整等效栅极-漏极电容Cgd。因此，串叠电路可被广泛地利用于对导通损失有不同需求的应用上。
虽然本发明已以实施方式公开如上，然其并非用以限定本发明，任何本领域技术人员，在不脱离本发明的精神和范围内，当可作各种的变动与润饰，因此本发明的保护范围当视所附的权利要求所界定者为准。

Claims (19)

1.一种半导体装置，其特征在于，包含：
一第一晶体管，包含：
一第一电极；
一第二电极，用以接收一第一预定电压；以及
一控制电极，用以接收一输入信号；以及
一第二晶体管，包含：
一第一电极，用以接收一第二预定电压；
一第二电极，电性耦接至该第一晶体管的该第一电极；
一控制电极；以及
一控制垫，设置于该第二晶体管的该第一电极与该第二晶体管的该控制电极之间，并用以接收一第一调整信号。
2.如权利要求1的半导体装置，其特征在于，该第二晶体管的该控制电极电性耦接至该第一晶体管的该第二电极。
3.如权利要求1的半导体装置，其特征在于，该第二晶体管设置于一基板上，且该基板电性耦接至该第二晶体管的该控制垫。
4.如权利要求1的半导体装置，其特征在于，该第二晶体管设置于一基板上，且该基板用以接收一第二调整信号。
5.如权利要求1的半导体装置，其特征在于，该第二晶体管的该控制电极电性耦接至该控制垫。
6.如权利要求1的半导体装置，其特征在于，该第一晶体管为一常通型晶体管，且该第二晶体管为一常闭型晶体管。
7.如权利要求1的半导体装置，其中该控制垫包含一场效电板。
8.如权利要求1的半导体装置，其特征在于，该第一晶体管与该第二晶体管形成于同一晶片。
9.如权利要求1的半导体装置，其特征在于，该第一晶体管形成于一第一晶片，该第二晶体管形成于一第二晶片，且该第一晶片与该第二晶片封装于一封装体内。
10.如权利要求9的半导体装置，其特征在于，该封装体包含一金属基板或一导线架。
11.一种半导体装置，其特征在于，包含：
一基板；
一高压晶体管，设置于该基板上，该高压晶体管包含一第一源极电极、一第一漏极电极、一第一栅极电极以及一场效电板，且该场效电板设置于该第一栅极电极与该第一漏极电极之间；
一低压晶体管，设置于该基板上，该低压晶体管包含一第二源极电极、一第二漏极电极以及一第二栅极电极，且该第二漏极电极电性耦接至该第一源极电极；
一第一端耦接至该第一漏极电极；
一第二端耦接至该第二源极电极；
一第三端耦接至该第二栅极电极，以接收一控制信号；以及
一第四端耦接至该高压晶体管的该场效电板，以控制该半导体装置的一容值。
12.如权利要求11的半导体装置，其特征在于，该第一栅极电极电性耦接至该第二源极电极。
13.如权利要求11的半导体装置，其特征在于，该高压晶体管与该低压晶体管形成于同一晶片上。
14.如权利要求11的半导体装置，其特征在于，该高压晶体管形成于一第一晶片上，该低压晶体管形成于一第二晶片上，且该第一晶片与该第二晶片封装于一封装体内。
15.如权利要求14的半导体装置，其特征在于，该封装体包含一金属基板或一导线架。
16.如权利要求11的半导体装置，其特征在于，该高压晶体管为一常通型晶体管，且该低压晶体管为一常闭型晶体管。
17.如权利要求11的半导体装置，其特征在于，该高压晶体管为一氮基高电子迁移率晶体管，且该低压晶体管为一硅基晶体管。
18.如权利要求11的半导体装置，其特征在于，该第一栅极电极电性耦接至该高压晶体管的该场效电板。
19.如权利要求11的半导体装置，其特征在于，该高压晶体管的该场效电板耦接至该基板。
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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9991225B2 (en) * 2015-06-23 2018-06-05 Texas Instruments Incorporated High voltage device with multi-electrode control
US10205024B2 (en) * 2016-02-05 2019-02-12 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure having field plate and associated fabricating method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4864373A (en) * 1985-01-16 1989-09-05 Fujitsu Limited Semiconductor circuit device with voltage clamp
EP1085653A1 (en) * 1999-09-13 2001-03-21 Chartered Semiconductor Manufacturing Pte Ltd. A technique to generate negative conductance in CMOS tuned cascode RF amplifier
CN101238560A (zh) * 2005-06-10 2008-08-06 日本电气株式会社 场效应晶体管
CN102598095A (zh) * 2009-11-13 2012-07-18 株式会社半导体能源研究所 显示器件以及包含显示器件的电子器件

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4443715A (en) * 1982-03-25 1984-04-17 Gte Laboratories Incorporated Driver circuit
US5621362A (en) * 1996-02-05 1997-04-15 Motorola, Inc. Cascode oscillator having optimum phase noise and bandwidth performance
US6995616B2 (en) * 2003-10-14 2006-02-07 Broadcom Corporation Power amplifier having cascode architecture with separately controlled MOS transistor and parasitic bipolar transistor
US7501670B2 (en) * 2007-03-20 2009-03-10 Velox Semiconductor Corporation Cascode circuit employing a depletion-mode, GaN-based FET
US7982239B2 (en) 2007-06-13 2011-07-19 Northrop Grumman Corporation Power switching transistors
US7960997B2 (en) * 2007-08-08 2011-06-14 Advanced Analogic Technologies, Inc. Cascode current sensor for discrete power semiconductor devices
US20120175679A1 (en) * 2011-01-10 2012-07-12 Fabio Alessio Marino Single structure cascode device
US20120262220A1 (en) * 2011-04-13 2012-10-18 Semisouth Laboratories, Inc. Cascode switches including normally-off and normally-on devices and circuits comprising the switches
US8536931B2 (en) 2011-06-17 2013-09-17 Rf Micro Devices, Inc. BI-FET cascode power switch
KR20130004707A (ko) 2011-07-04 2013-01-14 삼성전기주식회사 질화물 반도체 소자, 질화물 반도체 소자의 제조방법 및 질화물 반도체 파워소자
US8866253B2 (en) * 2012-01-31 2014-10-21 Infineon Technologies Dresden Gmbh Semiconductor arrangement with active drift zone
EP2693639B1 (en) * 2012-07-30 2015-09-09 Nxp B.V. Cascoded semiconductor devices
US9035690B2 (en) * 2012-08-30 2015-05-19 Infineon Technologies Dresden Gmbh Circuit arrangement with a first semiconductor device and with a plurality of second semiconductor devices
EP2736170B1 (en) * 2012-11-23 2015-06-17 Nxp B.V. Cascoded semiconductor devices
EP2736171A1 (en) * 2012-11-23 2014-05-28 Nxp B.V. Cascoded semiconductor devices
EP2787641B1 (en) * 2013-04-05 2018-08-29 Nexperia B.V. Cascoded semiconductor devices
US9007117B2 (en) * 2013-08-02 2015-04-14 Infineon Technologies Dresden Gmbh Solid-state switching device having a high-voltage switching transistor and a low-voltage driver transistor
US9735078B2 (en) * 2014-04-16 2017-08-15 Infineon Technologies Ag Device including multiple semiconductor chips and multiple carriers

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4864373A (en) * 1985-01-16 1989-09-05 Fujitsu Limited Semiconductor circuit device with voltage clamp
EP1085653A1 (en) * 1999-09-13 2001-03-21 Chartered Semiconductor Manufacturing Pte Ltd. A technique to generate negative conductance in CMOS tuned cascode RF amplifier
CN101238560A (zh) * 2005-06-10 2008-08-06 日本电气株式会社 场效应晶体管
CN102598095A (zh) * 2009-11-13 2012-07-18 株式会社半导体能源研究所 显示器件以及包含显示器件的电子器件

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