CN105307404A - Parallel via hole design method for improving signal quality and reducing processing cost - Google Patents
Parallel via hole design method for improving signal quality and reducing processing cost Download PDFInfo
- Publication number
- CN105307404A CN105307404A CN201510902143.6A CN201510902143A CN105307404A CN 105307404 A CN105307404 A CN 105307404A CN 201510902143 A CN201510902143 A CN 201510902143A CN 105307404 A CN105307404 A CN 105307404A
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- CN
- China
- Prior art keywords
- signal
- via hole
- signal quality
- stub
- len
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 15
- 230000008054 signal transmission Effects 0.000 claims description 4
- 230000002411 adverse Effects 0.000 abstract 1
- 238000003475 lamination Methods 0.000 abstract 1
- 230000005540 biological transmission Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000002788 crimping Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
- H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/096—Vertically aligned vias, holes or stacked vias
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09945—Universal aspects, e.g. universal inner layers or via grid, or anisotropic interposer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/17—Post-manufacturing processes
- H05K2203/171—Tuning, e.g. by trimming of printed components or high frequency circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/17—Post-manufacturing processes
- H05K2203/173—Adding connections between adjacent pads or conductors, e.g. for modifying or repairing
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention discloses a parallel via hole design method for improving signal quality and reducing processing cost, belongs to the field of computer signal quality, and aims to solve the technical problems of via hole stub caused by layer change of signal via holes and reduction of processing cost and adverse factors influencing signal quality. The technical scheme is as follows: the method comprises the following steps: (1) determining the number of layers of the PCB lamination; (2) determining the number of signal layers according to the number of layers of the PCB board in the step (1); (3) calculating the length of the via stub according to the number of the signal layers in the step (2); (4) and (4) judging the influence on the GHZ signal according to the length of the via hole stub in the step (3).
Description
Technical field
The present invention relates to Computer signal quality field, specifically a kind of Via Design method in parallel improving signal quality and cut down finished cost.
Background technology
Electron trade is under the driving of Moore's Law, and product function is more and more stronger, and integrated level is more and more higher, and the speed of signal is more and more faster, and the corresponding R&D cycle is also shorter and shorter.Via hole stump (i.e. STUB) in the middle of electronic hardware design on board level left by signal layer-exchange hole-through is the problem that signal integrity field is extremely paid attention to always.Due to microminiaturization, the high speed of electronic product, various challenge is brought to design and through engineering approaches.PCB layout is the Physical realization of electrical connection.In high speed serialization system, we need to consider high-quality signal transmission quality.Only have for Design of Signal goes out high-quality physical transmission channel, signal high-quality can be ensured, effectively transmit.And method for designing popular to be at present plate level add man-hour, adopt back drill production technology.The method improves processing cost, the process-cycle, adds product design, production difficulty.The existence considering various influencing factor is needed in the middle of design on board level, as transmission line impedance, transmission line loss, the various influencing factors such as via hole stump.How can solve signal via and change the via hole stump problem that layer brings, can cut down finished cost and reduce the unfavorable factor affecting signal quality simultaneously.
Technical assignment of the present invention is to provide a kind of Via Design method in parallel improving signal quality and cut down finished cost, and solves signal via and changes via hole stump that layer brings and can cut down finished cost and reduce the problem of the unfavorable factor affecting signal quality simultaneously.
The technical solution adopted for the present invention to solve the technical problems is: comprise the steps:
(1) number of plies that pcb board is stacked is determined;
(2) according to the quantity of the number of plies determination signals layer of step (1) pcb board;
(3) via hole stub end length is calculated according to the quantity of step (2) signals layer;
(4) impact on GHZ signal is judged according to step (3) via hole stub end length;
(5) when the signal delay half period of returning from stump end reflection, namely resonance is produced; The frequency of this resonance point is the F=1.5/LEN length INCH of STUB (F to be GHz, LEN be); To reduce the impact of this resonance point on Signal transmissions to minimum value, then need to meet resonance frequency much larger than the signal bandwidth in data flow, i.e. nyquist frequency (1/2DATERATE) rough estimate F>10x1/2xDATERATE and LEN<300/DATERATE; According to the GHZ signal that above-mentioned formula and step (1)-(4) are determined, calculate acceptable via hole stub end length;
(6) the acceptable via hole stub end length calculated according to step (5) offers via hole in parallel.
Of the present inventionly a kind ofly improve Via Design method in parallel that signal quality cuts down finished cost compared to the prior art, there is following beneficial effect: the present invention avoids the impact of via hole stump on signal dexterously, also eliminate the back drill operation of plant produced; The invention solves the problem that signal via changes the via hole stump that layer brings simultaneously, can cut down finished cost and reduce the unfavorable factor affecting signal quality simultaneously.
The present invention have reasonable in design, structure simple, be easy to process, the feature of one-object-many-purposes, thus, have good value for applications.
Embodiment
Below by specific embodiment, the invention will be further described.
Embodiment 1
8 laminates, thickness of slab 4MM, pcb board stepped construction, signal-stratum-signal-power-power-signal-stratum-signal, totally four signals layers.If top layer cabling, third layer changes layer, and via hole stub end length is 151.58MIL, and this stub end length is very large for impact GHZ signal.This stump to the influence mode of signal is: when from Lenstub(stump) end reflection return signal delay half period time, namely produce resonance.The frequency of this resonance point is that (F is GHz to F=1.5/LEN, LEN is the length INCH of STUB) to reduce the impact of this resonance point on Signal transmissions to minimum value, then need to meet resonance frequency much larger than the signal bandwidth in data flow, i.e. nyquist frequency (1/2DATERATE) rough estimate F>10x1/2xDATERATE and LEN<300/DATERATE.According to this estimation equation, if 8Gbps signal, acceptable via hole stub end length be 37.5MIL. in this 8 Rotating fields, 8Gbps signal is walked in third layer, and via hole stump is not allowed to.General Normal practice adopts back drill, and the method increases design difficulty, improves processing cost.And because process technology limit, the crimping length reserving stitch is needed for crimping device, cannot accomplish to cut STUB completely.The present invention is directed to this kind of situation, invent a kind of via structure that can reduce STUB impact, the long STUB via structure model of STUB=151.58MIL, remove the Via Design model in parallel of STUB impact.Adopt via structure advantage in parallel of the present invention be STUB is reduced to minimum.
Embodiment 2
One thickness of slab is 20 layers of backboard of 3.5MM, and it is 8 right that 8Gpbs signal only has, and reserved cabling aspect causes signal STUB long, adopts back drill design cost higher, and needs back drill signal very few, therefore adopt this process costs higher, and many one procedures.So adopt the present invention's Via Design scheme in parallel, obtain same signal integrity effect.
By embodiment above, described those skilled in the art can be easy to realize the present invention.But should be appreciated that the present invention is not limited to above-mentioned embodiment.On the basis of disclosed execution mode, described those skilled in the art can the different technical characteristic of combination in any, thus realizes different technical schemes.
Claims (1)
1. improve the Via Design method in parallel that signal quality cuts down finished cost, it is characterized in that: comprise the steps:
(1) number of plies that pcb board is stacked is determined;
(2) according to the quantity of the number of plies determination signals layer of step (1) pcb board;
(3) via hole stub end length is calculated according to the quantity of step (2) signals layer;
(4) impact on GHZ signal is judged according to step (3) via hole stub end length;
(5) when the signal delay half period of returning from stump end reflection, namely resonance is produced; The frequency of this resonance point is the F=1.5/LEN length INCH of STUB (F to be GHz, LEN be); To reduce the impact of this resonance point on Signal transmissions to minimum value, then need to meet resonance frequency much larger than the signal bandwidth in data flow, i.e. nyquist frequency (1/2DATERATE) rough estimate F>10x1/2xDATERATE and LEN<300/DATERATE; According to the GHZ signal that above-mentioned formula and step (1)-(4) are determined, calculate acceptable via hole stub end length;
(6) the acceptable via hole stub end length calculated according to step (5) offers via hole in parallel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510902143.6A CN105307404A (en) | 2015-12-09 | 2015-12-09 | Parallel via hole design method for improving signal quality and reducing processing cost |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510902143.6A CN105307404A (en) | 2015-12-09 | 2015-12-09 | Parallel via hole design method for improving signal quality and reducing processing cost |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105307404A true CN105307404A (en) | 2016-02-03 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510902143.6A Pending CN105307404A (en) | 2015-12-09 | 2015-12-09 | Parallel via hole design method for improving signal quality and reducing processing cost |
Country Status (1)
| Country | Link |
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| CN (1) | CN105307404A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107846780A (en) * | 2017-11-01 | 2018-03-27 | 郑州云海信息技术有限公司 | A kind of method of the cabling in pcb board |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101075813A (en) * | 2006-05-18 | 2007-11-21 | 英业达股份有限公司 | High-speed signal transmission-line structure of connected-pole parallel series |
| CN101341806A (en) * | 2004-10-29 | 2009-01-07 | 英特尔公司 | An apparatus and method for improving printed circuit board signal layer transitions |
| CN103841755A (en) * | 2012-11-26 | 2014-06-04 | 鸿富锦精密工业（深圳）有限公司 | Method for reducing via stub and printing circuit board designed by using the method |
| CN104822224A (en) * | 2014-01-31 | 2015-08-05 | 英特尔公司 | Circuit component bridge device |
-
2015
- 2015-12-09 CN CN201510902143.6A patent/CN105307404A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101341806A (en) * | 2004-10-29 | 2009-01-07 | 英特尔公司 | An apparatus and method for improving printed circuit board signal layer transitions |
| CN101075813A (en) * | 2006-05-18 | 2007-11-21 | 英业达股份有限公司 | High-speed signal transmission-line structure of connected-pole parallel series |
| CN103841755A (en) * | 2012-11-26 | 2014-06-04 | 鸿富锦精密工业（深圳）有限公司 | Method for reducing via stub and printing circuit board designed by using the method |
| CN104822224A (en) * | 2014-01-31 | 2015-08-05 | 英特尔公司 | Circuit component bridge device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107846780A (en) * | 2017-11-01 | 2018-03-27 | 郑州云海信息技术有限公司 | A kind of method of the cabling in pcb board |
| CN107846780B (en) * | 2017-11-01 | 2020-06-16 | 苏州浪潮智能科技有限公司 | Method for wiring in PCB |
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| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160203 |