CN105306009A - FIR (Finite Impulse Response) digital filter - Google Patents

Abstract

The invention discloses an FIR (Finite Impulse Response) digital filter. A method of adopting a DSP chipTMS320LF2407A to improve an anti-jamming capability of the filter, establishing a TI DSP model rapidly by using a Matlab and generating a C language program directly is adopted, so that development of DSP software is simplified, DSP program design with complex functions can be finished, strict linearity can be realized, delay distortion is not existed, only fixed time delay exists, the processing speed is faster and the efficiency is higher as filtering treatment is carried out through programming; and the FIR digital filter also has the characteristics of low power consumption, high precision, low volume, multiple functions, good stability, good reliability and low cost.

Description

A kind of Finite Impulse Response filter

Technical field

The present invention relates to signal transacting field, be specifically related to a kind of Finite Impulse Response filter.

Background technology

In digital signal processing, digital filtering occupies extremely important status.Digital filter easily realizes different amplitudes and phase-frequency characteristic index, overcomes the voltage drift relevant to analog filter device performance, temperature drift and noise problem.With dsp chip realize digital filtering except have good stability, accuracy high, not affected by environment except, also there is the feature that flexibility is good.

Because dsp controller has the structure of many uniquenesses, many group bus structures are such as adopted to realize parallel processing, independently accumulator and multiplier and abundant addressing system, adopts dsp controller just can improve the ability of Digital Signal Processing computing, can accomplish real-time process to digital signal.Digital Signal Processing utilizes application specific processor or computer, in digital form signal sampled, convert, filtering, enhancing, compression, the process such as identification, to obtain meeting the signal form that people require.Digital signal processor is a kind of special microprocessor of processing digital signal, is mainly used in the digital processing algorithm realizing various signal real-time.It structurally improves for the feature of Digital Signal Processing and optimizes, and adds special instruction and be specifically designed to digital processing, and thus processing speed is faster, and efficiency is higher.

Finite impulse response filter, i.e. FIR filter are the one of digital filter, and the shortcoming of existing Finite Impulse Response filter is the linear not strict of phase response and precision is low.

Summary of the invention

The invention provides a kind of Finite Impulse Response filter, solve the linear strict of existing Finite Impulse Response filter phase response and problem that precision is low.

The present invention solves the problem by the following technical programs:

A kind of Finite Impulse Response filter, is made up of dsp chip, A/D converter, D/A converter and power circuit; The data that described dsp chip collects for the treatment of A/D converter and D/A converter; Described A/D converter is used for analog signal to be changed to digital signal, inputs to dsp chip; Described D/A converter is used for digital signal to be converted to analog signal, inputs to external equipment; Described power circuit is dsp chip, A/D converter, D/A converter are powered.

In such scheme, described A/D converter is TVL2544.

In such scheme, described D/A converter is TVL56381.

Further, designed by following steps:

1) carry out initialization to DSP, the vector sum mode of operation needed for definition, is configured the register used

2) the pre-designed N number of numerical value in the shock response sequence hlnl of the FRI filter of N number of tap that has is put into memory cell

3) start to carry out sampling and reading sample value, put into suitable memory cell;

4) sample value is carried out calculation process;

5) output processing result, repeat 3), 4), 5).

Further, described step 4) be made up of following steps:

A) reset by accumulator, arrange two storage unit A be multiplied, the initial value of B is K, L;

B) K sample value AK is multiplied with the value BL of L impulse response sequence, and product is sent into accumulator adds up;

C) K mono-1 sample value AK 1 are put into AK, the former numerical value now in AK is capped;

D) repeat b) with c) until complete N multiply operation.

Advantage of the present invention and effect are:

1, illustrate that circuit working is stablized by software verification, simulation hardware and environmental experiment, the phase response demonstrating FRI filter can be strict linear, there is not delay distortion in it, regular time is only had to postpone, the present invention, while ensureing that amplitude-frequency characteristic meets technical requirement, more easily accomplishes strict linear phase; Carry out filtering process by programming, make processing speed faster, efficiency is higher;

2, low-power consumption, high accuracy, small size, multi-functional, reliable and stable and inexpensive, improve integrated level and the reliability of filter, improve the rejection ability to interference signal.

Embodiment

Below in conjunction with embodiment, the invention will be further described, but the present invention is not limited to these embodiments.

The passband of Finite Impulse Response filter provided by the invention is 12HZ ~ 14.4KHZ, and stopband is 9.6KHZ ~ 12KHZ, and sample frequency is 48KHZ, and stopband attenuation is 60dB.

Consider arithmetic speed, price, hardware resource, developing instrument and other factors, dsp chip of the present invention selects the TMS32OLF2407A of TI company.This chip is 16 fixed-point DSP chip, has 544words*16bitsDARAM and 2K16-bitwordsSARAM, and has 16 data lines, can expand 3 independently memory spaces.

The power source special chip of TI company can provide duplicate supply to export 3.3V/2.5V, 3.3V/1.8V, 3.3V/1.5V, 3.3V/1.2V, and the present invention selects the burning voltage chip of 3.3V/2.5V and electrification reset is short for time of delay.3.3V voltage is that dsp chip is powered.Clock signal is provided by clock chip, can selection work voltage be the active crystal oscillator of 20MHZ of 3.3V.In programming, configuration register SCSRI is 2* external clock.

In the peripheral circuit of dsp chip, A/D converter is a very important device.Consider the precision of A/D converter, change-over time, price, it is a kind of serial a/d transducer TVL2544 of the supporting making of DSP that the present invention selects TI company specially.TVL2544 is 12 4 passage low-power consumption serial data A/D converters, and can work 3.6us change-over time under 2.7V ~ 5.5V condition, and reference source has inside and outside and selects, and internal reference source programmable, SPI interface and TMS320 series DSP compatibility.

A/D converter ALT-CH alternate channel analog input voltage range is 0V ~ 4V, external microprocessor carries out initial configuration by SPI interface to module, namely A/D conversion and control register and reference power settings is write, then input instruction 0000H chooses analog input channel A0, input instruction Z000H chooses analog input channel Al or input instruction 4000H chooses analog input channel A2, and input instruction 6000H chooses analog input channel A3.Then start the A/D conversion operations of respective channel, under certain SPI interface sequence, export translation data.In transformation result, high 12 is A/D converting result data position, and low four are always 0.According to the working method that the configuration definition of control register needs, the control command register that control command is sent to TLv2544 by the SPI interface of DSP completes Initialize installation.

The connection of D/A converter and dsp chip: input signal, first through amplifier and filter, then carries out A/D conversion, analog signal is converted to digital bit stream.According to Nyquist sampling theorem, for guarantee information is not lost, sampling frequency is at least 2 times of input signal highest frequency.The input of dsp chip is the digital signal represented with sampled version obtained after A/D conversion, and the digital signal of dsp chip to input will carry out the process of certain form, as carried out a series of multiply accumulating operation.Digital processing is the key of DSP, and this and other system such as telephone switching system are very different.In switching system, Route Selection is carried out in the effect of processor, it is not modified to input data, and dsp processor will be revised accordingly to data, digital quantity is after treatment converted to analog quantity through D/A conversion, carries out interpolation and smothing filtering more afterwards, obtains continuous print analog waveform, although therefore both real-time system, both real-time constraints are very different.

A kind of D/A converter TVL56381 that DSP ancillary equipment is supporting, low-power consumption 12 Bits Serial data D/A converter under 2.7V ~ 5.5V condition of work, internal reference power supply programmable, setting-up time is 1us in fast mode, 3.5us, SPI interface and TMS320 series DSP compatibility under slow speed mode: DNI is serial data input, SCLK is clock signal input terminal, C/S is chip selection signal, and OUAT, OUTB are two analog output channels, and REF is fiducial reference source input.In 16 bit data of sampling, low 12 is valid data position.External microprocessor carries out initial configuration by SPI interface to module, namely D/A conversion and control register is write, then channel selecting instruction and channel data are write corresponding passage/director data register by external microprocessor, then complete under certain SPI interface sequence and upgrade the output of D/A passage.

The present invention is made up of dsp chip, A/D converter, D/A converter and power circuit; The data that dsp chip collects for the treatment of A/D converter and D/A converter; A/D converter is used for analog signal to be changed to digital signal, inputs to dsp chip; D/A converter is used for digital signal to be converted to analog signal, inputs to external equipment; Power circuit is dsp chip, A/D converter, D/A converter are powered.

Matlab/Siulink is used to set up the step of Filtering Model:

1) in newly-built simulink file, the LF24o07eZdsp functional block of C2000TargetPreferences is put into, wherein clock ratio selecting predictors l ~ 128 of DSP timer;

2) in the Matlab DSPToolBox of simulink, design of filter specific purpose tool DFATOOL is put into file; Selective filter type is FIR band stop filter, Kaises window function, and filter order is Minimumorder, Fpassl be 7.2KHZ, Fstopl be 9.6KHZ, Fpass2 be 14.4KHz, Fstop2 is 12KHZ, and sample frequency is 48KHz;

3) graphic file is generated c program.

The project file that the C programmer Automatically invoked CCS2 software translating generated by MATLAB graphic file runs, the program directly generated by MATLAB can realize digital filtering function, but owing to employing many default settings in program, in running, also there are some problems.In the program generated with said method, only timer interruption is processed in interrupt handling routine.When causing other to interrupt due to interference signal, DSP can be caused to shut down, therefore will define invalid interruption in interrupt vector, and add interrupt service routine in interrupt response program.Other functions also need could true(-)running to realize through debugging.

Sample to the analog signal of input, be converted to digital signal by analog signal, DSP reads sample value each time, and carries out convolution algorithm to sample value each time, then operation result is delivered to D/A and converts analog signal output to:

1) carry out initialization to DSP, the vector sum mode of operation needed for definition, is configured the register used

2) the pre-designed N number of numerical value in the shock response sequence hlnl of the FRI filter of N number of tap that has is put into memory cell

3) start to carry out sampling and reading sample value, put into suitable memory cell;

4) sample value is carried out calculation process, comprises:

A) reset by accumulator, arrange two storage unit A be multiplied, the initial value of B is K, L;

B) K sample value AK is multiplied with the value BL of L impulse response sequence, and product is sent into accumulator adds up;

C) K mono-1 sample value AK 1 are put into AK, the former numerical value now in AK is capped;

D) repeat b) with c) until complete N multiply operation;

5) output processing result, repeat 3), 4), 5).

Need log-on data to carry out A/D conversion after parameter initialization completes and the data D/A of DSP process changed to export.The working method of TVL2544 is: internal reference voltage 4V, and 12 short clock-cycle samplings, monotype is changed and adopted inner OSC.Therefore control register is configured to x0A804.TVL5638 working method is immediate mode and uses inner, and 2.048V reference voltage, control register is configured to OxD002.

Carry out emulation experiment, can see from amplitude-frequency response, the passband of filter, stopband, passband ripple, stopband attenuation the present invention are to the requirement of performance.As can be seen from phase-frequency response curve, the phase response of this FRI filter can be strict linear, and therefore it does not exist delay distortion, only has regular time to postpone, and is applicable to picture signal process, transfer of data etc. with the system of waveform carry information.FRI filter overcomes analog filter and iir digital filter only considers that amplitude-frequency characteristic does not consider the shortcoming of phase characteristic, and they will obtain the necessary additional phase place correction network of linear phase, make the complexity that filter becomes.And FIR filter is while ensureing that amplitude-frequency characteristic meets technical requirement, more easily accomplish strict linear phase.

Claims (5)

1. a Finite Impulse Response filter, is characterized in that:

Be made up of dsp chip, A/D converter, D/A converter and power circuit;

The data that described dsp chip collects for the treatment of A/D converter and D/A converter;

Described A/D converter is used for analog signal to be changed to digital signal, inputs to dsp chip;

Described D/A converter is used for digital signal to be converted to analog signal, inputs to external equipment;

Described power circuit is dsp chip, A/D converter, D/A converter are powered.

2. a kind of Finite Impulse Response filter according to claim 1, is characterized in that: described A/D converter is TVL2544.

3. a kind of Finite Impulse Response filter according to claim 1, is characterized in that: described D/A converter is TVL56381.

4. a kind of Finite Impulse Response filter according to claim 1, is characterized in that:

Designed by following steps:

1) carry out initialization to DSP, the vector sum mode of operation needed for definition, is configured the register used

2) the pre-designed N number of numerical value in the shock response sequence hlnl of the FRI filter of N number of tap that has is put into memory cell

3) start to carry out sampling and reading sample value, put into suitable memory cell;

4) sample value is carried out calculation process;

5) output processing result, repeat 3), 4), 5).

5. a kind of Finite Impulse Response filter according to claim 4, is characterized in that:

Described step 4) be made up of following steps:

A) reset by accumulator, arrange two storage unit A be multiplied, the initial value of B is K, L;

B) K sample value AK is multiplied with the value BL of L impulse response sequence, and product is sent into accumulator adds up;

C) K mono-1 sample value AK 1 are put into AK, the former numerical value now in AK is capped;

D) repeat b) with c) until complete N multiply operation.