CN105304130B - Flash memory device and the method for executing simultaneously operating - Google Patents
Flash memory device and the method for executing simultaneously operating Download PDFInfo
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- CN105304130B CN105304130B CN201410365975.4A CN201410365975A CN105304130B CN 105304130 B CN105304130 B CN 105304130B CN 201410365975 A CN201410365975 A CN 201410365975A CN 105304130 B CN105304130 B CN 105304130B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The present invention provides a kind of flash memory device and the methods for executing simultaneously operating, wherein, flash memory device includes: the first Serial Peripheral Interface (SPI) (SPI) flash memory crystal grain, has the first crystal grain identification symbol and the first Serial Peripheral Interface (SPI) pin group；Second Serial Peripheral Interface (SPI) flash memory crystal grain has the second crystal grain identification symbol and the second Serial Peripheral Interface (SPI) pin group；Encapsulation is had the above-mentioned first Serial Peripheral Interface (SPI) flash memory crystal grain and above-mentioned second Serial Peripheral Interface (SPI) flash memory crystal grain arranged with stack arrangement, and there is Serial Peripheral Interface (SPI) to encapsulate pin group；Wherein, above-mentioned Serial Peripheral Interface (SPI) encapsulation pin group distinguishes coupled in parallel to above-mentioned first Serial Peripheral Interface (SPI) pin group and above-mentioned second Serial Peripheral Interface (SPI) pin group.The present invention has the advantages that Serial Peripheral Interface (SPI) flash memory and higher data storage capacities, and compatible in locally executing and the application of code mapping.
Description
Technical field
The present invention is a kind of related flash memory, in particular to using the memory crystal grain stacked and serially outer
If the flash memory device of interface.
Background technique
String type flash memory has become the popular substitution memory of traditional block form flash memory.String type quick flashing
Memory provides many advantages, including package area is small, low pin count, simplifies printed circuit board layout, low power consumption, performance
Comparable to block form flash memory and corresponding apparatus and system level cost is relatively low.Serial Peripheral Interface (SPI) widely makes
For string type flash memory, and unit or multidigit Serial Peripheral Interface (SPI) (including multidigit instruction and (or) address can be passed through
Input and long numeric data output) carry out device configuration, especially receive an acclaim at present.Serial Peripheral Interface (SPI) has many excellent
Point: unit Serial Peripheral Interface (SPI) allows extensive compatibility, and when multidigit Serial Peripheral Interface (SPI) is in conjunction with some flash memories,
Allow quick " code mapping (code shadowing) " to random access memory and " local under high timing speed
The code storages applications such as execution (XIP) ".
String type flash memory usually can provide the capacity of 512Kb to 1Gb.However, to high density string type flash memory
For reservoir, the demand of lower every cost continues to increase.Wherein, though its feasible cost of single high density crystal grain compared with
Height, therefore the low-density crystal grain of same type can be stacked and form highdensity string type flash memory device to replace as one
For scheme.For example, the string type flash memory crystal grain for two same types that density is 256Mb can be stacked to constitute
Capacity be 512Mb (2x256Mb) device, or by density be 256Mb four same types string type flash memory
Crystal grain is stacked to constitute capacity as the device of 1Gb (4x256Mb).
In addition, different types of flash memory crystal grain can be stacked to constitute the single memory device with different characteristics
It sets.Flash memory usually has NOR flash memory and NAND quick-flash memory, in NOR flash memory, each storage
Device unit is connected between bit line and ground connection, and in NAND quick-flash memory, several memory cell series connection are connected to position
Between line and ground connection.Wherein, NOR flash memory generally has low-density, high reading speed, low writing speed, low erasing
The characteristics such as speed and arbitrary access, and NAND quick-flash memory generally has high density, middle reading speed, high page write-in speed
The characteristics such as degree, high erasing speed and the access indirectly or in a manner of I/O.NOR flash memory is because can carry out random
Access, microprocessor would generally use NOR flash memory carry out quickly " code mapping " to random access memory and
The application such as " locally executing ", and NAND quick-flash memory is because of its high speed sequence write capability and the spy of high density but low cost
Property, make it particularly suited for the high system of data storage capacities demand.In addition, certain form of NAND quick-flash memory is at present
It is modified to provide the characteristic of similar SPI-NOR flash memory in the application of code mapping.
The operating technology of Serial Peripheral Interface (SPI) flash memory device with stacked die is still not perfect at present.
“Spansion Inc.,Data Sheet,S70FL256P 256-Mbit CMOS 3.0 Volt Flash Memory
With104-MHz SPI Multi I/O Bus, Revision 05, January 30,2013 " is disclosed two complete phases
With 128Mb crystal grain carry out heap poststack, then will other/CS pin be welded to encapsulation above different corresponding pin constituted it is serial
Peripheral Interface flash memory device.Unfortunately, it needs through controller to provide and manage multiple/CS control letter
Number, in addition, have more /CS pin requirement can also make the Serial Peripheral Interface (SPI) flash memory device that can not carry out eight pins
Encapsulation.
“Micron Technology Inc.,N25Q512A 1.8V,Multiple I/O Serial Flash
Memory, September 2013 " are disclosed by two different crystal grain heap poststacks, in addition to reading and erasing in relation to memory
Operation is outer, the angle of user can be considered to the flash memory device of single device.However, though above-mentioned apparatus can be in eight pins
In encapsulation, the operation of quaternary I/O serial peripheral interface protocol is carried out, but its manufacturing cost is often because of its complicated special designing
And it is higher.
Summary of the invention
A kind of method that the present invention provides flash memory device and executes simultaneously operating has Serial Peripheral Interface (SPI)
The advantages of (Serial Peripheral Interface, SPI) flash memory and higher data storage capacities, and
And it is compatible in some embodiments in locally executing and the application of code mapping.The present invention includes that following demonstration is implemented
Example.
One embodiment of the invention provides a kind of flash memory device, comprising: one first Serial Peripheral Interface (SPI) flash
Device crystal grain has one first crystal grain identification symbol and the first Serial Peripheral Interface (SPI) pin group；One second Serial Peripheral Interface (SPI) quick flashing
Memory crystal grain has one second crystal grain identification symbol and the second Serial Peripheral Interface (SPI) pin group；And one encapsulation, have with
The the first Serial Peripheral Interface (SPI) flash memory crystal grain and the second Serial Peripheral Interface (SPI) flash memory of one stack arrangement arrangement
Crystal grain, and there is a Serial Peripheral Interface (SPI) to encapsulate pin group, it is serial outer with the first Serial Peripheral Interface (SPI) pin group and second
If interface pins group coupled in parallel.
Another embodiment of the present invention provides a kind of to execute simultaneously operating in Serial Peripheral Interface (SPI) flash memory device
Method, it includes that a chip selects a Serial Peripheral Interface (SPI) of pin to encapsulate that wherein Serial Peripheral Interface (SPI) flash memory device, which has,
Pin group.Serial Peripheral Interface (SPI) flash memory device suitable for the above method includes one first Serial Peripheral Interface (SPI) quick flashing
Memory crystal grain has one first crystal grain identification symbol and the first Serial Peripheral Interface (SPI) pin group；And one second serial peripheral
Interface quick flash storage crystal grain has one second crystal grain identification symbol and the second Serial Peripheral Interface (SPI) pin group；First is serial outer
If interface quick flash storage crystal grain and the second Serial Peripheral Interface (SPI) flash memory crystal grain stacking and the first Serial Peripheral Interface (SPI)
Pin group and the second Serial Peripheral Interface (SPI) pin group and Serial Peripheral Interface (SPI) encapsulate pin group coupled in parallel.Method is included in string
The chip selection pin of row Peripheral Interface flash memory device receives the first chip and selects active signal, the first chip selection master
Dynamic signal is provided to the first Serial Peripheral Interface (SPI) memory crystal grain and the second Serial Peripheral Interface (SPI) memory crystal grain with parallel；With
And the step of receiving the first chip selection active signal is combined, in the first Serial Peripheral Interface (SPI) flash memory crystal grain and second
The first crystal grain selection instruction is executed on Serial Peripheral Interface (SPI) flash memory crystal grain with enable the first Serial Peripheral Interface (SPI) flash memory
Reservoir crystal grain responds a Serial Peripheral Interface (SPI) instruction set, and the above-mentioned second Serial Peripheral Interface (SPI) flash memory crystal grain of enable is only rung
Answer a universal command subset, universal command subset is the subset of Serial Peripheral Interface (SPI) instruction set and including crystal grain selection instruction.Side
Method further include received from the chip of Serial Peripheral Interface (SPI) flash memory device selection pin the first chip selection stop signal with
Terminate first on the first Serial Peripheral Interface (SPI) flash memory crystal grain and the second Serial Peripheral Interface (SPI) flash memory crystal grain
The execution of crystal grain selection instruction.Method further includes responding outside serial when the first Serial Peripheral Interface (SPI) flash memory crystal grain is enabled
If when interface instruction collection, receiving the selection of the second chip actively in the chip selection pin of Serial Peripheral Interface (SPI) flash memory device
Signal, the second chip selection active signal are provided to the first Serial Peripheral Interface (SPI) flash memory crystal grain and second serially in parallel
Peripheral Interface flash memory crystal grain；And the step of receiving the second chip selection active signal is combined, in the first serial peripheral
The first Serial Peripheral Interface (SPI) instruction that non-universal instruction is executed on interface quick flash storage crystal grain, causes an inside self-timing operation
The execution of (internal self-timed operation).Method further includes in Serial Peripheral Interface (SPI) flash memory device
Chip selection pin receive the second chip selection stop signal on the first Serial Peripheral Interface (SPI) flash memory crystal grain eventually
Only the first Serial Peripheral Interface (SPI) instructs, but does not terminate internal self-timing operation.Method further includes in Serial Peripheral Interface (SPI) flash memory
Third wafer is received on the chip selection pin of reservoir device and selects active signal, and third wafer selection active signal provides in parallel
To the first Serial Peripheral Interface (SPI) flash memory crystal grain and the second Serial Peripheral Interface (SPI) flash memory crystal grain；And it combines and connects
The step of receiving third wafer selection active signal, in the first Serial Peripheral Interface (SPI) flash memory crystal grain and the second serial peripheral
The second crystal grain selection instruction is executed on interface quick flash storage crystal grain with enable the second Serial Peripheral Interface (SPI) flash memory crystal grain
Respond above-mentioned Serial Peripheral Interface (SPI) instruction set, and enable the first Serial Peripheral Interface (SPI) flash memory crystal grain response universal command
Collection, wherein the second crystal grain selection instruction specifies one second crystal grain identification symbol to the serial circumference flash memory device.
Method further includes the chip selection pin reception third wafer selection stop signal in Serial Peripheral Interface (SPI) flash memory device,
To terminate second on the first Serial Peripheral Interface (SPI) flash memory crystal grain and the second Serial Peripheral Interface (SPI) flash memory crystal grain
The execution of crystal grain selection instruction.Method further includes responding outside serial when the second Serial Peripheral Interface (SPI) flash memory crystal grain is enabled
If when interface instruction collection, receiving the selection of the 4th chip actively in the chip selection pin of Serial Peripheral Interface (SPI) flash memory device
Signal, the 4th chip selection active signal are provided to the first Serial Peripheral Interface (SPI) flash memory crystal grain and second serially in parallel
Peripheral Interface flash memory crystal grain；And the step of receiving above-mentioned 4th chip selection active signal is combined, it is serial in second
The instruction of the second Serial Peripheral Interface (SPI) is executed on Peripheral Interface flash memory crystal grain, while in the first Serial Peripheral Interface (SPI) memory
Internal self-timing operation is executed on crystal grain.Method further includes the chip selection pin reception in Serial Peripheral Interface (SPI) memory device
4th chip selects stop signal to terminate the instruction of the second Serial Peripheral Interface (SPI).
A kind of method that the present invention provides flash memory device and executes simultaneously operating, the flash of multiple stackings
Device crystal grain only needs single one physical/CS pin；Eight pins that all serial peripheral interface protocols can be performed encapsulate, including quaternary is serial
Peripheral interface protocol；Some Serial Peripheral Interface (SPI) operations can be run simultaneously；It only needs to existing Serial Peripheral Interface (SPI) flash memory
Reservoir die design carries out small part amendment；Suitable for traditional multi-die package technology；It is stackable heterogeneous
(heterogeneous) flash memory crystal grain is to reach multi-functional and target efficiency.It can be with traditional flash memory
Instruction set is compatible, and can be instructed and be expanded by " crystal grain selection ".
Detailed description of the invention
Fig. 1, which shows to have described in an embodiment according to the present invention, stacks the serial of Serial Peripheral Interface (SPI) flash memory crystal grain
The block diagram of Peripheral Interface flash memory device.
Fig. 2, which is shown, has the string for stacking Serial Peripheral Interface (SPI) flash memory crystal grain described in another embodiment according to the present invention
The block diagram of row Peripheral Interface flash memory device.
Fig. 3 shows the block diagram of crystal grain selection instruction.
Fig. 4 is shown in the Serial Peripheral Interface (SPI) flash memory dress for stacking Serial Peripheral Interface (SPI) flash memory crystal grain
Set the middle block diagram for executing simultaneously operating instruction sequence.
Fig. 5 shows another in the Serial Peripheral Interface (SPI) flash with stacking Serial Peripheral Interface (SPI) flash memory crystal grain
The block diagram of simultaneously operating instruction sequence is executed in device device.
The operational flowchart of the Serial Peripheral Interface (SPI) flash memory crystal grain of Fig. 6 display response crystal grain selection instruction.
Fig. 7, which is shown between crystal grain, utilizes a kind of side plan view of crystal grain Stack Technology of gasket.
Fig. 8, which is shown, utilizes a kind of staggered side plan view of crystal grain Stack Technology of crystal grain.
Fig. 9 display utilizes a kind of side plan view of crystal grain Stack Technology of crystal grain of different sizes.
Symbol description:
10,20,70,90,100~Serial Peripheral Interface (SPI) flash memory device；
11,12,13,14,21,22,23,24,72,74,92,94,102,104~Serial Peripheral Interface (SPI) flash memory crystalline substance
Grain；
60,61,62,64,66,68~steps flow chart；
71,91,101~encapsulation main body；
73~spacer；
75,95,105~sticker；
76,96,106~cooling pad；
77,78,97,107,108~region；
81,82,83,84,98,99,111,112,113,114~lead；
93,103~material.
Specific embodiment
In this article, " Serial Peripheral Interface (SPI) flash memory crystal grain " (hereinafter referred flash memory crystal grain) refer to including
The integrated-circuit die of the flash memory array of any pattern connects configured with one group for being compatible with serial peripheral interface protocol
Foot.Any amount of flash memory crystal grain can be by being stacked and being sealed using any desired multi-die package technology
Dress.Wherein it is possible to during manufacture, each the flash memory crystal grain stacked in encapsulation is first specified individually one it is unique
Crystal grain identification symbol (Die ID), and during general operation, it is different by being specified to crystal grain selection instruction (Die Select)
Crystal grain identification symbol, one of flash memory crystal grain stacked with enable responds the subsequent instructions on Serial Peripheral Interface (SPI), and causes
Can in encapsulation other flash memory crystal grain for stacking it is (such as brilliant only in response to certain universal commands subsequent on Serial Peripheral Interface (SPI)
Grain selection instruction).
In this article, " pin " refers to the conductive element that flash memory crystal grain is connected to direct or indirect exposed electrical
Part, including the conducting element (such as pad (bonding pad)) on either crystal grain, or embedded in encapsulation above or in encapsulation
Conducting element (such as recess contact (recessed contact), concordant contact (flush contact), prominent contact
(projecting contact)) etc..
In this article, " Serial Peripheral Interface (SPI) pin " and " Serial Peripheral Interface (SPI) encapsulation pin ", which refers to, is compatible with outside serial
If the pin of interface protocol.According to serial peripheral interface protocol, six pins can be configured to single Serial Peripheral Interface (SPI) (single
SPI), double Serial Peripheral Interface (SPI)s (dual SPI), quaternary Serial Peripheral Interface (SPI) (quad SPI) or quaternary Peripheral Interface
(Quad Peripheral Interface, QPI, also referred to as serial quaternary interface (Serial Quad Interface,
SQI)), and may include single position or multidigit instruction and (or) address input and single position or long numeric data input and
(or) export, configurability may include expected any subset in above structure.Six pins offer chip selection/CS,
Timing CLK, configurable pin DI (IO0), configurable pin DO (IO1), configurable pin/WP (IO2) and configurable pin/
HOLD(IO3).For the operation of single Bits Serial Peripheral Interface, pin can configure to as instruction/address/data input
DI, data output DO, write protection/WP and holding/HOLD.For double serial peripheral equipment interface SPIs, it can configure pin and use
Using as input/output IO0, input/output IO1, write protection/WP and holding/HOLD.To quaternary Serial Peripheral Interface (SPI)
For SPI and quaternary Peripheral Interface QPI, pin can configure to as input/output IO0, input/output IO1, input/it is defeated
IO out2And input/output IO3。
Not causing the operation of busbar connector access conflict can be performed simultaneously on different flash memory crystal grain.Many operations
By the way that the incoming serial Peripheral Interface busbar connector initial (with or without the operation code of address) will be instructed, then pass through inside
The control of control circuit carries out self-timing operation, during which lasts about millisecond to the second etc..Aforesaid operations be, for example, include programming/
Wipe memory array, write state buffer and the safe buffer of program/erase.Since the execution of above-metioned instruction is wrapped
The inside operation contained is not related to any busbar connector access, therefore these operations are suitble to be related to other similar operation or other
Converge the operation synchronous operation accessed.The operation that confluence access must be still related to after sending instruction is read for example including memory array
It takes, state is read, device identification symbol is read, SFDP is read, safe buffer is read, cache is loaded into (NAND) and memory
The initial part (NOR) of coding.
It carries out stacking achievable higher memory density using the flash memory crystal grain of whole same types.Fig. 1
Display includes the Serial Peripheral Interface (SPI) flash memory dress of the identical flash memory crystal grain 11,12,13 and 14 of four stackings
Set 10.Flash memory crystal grain 11,12,13 and 14 respectively configuration there are six Serial Peripheral Interface (SPI) pin and power supply (Vcc) with
It is grounded (GND) etc. and amounts to eight pins.And flash memory crystal grain 11,12,13 and 14 for example may include NOR, NAND or
Any suitable flash memory crystal grain.It is to be stacked using four flash memory crystal grain in the present embodiment, but this hair
It is bright without being limited thereto.In other embodiments, any number of flash memory crystal grain can also be used to be stacked.
In another embodiment of the invention, different flash memory crystal grain also may be selected to be stacked, selection is passed through
The flash memory crystal grain of different capacity and characteristic can make flash memory device provide enough capacity and characteristic to accord with
Close certain specific applications.Fig. 2 is shown with the SPI-NOR flash memory crystal grain 21 and SPI-NAND flash memory stacked
The Serial Peripheral Interface (SPI) flash memory device 20 of crystal grain 22,23 and 24.Wherein above-mentioned SPI-NOR flash memory crystal grain 21
Especially suitable for the application of coding, such as locally execute and code mapping, and above-mentioned SPI-NAND flash memory crystal grain 22,
23 and 24 especially suitable for data storage, and heap poststack can provide very high density.Flash memory crystal grain 21,
22,23 and 24 include other crystal grain identification symbol, modified order and a control logic to respond crystal grain selection instruction.If desired
Faster random access memory, can be by two SPI-NOR flash memory crystal grain and two SPI-NAND flash memories
Crystal grain is stacked, or additional increase SPI-NOR flash memory.SPI-NAND flash memory suitable for code storage application
Reservoir crystal grain (not shown) also may replace SPI-NOR flash memory crystal grain 21, such as can refer to U.S. Patent Publication No. US
SPI-NAND flash memory disclosed in 2012/0084491.The memory array in each flash memory crystal grain stacked is big
It is small to be same or different, also or part is identical or part is different.For example, flash memory dress shown in Fig. 2
Set in 20, SPI-NOR flash memory crystal grain 21 do not need it is larger, for many general XIP and code mapping, such as
16-32Mb is as enough；And SPI-NAND flash memory crystal grain then can be larger, such as 1Gb, to provide many general applications
Enough data storages.Above-mentioned capacity is only rough description, may be increased because of the development of manufacturing technology.
Respectively there are six Serial Peripheral Interface (SPI) pin, Yi Ji electricity for configuration for each flash memory crystal grain 21,22,23 and 24
Source (Vcc) and ground connection (GND) etc. amount to eight pins.And flash memory crystal grain 21,22,23 and 24 for example may include
NOR, NAND or any suitable flash memory crystal grain.
Disclosed Serial Peripheral Interface (SPI) flash memory device can provide what follows any one or it is more
The combination of a advantage, and may be there are also other advantages: (a) the flash memory crystal grain of multiple stackings only needs single one physical/CS to connect
Foot；(b) the eight pins encapsulation of all serial peripheral interface protocols, including quaternary serial peripheral interface protocol can be performed；(c) some
Serial Peripheral Interface (SPI) operation can be run simultaneously；(d) only need to existing Serial Peripheral Interface (SPI) flash memory die design into
The amendment of row small part；(e) it is suitable for traditional multi-die package technology；And (f) stackable heterogeneous (heterogeneous)
Flash memory crystal grain is to reach multi-functional and target efficiency.
Disclosed Serial Peripheral Interface (SPI) flash memory device uses the flash memory crystal grain institute structure stacked
At, it can be compatible with traditional flash memory instruction set, and can be instructed and be expanded by " crystal grain selection ".For example, such as
Shown in Fig. 3, crystal grain selection instruction can be instruction (such as the C2 hexadecimal crystal grain selection operation code (hex of two hytes
Opcode)), and eight crystal grain identifications accord with.Wherein, although digit needed for crystal grain identification symbol depends on serial peripheral
The maximum number of stackable flash memory crystal grain in interface quick flash storage device, and it only needs two to may specify four
The flash memory crystal grain of a stacking, but still eight crystal grain identification symbol length can be retained, so that the crystal grain of call instruction recognizes symbol
End at hyte boundary according to general custom.
Crystal grain selection instruction selects other any flash memory crystal grain in multiple grain stacked package in the following manner.It is brilliant
Grain selection instruction is accorded with together with by controller (not shown) with the identification of the specific die for the flash memory crystal grain to be accessed and being sent to
Serial Peripheral Interface (SPI) flash memory device.Then, all flash memory crystal grain of stacking can all run crystal grain selection instruction,
The flash memory crystal grain for wherein meeting the crystal grain identification symbol can be enabled to respond all Serial Peripheral Interface (SPI) instruction set
(SPI instruction set), and other flash memory crystal grain can then be enabled to refer to only in response to Serial Peripheral Interface (SPI)
A subset (referred to general subset of instructions, Universal instruction subset) for collection is enabled, but is not responding to others
Serial Peripheral Interface (SPI) instruction set.If when simultaneously operating to be supported, the order of non-selection crystal grain and control logic can continue to execute and appoint
The inside operation what is currently carried out.This function can be designed to the order and control of the flash memory crystal grain of each stacking
In logic.
Fig. 4 and Fig. 5 is an example of simultaneously operating, and example herein is synchronous erasing and reads.In order to clear
For the sake of, omit other common multiple signals during instruction sequence.Above-mentioned signal includes/CS signal, for example ,/CS letter
Number be converted to before each instruction it is low with selection device, and in erasing, coding and write state buffer inside allow
Height is converted to when loop to complete to instruct./ CS signal can be used together with crystal grain selection instruction in this method through the above way
In.
Instruction sequence depicted in Fig. 4 starts from crystal grain selection operation code DS, is then crystal grain identification symbol 0, is then wiping
Except operation code ER (a for example, chip erasing instruction (Chip Erase instruction)) so that crystal grain 0 /CS signal from
When low conversion is supreme, internal self-timing erasing operation is executed.Next instruction sequence be crystal grain selection operation code DS, then for
Crystal grain identification symbol 1, is then read opcode RD, relevant address bit ADR and redundant digit DMY, so that crystal grain 1 executes reading
Operation.Wherein, the read operation /CS signal from high conversion to it is low when initial, and it is complete when/CS signal is supreme from low conversion
At.In this example, the time of read operation is longer than erasing operation.Next instruction sequence is crystal grain selection operation code DS,
Then it is crystal grain identification symbol 0, is then reading state buffer operation code RSR, to the data (example in reading state buffer
Such as the position the BUSY SO in state buffer 1), to confirm whether erasing operation has been completed.For example, work as Serial Peripheral Interface (SPI)
When flash memory crystal grain executes internal erasing, coding or write state buffer loop, BUSY are the only reading for being set as 1
Position.In this, crystal grain 0 is responded by the data in state buffer to indicate that erasing operation has no longer been performed, and brilliant
Grain 0 is ready for executing other operations.
Instruction sequence depicted in Fig. 5 starts from crystal grain selection operation code DS, is then crystal grain identification symbol 0, is then wiping
Except operation code ER, so that crystal grain 0 executes internal self-timing erasing operation when/CS signal is supreme from low conversion.Next finger
Enabling sequence is crystal grain selection operation code DS, is then crystal grain identification symbol 1, is then read opcode RD, relevant address bit ADR
And redundant digit DMY, so that crystal grain 1 executes read operation.Wherein, the read operation /CS signal from high conversion to it is low when
Initial, and completed when/CS signal is supreme from low conversion.In this example, the time of read operation is shorter than erasing operation, and
Read operation is completed before completing erasing operation.Next instruction sequence is crystal grain selection operation code DS, is then distinguished for crystal grain
Know symbol 0, is then reading state buffer operation code RSR, to the data in reading state buffer, to confirm erasing operation
Whether complete.Although crystal grain 0 becomes due in response to crystal grain selection instruction at this point, the inside erasing instruction of crystal grain 0 is still executing
The crystal grain selected, and responded by the data in state buffer to indicate that erasing operation is still executing.It is next
Instruction sequence is another reading state buffer operation code RSR, to reaffirm the data in state buffer.At this point, brilliant
Grain 0 is responded by the data in state buffer to indicate that erasing operation has no longer been performed, and crystal grain 0 is ready for
Execute other operations.
Fig. 6 shows the execution flow chart of crystal grain selection instruction.Firstly, receiving crystal grain selection instruction (square 60).Meanwhile if
There is any ongoing internal self-timing operation, is then persistently operated (square 61).Then, compare each crystalline substance in stacked die
Whether the crystal grain identification symbol of grain meets the crystal grain identification symbol (square 62) for being connected in crystal grain selection instruction.If detecting the two symbol
It closes, then the flash memory crystal grain is put into or is retained in full serial Peripheral Interface instruction set execution mode (square 64),
Above-mentioned full serial Peripheral Interface instruction set execution mode is that flash memory crystal grain can respond entire Serial Peripheral Interface (SPI) instruction set
The mode standard of middle all instructions.If the two is not detected to meet, flash memory crystal grain is put into or is remained in is general
In subset of instructions execution pattern (square 66).Above-mentioned universal command subset execution pattern is flash memory crystal grain only in response to general
One new model of instruction.Heretofore described " universal command " refers to a subset of Serial Peripheral Interface (SPI) instruction set, the subset
Including crystal grain selection instruction and certain stereotyped commands (such as device resetting).Wherein, no matter whether flash memory crystal grain can
Entire Serial Peripheral Interface (SPI) instruction set is responded, the subset can be all responded.This execution process may be implemented in any desired side
In method, such as hardware, firmware, software, state machine, any of the above-described combination, or in any other method.
The flash memory crystal grain of stacking can carry out many different types of simultaneously operatings.In in flash memory
The time demand of portion's erasing, programming and write operation is different, and having the flash memory crystal grain stacked can execute respectively not
Ability with instruction can increase data throughout (throughput) advantageously during general operation, and manufacture the phase in system
Between promote efficient " coding downloading ".For example, simultaneously operating is particularly conducive to " read (Read while when write-in
Write) " (state buffer write-in, either 0 to 1 or 1 to 0), " reading when program/erase " (do not include that SPI-NOR is compiled
The TCP data segment of Cheng Zhiling), and " multiple grain program/erase " (does not include the data transfer part of SPI-NOR programming instruction
Point).Although being illustrated herein with two simultaneously operatings, however, the present invention is not limited thereto, the quantity of simultaneously operating can also be with institute's heap
The quantity of folded flash memory crystal grain is as many.The flash memory crystal grain of each stacking can be individual by crystal grain selection instruction
Enable, and by reading state buffer to confirm that its state, such as the crystal grain are carrying out write-in, programming or erasing operation
And new instruction can not be received, or can receive new instruction.
When electric power starting, a specific die (such as crystal grain identification accord with as the crystal grain of " 00 ") can be specified on demand based on
Dynamic crystal grain.And before general operation, SFDP (Serial Flash Discoverable Parameters) instruction can be used to distinguish
Know whether Serial Peripheral Interface (SPI) flash memory device has the function of stacked die and support " crystal grain selection ".In order to reach this
One purpose, can be in the header (header) of the additional vendor-specific SFDP of main SFDP table.
The flash memory that unique crystal grain identification symbol can be assigned to each stacking by any technology in the fabrication process is brilliant
Grain.For example, different crystal grain identification symbol positions can be provided in buffer on demand, and in the fabrication process that institute's rheme is pre-
The stacking of crystal grain is carried out after first programming again.Due to buffer position very little, there will not be space to punish (space penalty).
It is to be noted that the crystal grain identification of all flash memory crystal grain accords with each other simultaneously in must carefully stacking in stacked die
It does not repeat, and is stacked in an appropriate order.In addition, crystal grain identification symbol pin can also be provided on flash memory crystal grain
(Die ID pin) (e.g. pad), and above-mentioned pad is wire bonded to VCC or GND in stacking in the right way
Flash memory crystal grain establishes an other unique crystal grain identification symbol.It for example, can when tool is there are two flash memory crystal grain
The crystal grain identification symbol pin of first flash memory crystal grain is wire bonded to GND to establish the first crystal grain identification symbol, and fast by second
The crystal grain identification symbol pin of flash memory crystal grain is wire bonded to Vcc to establish the second crystal grain identification symbol；When there are four flash for tool
When device crystal grain, two crystal grain identification symbol pin can be provided each flash memory crystal grain, it is brilliant by the two of the first flash memory crystal grain
Grain identification symbol pin is wire bonded to GND to establish the first crystal grain identification symbol, and two crystal grain of the second flash memory crystal grain are recognized symbol
Pin is wire bonded to GND and Vcc respectively to establish the second crystal grain identification symbol, and two crystal grain of third flash memory crystal grain are recognized symbol
Pin is wire bonded to Vcc and GND respectively to establish third crystal grain identification symbol, and two crystal grain of the 4th flash memory crystal grain are recognized
Symbol pin is wire bonded to Vcc to establish the 4th crystal grain identification symbol.When providing crystal grain identification symbol buffer position, crystal grain identification symbol pin
It may be used as the logic input that crystal grain identification symbol buffer position is input to by a other transmission gate pole.Although crystal grain identification symbol
Pin will cause space punishment (especially when it is weld pad), but advantageously, mistakenly specify crystalline substance by this mode
The risk of grain identification symbol is very low.
Although the flash memory crystal grain stacked may be placed in the encapsulation more than eight pins, and disclosed herein
Technology can merge application with other additional pins, but disclosed herein technology can advantageously make the flash memories of multiple stackings
Reservoir crystal grain is applicable to simple and eight pins with minimum floor space and encapsulates.Due to system printed circuit board layout only
Account for minimum floor space, the encapsulation of eight pins (such as small outline integrated circuit encapsulates (Small Outline Integrated
Circuit, SOIC) and WSON (Very Very Thin Small Outline No Lead)) still it is widely used in string type
Flash memory device.
Fig. 7 is schematically painted the flash memory crystal grain 72 and 74 comprising two stackings in encapsulation main body 71
The side view of the Serial Peripheral Interface (SPI) flash memory device 70 of eight pin WSON types.Although any applicable stacking can be used
Technology, but the Serial Peripheral Interface (SPI) flash memory device of the present embodiment schematically use spacer (spacer body) 73 with
Ensure the bottom of flash memory crystal grain 72 and the lead at the top of flash memory crystal grain 74 and corresponding bonding wire (wire
Bond) there are enough spaces between (such as lead 83,84 and corresponding bonding wire).Spacer 73 can be any suitable type,
Solid, the thicker sticky solid or other sticky materials of material for example, with top and bottom bonding plane.Fastly
Flash memory crystal grain 74 is depended on cooling pad 76 using any applicable technology, e.g. sticker 75 or other adhesion materials
Material.Flash memory crystal grain 72 and 74 be wire bonded on multiple conducting wires of lead frame (lead frame) (such as by lead 81,
82,83,84 and corresponding bonding wire).Multiple conducting wires of lead frame be exposed to encapsulation main body 71 outer (such as region 77 and 78) with
Pad is provided and is connected to external circuit.
Fig. 8 is schematically painted the flash memory crystal grain 92 and 94 comprising two stackings in encapsulation main body 91
The side view of the Serial Peripheral Interface (SPI) flash memory device 90 of eight pin WSON types.Serial Peripheral Interface (SPI) flash memory dress
90 are set using stacking migration technology to avoid between 94 top of 92 bottom of flash memory crystal grain and flash memory crystal grain
Interference between lead and corresponding bonding wire (such as lead 99 and corresponding bonding wire).Flash memory crystal grain 92 and 94
Be fixed among stacking using any applicable material 93, e.g. the solid of the material with top and bottom bonding plane or
Person's sticker.Flash memory crystal grain 94 adheres to cooling pad 96 using any applicable technology, e.g. sticker 95 or
Other sticky materials.Flash memory crystal grain 92 and 94 is wire bonded on multiple conducting wires of lead frame (such as by lead 98,99
And corresponding bonding wire).Multiple conducting wires of lead frame are exposed to encapsulation main body 91 outer (such as region 97) and are connected to providing pad
External circuit.
Fig. 9 is schematically painted the flash memory crystal grain 102 and 104 comprising two stackings in encapsulation main body 101
In eight pin WSON types Serial Peripheral Interface (SPI) flash memory device 100 side view.Although any be applicable in can be used
Stack Technology, but the Serial Peripheral Interface (SPI) flash memory device 100 of the present embodiment uses the crystal grain of different size or shape
To avoid bottom and the lead at the top of flash memory crystal grain 104 and the corresponding bonding wire (example of flash memory crystal grain 102
Such as lead 113,114 and corresponding bonding wire) between interference.Flash memory crystal grain 102 and 104 utilizes any applicable
Material 103 is fixed among stacking, the solid or sticker of the material e.g. with top and bottom bonding plane.Quick flashing
Memory crystal grain 104 adheres to cooling pad 106, e.g. sticker 105 or other adhesion materials using any applicable technology
Material.Flash memory crystal grain 102 and 104 be wire bonded on multiple conducting wires of lead frame (such as by lead 111,112,113,
114 and corresponding bonding wire).Multiple conducting wires of lead frame are exposed to encapsulation main body 101 outer (such as region 107 and 108) to mention
External circuit is connected to for pad.
In heretofore described Stack Technology and other Stack Technologies and be not required to it is mutually exclusive, and two or more
A above-mentioned technology can be used for the manufacture of any given stack.Prior art has disclosed many different Stack Technologies, such as can join
Read No. 2011/0195529 content taken off of U.S. Patent Publication No. US.Although being said in a manner of wire bond in Fig. 7-9
It is bright, but any other is suitable for crystal grain and encapsulates the welding technique (such as perforation (via)) between pin, it is also possible to replace
Or in conjunction with wire bond.
Embodiment disclosed by this specification is to be not limited to this to illustrate patent requirements range of the invention
The range of invention, protection scope of the present invention is when as defined in claim.Disclosed embodiment in the present invention
Modification and variation are feasible, and skilled artisan can be by reading the present invention in practical alternate embodiment
The object.In addition, particular value described herein is only used as demonstration, and can be changed according to required.This hair is not being departed from
In bright spirit and scope, can to disclosed herein embodiment make other variations or modification, also including embodiment
The substitution of multiple element, and protection scope of the present invention is only defined by claim.
Claims (12)
1. a kind of flash memory device, which is characterized in that the flash memory device includes:
There is one first Serial Peripheral Interface (SPI) flash memory crystal grain one first crystal grain identification symbol and one first serial peripheral to connect
Mouth pin group；
There is one second Serial Peripheral Interface (SPI) flash memory crystal grain one second crystal grain identification symbol and one second serial peripheral to connect
Mouth pin group；And
One encapsulation has the first Serial Peripheral Interface (SPI) flash memory crystal grain arranged with a stack arrangement and described the
Two Serial Peripheral Interface (SPI) flash memory crystal grain, and there is a Serial Peripheral Interface (SPI) to encapsulate pin group；
Wherein, Serial Peripheral Interface (SPI) encapsulation pin group distinguish coupled in parallel to the first Serial Peripheral Interface (SPI) pin group with
And the second Serial Peripheral Interface (SPI) pin group；
Wherein, the first Serial Peripheral Interface (SPI) flash memory crystal grain includes one first order and control logic, to basis
There is a crystal grain selection instruction of the first crystal grain identification symbol with the first Serial Peripheral Interface (SPI) flash memory described in enable
Crystal grain responds a Serial Peripheral Interface (SPI) instruction set, and is referred to according to the crystal grain selection for not connecting the first crystal grain identification symbol
It enables and being led to the first Serial Peripheral Interface (SPI) flash memory crystal grain described in enable only in response to the one of the Serial Peripheral Interface (SPI) instruction set
Use subset of instructions；
Wherein, the second Serial Peripheral Interface (SPI) flash memory crystal grain includes one second order and control logic, to basis
There is the crystal grain selection instruction of the second crystal grain identification symbol with the second Serial Peripheral Interface (SPI) flash described in enable
Device crystal grain responds the Serial Peripheral Interface (SPI) instruction set, and is selected according to the crystal grain for not connecting above-mentioned second crystal grain identification symbol
Instruction is selected with the second Serial Peripheral Interface (SPI) flash memory crystal grain described in enable only in response to the Serial Peripheral Interface (SPI) instruction set
The universal command subset.
2. flash memory device as described in claim 1, which is characterized in that the flash memory device further include:
Multiple first buffers position on the first Serial Peripheral Interface (SPI) flash memory crystal grain, to store described
One crystal grain identification symbol, first order are coupled to first buffer position with control logic；And
Multiple second buffers position on the second Serial Peripheral Interface (SPI) flash memory crystal grain, to store described
Two crystal grain identification symbol, second order are coupled to second buffer position with control logic.
3. flash memory device as described in claim 1, which is characterized in that
The first Serial Peripheral Interface (SPI) pin group, including one first chip selection pin, one first timing pin and four
First configurable pin；
The second Serial Peripheral Interface (SPI) pin group, including one second chip selection pin, one second timing pin and four
Second configurable pin；And
The Serial Peripheral Interface (SPI) encapsulates pin group, including is coupled to the first chip selection pin and second chip
The third wafer selection pin of selection pin, be coupled to the first timing pin and the second timing pin one the
Three timing pins are coupled to four first configurable pins and four thirds of four second configurable pins and can match
Set pin.
4. flash memory device as described in claim 1, which is characterized in that
The first Serial Peripheral Interface (SPI) flash memory crystal grain further include at least one first crystal grain identification symbol pin, described first
Crystal grain identification symbol pin is accorded with being coupled to at least partly establishing the first crystal grain identification；And
The second Serial Peripheral Interface (SPI) flash memory crystal grain further include at least one second crystal grain identification symbol pin, described second
Crystal grain identification symbol pin is coupled to power supply at least partly to establish the second crystal grain identification symbol.
5. flash memory device as claimed in claim 2, which is characterized in that
The first Serial Peripheral Interface (SPI) flash memory crystal grain further includes that at least one first transmission gate and at least one first are brilliant
Grain identification symbol pin, the first crystal grain identification symbol pin are coupled to first buffer position by first transmission gate
At least one is at least partly to establish the first crystal grain identification symbol；And
The second Serial Peripheral Interface (SPI) flash memory crystal grain further includes that at least one second transmission gate and at least one second are brilliant
Grain identification symbol pin, the second crystal grain identification symbol pin are coupled to second buffer position by second transmission gate
At least one is at least partly to establish the second crystal grain identification symbol.
6. flash memory device as claimed in claim 5, which is characterized in that
The first crystal grain identification symbol pin is coupled to ground；And
The second crystal grain identification symbol pin is coupled to power supply.
7. flash memory device as described in claim 1, which is characterized in that the flash memory device further include:
There is one third Serial Peripheral Interface (SPI) flash memory crystal grain third crystal grain identification symbol and a third serial peripheral to connect
Mouth pin group；And
There is one the 4th Serial Peripheral Interface (SPI) flash memory crystal grain one the 4th crystal grain identification symbol and one the 4th serial peripheral to connect
Mouth pin group；
Wherein the encapsulation also has the third Serial Peripheral Interface (SPI) flash memory crystal grain arranged with the stack arrangement
And the 4th Serial Peripheral Interface (SPI) flash memory crystal grain.
8. flash memory device as claimed in claim 7, which is characterized in that
The first Serial Peripheral Interface (SPI) flash memory crystal grain also have there are two crystal grain identification symbol pin, to be coupled to
Establish the first crystal grain identification symbol；
The second Serial Peripheral Interface (SPI) flash memory crystal grain, which also has to recognize there are two crystal grain, accords with pin, to be respectively coupled to
Ground and power supply are to establish the second crystal grain identification symbol；
The third Serial Peripheral Interface (SPI) flash memory crystal grain, which also has to recognize there are two crystal grain, accords with pin, to be respectively coupled to
Power supply and ground are to establish the third crystal grain identification symbol；And
The 4th Serial Peripheral Interface (SPI) flash memory crystal grain, which also has to recognize there are two crystal grain, accords with pin, to be coupled to power supply
To establish the 4th crystal grain identification symbol.
9. flash memory device as described in claim 1, which is characterized in that
The first Serial Peripheral Interface (SPI) flash memory crystal grain includes SPI-NOR flash memory；And
The second Serial Peripheral Interface (SPI) flash memory crystal grain includes SPI-NOR flash memory.
10. flash memory device as described in claim 1, which is characterized in that
The first Serial Peripheral Interface (SPI) flash memory crystal grain includes SPI-NAND flash memory；And
The second Serial Peripheral Interface (SPI) flash memory crystal grain includes SPI-NAND flash memory.
11. flash memory device as described in claim 1, which is characterized in that
The first Serial Peripheral Interface (SPI) flash memory crystal grain includes SPI-NOR flash memory；And
The second Serial Peripheral Interface (SPI) flash memory crystal grain includes SPI-NAND flash memory.
12. a kind of method for executing simultaneously operating, is suitable for a Serial Peripheral Interface (SPI) flash memory device, the serial peripheral
It includes that a chip selects a Serial Peripheral Interface (SPI) of pin to encapsulate pin group that interface quick flash storage device, which has, and feature exists
In the method for the execution simultaneously operating includes:
The selection of one first chip is received actively in the chip selection pin of the Serial Peripheral Interface (SPI) flash memory device
Signal, wherein the Serial Peripheral Interface (SPI) flash memory device includes:
There is one first Serial Peripheral Interface (SPI) flash memory crystal grain one first crystal grain identification symbol and one first serial peripheral to connect
Mouth pin group；And
There is one second Serial Peripheral Interface (SPI) flash memory crystal grain one second crystal grain identification symbol and one second serial peripheral to connect
Mouth pin group；
The first Serial Peripheral Interface (SPI) flash memory crystal grain and the second Serial Peripheral Interface (SPI) flash memory crystal grain heap
Folded and the first Serial Peripheral Interface (SPI) pin group and the second Serial Peripheral Interface (SPI) pin group coupled in parallel are to described
Serial Peripheral Interface (SPI) encapsulates pin group；And
First chip selection active signal be provided in parallel the first Serial Peripheral Interface (SPI) flash memory crystal grain and
The second Serial Peripheral Interface (SPI) flash memory crystal grain；
In conjunction with the step of receiving the first chip selection active signal, the first Serial Peripheral Interface (SPI) of Yu Suoshu flash memory is brilliant
One first crystal grain selection instruction is executed on grain and the second Serial Peripheral Interface (SPI) flash memory crystal grain, with described in enable the
One Serial Peripheral Interface (SPI) flash memory crystal grain responds a Serial Peripheral Interface (SPI) instruction set, and the second serial peripheral described in enable connects
Outspoken flash memory crystal grain only in response to the Serial Peripheral Interface (SPI) instruction set a universal command subset, wherein first crystal grain
Selection instruction specifies one first crystal grain identification symbol to the Serial Peripheral Interface (SPI) flash memory device and the universal command
Subset includes crystal grain selection instruction；
The selection of one first chip is received in the chip selection pin of the Serial Peripheral Interface (SPI) flash memory device to stop
Signal, in the first Serial Peripheral Interface (SPI) flash memory crystal grain and the second Serial Peripheral Interface (SPI) flash memory
The execution of the first crystal grain selection instruction is terminated on crystal grain；
When the first Serial Peripheral Interface (SPI) flash memory crystal grain, which is enabled, responds the Serial Peripheral Interface (SPI) instruction set, in
The chip selection pin of the Serial Peripheral Interface (SPI) flash memory device receives one second chip and selects active signal, institute
It states the second chip selection active signal and is provided to the first Serial Peripheral Interface (SPI) flash memory crystal grain and described the in parallel
Two Serial Peripheral Interface (SPI) flash memory crystal grain；
In conjunction with the step of receiving the second chip selection active signal, the first Serial Peripheral Interface (SPI) of Yu Suoshu flash memory is brilliant
The one first Serial Peripheral Interface (SPI) instruction of a non-universal command is executed on grain, the first Serial Peripheral Interface (SPI) instruction causes in one
The execution of portion's self-timing operation；
The selection of one second chip is received in the chip selection pin of the Serial Peripheral Interface (SPI) flash memory device to stop
Signal, in terminating first Serial Peripheral Interface (SPI) instruction on the first Serial Peripheral Interface (SPI) flash memory crystal grain, but
The internal self-timing operation is not terminated；
Third wafer selection is received actively in the chip selection pin of the Serial Peripheral Interface (SPI) flash memory device
Signal, third wafer selection active signal be provided in parallel the first Serial Peripheral Interface (SPI) flash memory crystal grain and
The second Serial Peripheral Interface (SPI) flash memory crystal grain；
In conjunction with the step of receiving the third wafer selection active signal, the first Serial Peripheral Interface (SPI) of Yu Suoshu flash memory is brilliant
One second crystal grain selection instruction is executed on grain and the second Serial Peripheral Interface (SPI) flash memory crystal grain, with described in enable the
Two Serial Peripheral Interface (SPI) flash memory crystal grain respond the Serial Peripheral Interface (SPI) instruction set, and the first serial peripheral described in enable
Interface quick flash storage crystal grain is only in response to the universal command subset, wherein the second crystal grain selection instruction specified one second is brilliant
Grain identification symbol is to the Serial Peripheral Interface (SPI) flash memory device；
Third wafer selection is received in the chip selection pin of the Serial Peripheral Interface (SPI) flash memory device to stop
Signal, in the first Serial Peripheral Interface (SPI) flash memory crystal grain and the second Serial Peripheral Interface (SPI) flash memory
The execution of the second crystal grain selection instruction is terminated on crystal grain；
When the second Serial Peripheral Interface (SPI) flash memory crystal grain, which is enabled, responds the Serial Peripheral Interface (SPI) instruction set, in
The chip selection pin of the Serial Peripheral Interface (SPI) flash memory device receives one the 4th chip and selects active signal, institute
It states the 4th chip selection active signal and is provided to the first Serial Peripheral Interface (SPI) flash memory crystal grain and described the in parallel
Two Serial Peripheral Interface (SPI) flash memory crystal grain；
In conjunction with the step of receiving the 4th chip selection active signal, the second Serial Peripheral Interface (SPI) of Yu Suoshu flash memory is brilliant
The instruction of one second Serial Peripheral Interface (SPI) is executed on grain, and is synchronized on the first Serial Peripheral Interface (SPI) flash memory crystal grain and is held
The row internal self-timing operation；And
The selection of one the 4th chip is received in the chip selection pin of the Serial Peripheral Interface (SPI) flash memory device to stop
Signal, to terminate the second Serial Peripheral Interface (SPI) instruction.
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| CN109637564A (en) | 2018-12-20 | 2019-04-16 | 惠州Tcl移动通信有限公司 | With more storage crystal grain storage devices and recognition methods |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1790707A (en) * | 2004-12-16 | 2006-06-21 | 希旺科技股份有限公司 | Multi-mode quickflashing memory IC |
| CN101055552A (en) * | 2006-04-13 | 2007-10-17 | 英特尔公司 | Multiplexing a parallel bus interface and a flash memory interface |
| CN103151066A (en) * | 2011-12-06 | 2013-06-12 | 华邦电子股份有限公司 | Flash memory for storing codes and data |
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| US20050285248A1 (en) * | 2004-06-29 | 2005-12-29 | Sun-Teck See | Method and system for expanding flash storage device capacity |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1790707A (en) * | 2004-12-16 | 2006-06-21 | 希旺科技股份有限公司 | Multi-mode quickflashing memory IC |
| CN101055552A (en) * | 2006-04-13 | 2007-10-17 | 英特尔公司 | Multiplexing a parallel bus interface and a flash memory interface |
| CN103151066A (en) * | 2011-12-06 | 2013-06-12 | 华邦电子股份有限公司 | Flash memory for storing codes and data |
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