CN105304130A - Flash memory apparatus and method for performing synchronous operation - Google Patents
Flash memory apparatus and method for performing synchronous operation Download PDFInfo
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- CN105304130A CN105304130A CN201410365975.4A CN201410365975A CN105304130A CN 105304130 A CN105304130 A CN 105304130A CN 201410365975 A CN201410365975 A CN 201410365975A CN 105304130 A CN105304130 A CN 105304130A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention provides a flash memory apparatus and a method for performing a synchronous operation. The flash memory apparatus comprises first serial peripheral interface (SPI) flash memory crystal particles with a first crystal particle identifier and a first SPI pin group, second SPI flash memory crystal particles with a second crystal particle identifier and a second SPI pin group, and a package with the first SPI flash memory crystal particles and the second SPI flash memory crystal particles arranged in a stack layout manner as well as an SPI package pin group, wherein the SPI package pin group is coupled to the first SPI pin group and the second SPI pin group in parallel. The flash memory apparatus has the advantage of an SPI flash memory and relatively high data storage capacity, and can be compatible with applications of local execution and code mapping.
Description
Technical field
The present invention is relevant a kind of flash memory, relates to especially and utilizes stacking memory crystal grain and the flash memory device of Serial Peripheral Interface (SPI).
Background technology
The hot topic that string type flash memory has become traditional block form flash memory substitutes storer.String type flash memory provides many advantages, comprises little, the low pin count of package area, simplifies printed circuit board layout, low power consumption, performance equals to block form flash memory and the cost of the Apparatus and system level of correspondence is lower.Serial Peripheral Interface (SPI) is used in string type flash memory widely, and the configuration of device is carried out (comprising multidigit instruction and (or) address input and long numeric data to export) by unit or multidigit Serial Peripheral Interface (SPI), receive an acclaim especially at present.Serial Peripheral Interface (SPI) has many advantages: unit Serial Peripheral Interface (SPI) allows compatibility widely, and multidigit Serial Peripheral Interface (SPI) and some flash memories in conjunction with time, " code mapping (codeshadowing) " can be allowed fast under high sequential speed to the code storage application such as random access memory and " local perform (XIP) ".
String type flash memory can provide the capacity of 512Kb to 1Gb usually.But for high density string type flash memory, the demand of every lower cost continues to increase.Wherein, though single high density crystal grain its cost feasible is higher, therefore can by the highdensity string type flash memory device of the stacking composition of low-density crystal grain of identical type using as a replacement scheme.For example, the string type flash memory crystal grain that can be by density two identical types of 256Mb is stacking with the device of formation capacity for 512Mb (2x256Mb), or is that the string type flash memory crystal grain of four identical types of 256Mb is stacking with the device of formation capacity for 1Gb (4x256Mb) by density.
In addition, can be stacking to form the single storage arrangement with different qualities by dissimilar flash memory crystal grain.Flash memory has NOR flash memory and NAND quick-flash memory usually, in NOR flash memory, each memory cell is connected between bit line and ground connection, and in NAND quick-flash memory, several memory cell series connection is connected between bit line and ground connection.Wherein, NOR flash memory generally has the characteristics such as low-density, high reading speed, low writing speed, low erasing speed and random access, and NAND quick-flash memory generally has high density, middle reading speed, high page writing speed, high erasing speed and indirectly or with characteristics such as the accesses of I/O mode.NOR flash memory is because can carry out random access; microprocessor can use NOR flash memory to carry out fast " code mapping " to the application such as random access memory and " local execution " usually; and NAND quick-flash memory is because of its high speed sequence write capability and high density but the characteristic of low cost, it is made to be specially adapted to the high system of data storage capacities demand.In addition, the NAND quick-flash memory of some type has been modified to the characteristic providing similar SPI-NOR flash memory in the application of code mapping at present.
There is the current still imperfection of operative technique of the Serial Peripheral Interface (SPI) flash memory device of stacked die." SpansionInc.; DataSheet; S70FL256P256-MbitCMOS3.0VoltFlashMemorywith104-MHzSPIMul tiI/OBus; Revision05; January30; 2013 " discloses and two identical 128Mb crystal grain is carried out heap poststack, then by other/CS pin is welded to the Serial Peripheral Interface (SPI) flash memory device that the upper different corresponding pin of encapsulation is formed.Unfortunately, it needs by controller to provide and to manage multiple/CS control signal, in addition, have more /CS pin requirement also can make this Serial Peripheral Interface (SPI) flash memory device cannot carry out the encapsulation of eight pins.
" MicronTechnologyInc.; N25Q512A1.8V; MultipleI/OSerialFlashMemory; September2013 " discloses two different crystal grain heap poststacks, except the reading of regarding memory and erase operation, just the angle of user can be considered the flash memory device of single device.But though said apparatus can in eight pin encapsulation, carry out the operation of quaternary I/O serial peripheral interface protocol, its manufacturing cost is often higher because of the particular design of its complexity.
Summary of the invention
The invention provides a kind of flash memory device and perform the method for synchronous operation, there is Serial Peripheral Interface (SPI) (SerialPeripheralInterface, SPI) advantage of flash memory, and higher data storage capacities, further, compatiblely in certain embodiments to perform and the application of code mapping in this locality.The present invention includes following example embodiment.
One embodiment of the invention provides a kind of flash memory device, comprising: one first Serial Peripheral Interface (SPI) flash memory crystal grain, has one first crystal grain identification symbol, and the first Serial Peripheral Interface (SPI) pin group; One second Serial Peripheral Interface (SPI) flash memory crystal grain, has one second crystal grain identification symbol, and the second Serial Peripheral Interface (SPI) pin group; And one encapsulates, have with the first Serial Peripheral Interface (SPI) flash memory crystal grain of a stack arrangement arrangement and the second Serial Peripheral Interface (SPI) flash memory crystal grain, and there is a Serial Peripheral Interface (SPI) encapsulation pin group, with the first Serial Peripheral Interface (SPI) pin group and the second Serial Peripheral Interface (SPI) pin group coupled in parallel.
Another embodiment of the present invention provides a kind of method performing synchronous operation in Serial Peripheral Interface (SPI) flash memory device, and wherein Serial Peripheral Interface (SPI) flash memory device has the Serial Peripheral Interface (SPI) encapsulation pin group comprising a wafer selection pin.The Serial Peripheral Interface (SPI) flash memory device be applicable in said method comprises one first Serial Peripheral Interface (SPI) flash memory crystal grain, has one first crystal grain identification symbol and the first Serial Peripheral Interface (SPI) pin group; And one second Serial Peripheral Interface (SPI) flash memory crystal grain, there is one second crystal grain identification symbol and the second Serial Peripheral Interface (SPI) pin group; First Serial Peripheral Interface (SPI) flash memory crystal grain and the second Serial Peripheral Interface (SPI) flash memory crystal grain stacking, and the first Serial Peripheral Interface (SPI) pin group and the second Serial Peripheral Interface (SPI) pin group and Serial Peripheral Interface (SPI) encapsulate pin group coupled in parallel.The wafer that method is included in Serial Peripheral Interface (SPI) flash memory device selects pin to receive the first wafer selection active signal, and the first wafer selects active signal to be provided to the first Serial Peripheral Interface (SPI) memory crystal grain and the second Serial Peripheral Interface (SPI) memory crystal grain with parallel; And the step of active signal is selected in conjunction with reception first wafer, on the first Serial Peripheral Interface (SPI) flash memory crystal grain and the second Serial Peripheral Interface (SPI) flash memory crystal grain, perform the first crystal grain selection instruction respond a Serial Peripheral Interface (SPI) instruction set with activation first Serial Peripheral Interface (SPI) flash memory crystal grain, and the above-mentioned second Serial Peripheral Interface (SPI) flash memory crystal grain of activation only responds a universal command subset, universal command subset is the subset of Serial Peripheral Interface (SPI) instruction set and comprises crystal grain selection instruction.Method also comprises selects pin to receive the first wafer selection stop signal to stop the execution of the first crystal grain selection instruction on the first Serial Peripheral Interface (SPI) flash memory crystal grain and the second Serial Peripheral Interface (SPI) flash memory crystal grain from the wafer of Serial Peripheral Interface (SPI) flash memory device.Method also comprises when the first Serial Peripheral Interface (SPI) flash memory crystal grain is enabled response Serial Peripheral Interface (SPI) instruction set, select pin to receive the second wafer in the wafer of Serial Peripheral Interface (SPI) flash memory device and select active signal, the second wafer selects that active signal is parallel is provided to the first Serial Peripheral Interface (SPI) flash memory crystal grain and the second Serial Peripheral Interface (SPI) flash memory crystal grain; And the step of active signal is selected in conjunction with reception second wafer, on the first Serial Peripheral Interface (SPI) flash memory crystal grain, perform the first Serial Peripheral Interface (SPI) instruction of non-universal instruction, cause the execution of an inner self-timing operation (internalself-timedoperation).The wafer that method is also included in Serial Peripheral Interface (SPI) flash memory device selects pin to receive the second wafer selection stop signal to stop the first Serial Peripheral Interface (SPI) instruction on the first Serial Peripheral Interface (SPI) flash memory crystal grain, but does not stop inner self-timing operation.The wafer that method is also included in Serial Peripheral Interface (SPI) flash memory device is selected pin to receive wafer and is selected active signal, and wafer selects that active signal is parallel is provided to the first Serial Peripheral Interface (SPI) flash memory crystal grain and the second Serial Peripheral Interface (SPI) flash memory crystal grain; And the step of active signal is selected in conjunction with reception wafer, on the first Serial Peripheral Interface (SPI) flash memory crystal grain and the second Serial Peripheral Interface (SPI) flash memory crystal grain, perform the second crystal grain selection instruction respond above-mentioned Serial Peripheral Interface (SPI) instruction set with activation second Serial Peripheral Interface (SPI) flash memory crystal grain, and activation first Serial Peripheral Interface (SPI) flash memory crystal grain response universal command subset, wherein said second crystal grain selection instruction specifies one second crystal grain identification to accord with to described serial circumference flash memory device.The wafer that method is also included in Serial Peripheral Interface (SPI) flash memory device selects pin to receive wafer selection stop signal, to stop the execution of the second crystal grain selection instruction on the first Serial Peripheral Interface (SPI) flash memory crystal grain and the second Serial Peripheral Interface (SPI) flash memory crystal grain.Method also comprises when the second Serial Peripheral Interface (SPI) flash memory crystal grain is enabled response Serial Peripheral Interface (SPI) instruction set, select pin to receive the 4th wafer in the wafer of Serial Peripheral Interface (SPI) flash memory device and select active signal, the 4th wafer selects that active signal is parallel is provided to the first Serial Peripheral Interface (SPI) flash memory crystal grain and the second Serial Peripheral Interface (SPI) flash memory crystal grain; And combine the step receiving above-mentioned 4th wafer selection active signal, on the second Serial Peripheral Interface (SPI) flash memory crystal grain, perform the second Serial Peripheral Interface (SPI) instruction, in the first Serial Peripheral Interface (SPI) memory crystal grain, perform inner self-timing operation simultaneously.The wafer that method is also included in Serial Peripheral Interface (SPI) storage arrangement selects pin to receive the 4th wafer selection stop signal to stop the second Serial Peripheral Interface (SPI) instruction.
The invention provides a kind of flash memory device and perform the method for synchronous operation, multiple stacking flash memory crystal grain only needs single one physical/CS pin; Eight pin encapsulation of all serial peripheral interface protocols can be performed, comprise quaternary serial peripheral interface protocol; The operation of some Serial Peripheral Interface (SPI)s can synchronous operation; Only need to carry out small part correction to existing Serial Peripheral Interface (SPI) flash memory die design; Be applicable to traditional multi-die package technology; Can the flash memory crystal grain of stacking heterogeneous (heterogeneous) to reach multi-functional and target usefulness.Can be compatible with traditional flash memory instruction set, and expand by " crystal grain selection " instruction.
Accompanying drawing explanation
Fig. 1 display has the calcspar of the Serial Peripheral Interface (SPI) flash memory device of stacking Serial Peripheral Interface (SPI) flash memory crystal grain according to one embodiment of the invention.
Fig. 2 display has the calcspar of the Serial Peripheral Interface (SPI) flash memory device of stacking Serial Peripheral Interface (SPI) flash memory crystal grain according to another embodiment of the present invention.
Fig. 3 shows the calcspar of crystal grain selection instruction.
Fig. 4 is shown in the calcspar performing synchronous operation instruction sequence in the Serial Peripheral Interface (SPI) flash memory device with stacking Serial Peripheral Interface (SPI) flash memory crystal grain.
Fig. 5 shows the calcspar that another performs synchronous operation instruction sequence in the Serial Peripheral Interface (SPI) flash memory device with stacking Serial Peripheral Interface (SPI) flash memory crystal grain.
Fig. 6 shows the operational flowchart of the Serial Peripheral Interface (SPI) flash memory crystal grain of response crystal grain selection instruction.
Fig. 7 is shown in the side plan view of a kind of crystal grain Stack Technology utilizing pad between crystal grain.
Fig. 8 shows the side plan view of a kind of crystal grain Stack Technology utilizing crystal grain to interlock.
Fig. 9 shows the side plan view of a kind of crystal grain Stack Technology utilizing the crystal grain varied in size.
Symbol description:
10,20,70,90,100 ~ Serial Peripheral Interface (SPI) flash memory device;
11,12,13,14,21,22,23,24,72,74,92,94,102,104 ~ Serial Peripheral Interface (SPI) flash memory crystal grain;
60,61,62,64,66,68 ~ steps flow chart;
71,91,101 ~ encapsulation main body;
73 ~ spacer;
75,95,105 ~ sticker;
76,96,106 ~ cooling pad;
77,78,97,107,108 ~ region;
81,82,83,84,98,99,111,112,113,114 ~ lead-in wire;
93,103 ~ material.
Embodiment
In herein, " Serial Peripheral Interface (SPI) flash memory crystal grain " (hereinafter referred flash memory crystal grain) refers to the integrated-circuit die of the flash memory array comprising any pattern, and it is configured with the group of pins being compatible with serial peripheral interface protocol.Any amount of flash memory crystal grain carries out stacking and encapsulation by utilizing any required multi-die package technology.Wherein, can be during manufacture, individually unique crystal grain identification symbol (DieID) is first specified to each stacking flash memory crystal grain in encapsulation, and during general operation, by specifying different crystal grain identification symbols to crystal grain selection instruction (DieSelect), with the subsequent instructions on the one of activation stacking flash memory crystal grain response Serial Peripheral Interface (SPI), and in activation encapsulation, other stacking flash memory crystal grain only respond some universal command (such as crystal grain selection instruction) follow-up on Serial Peripheral Interface (SPI).
In herein, " pin " refers to the conducting element being connected to flash memory crystal grain in order to direct or indirect exposed electrical, no matter comprise is conducting element (such as pad (bondingpad)) on crystal grain, or is embedded in conducting element (contact (recessedcontact) of such as caving in, concordant contact (flushcontact), outstanding contact (projectingcontact)) in the upper or encapsulation of encapsulation etc.
In herein, " Serial Peripheral Interface (SPI) pin " and " Serial Peripheral Interface (SPI) encapsulation pin " refers to the pin being compatible with serial peripheral interface protocol.According to serial peripheral interface protocol, six pins can be configured to single Serial Peripheral Interface (SPI) (singleSPI), two Serial Peripheral Interface (SPI) (dualSPI), quaternary Serial Peripheral Interface (SPI) (quadSPI), or quaternary Peripheral Interface (QuadPeripheralInterface, QPI, also referred to as serial quaternary interface (SerialQuadInterface, SQI)), and single position or multidigit instruction and (or) address input and single position or long numeric data input can be comprised and (or) export, its configurability may comprise expected any subset in said structure.Six pins provide wafer selection/CS, sequential CLK, configurable pin DI (IO
0), configurable pin DO (IO
1), configurable pin/WP (IO
2) and configurable pin/HOLD (IO
3).For single bit serial Peripheral Interface operation, configurable pin is in order to export DO, write protection/WP and maintenance/HOLD as instruction/address/data input DI, data.For two serial peripheral equipment interface SPI, configurable pin is in order to as I/O IO
0, I/O IO
1, write protection/WP and maintenance/HOLD.For quaternary serial peripheral equipment interface SPI and quaternary Peripheral Interface QPI, configurable pin is in order to as I/O IO
0, I/O IO
1, I/O IO
2, and I/O IO
3.
Do not cause the operation of bus-bar access conflict can be executed on different flash memory crystal grain simultaneously.Many operations, by instruction (having or do not have the operational code of address) incoming serial Peripheral Interface bus-bar is opened the beginning, then carry out self-timing operation by the control of internal control circuit, about continue during it millisecond to second not etc.Aforesaid operations is such as comprise program/erase memory array, write state working storage and the safe working storage of program/erase.The built-in function comprised due to the execution of above-mentioned instruction does not relate to the access of any bus-bar, and therefore these operations are applicable to relating to other similar operations or other operation synchronous operation confluxing and access.The operational example initial part (NOR) that memory array reads as comprised, state reads, device identification symbol reads, SFDP reads, safe working storage reads, cache is loaded into (NAND) and storer coding of access of confluxing still must be related to after sending instruction.
The flash memory crystal grain of whole identical type is used to carry out stacking attainable higher memory density.Fig. 1 display comprises the Serial Peripheral Interface (SPI) flash memory device 10 of four stacking identical flash memory crystal grain 11,12,13 and 14.Flash memory crystal grain 11,12,13 and 14 is respectively configured with six Serial Peripheral Interface (SPI) pins, and power supply (Vcc) amounts to eight pins with ground connection (GND) etc.And flash memory crystal grain 11,12,13 and 14 such as can comprise NOR, NAND or any suitable flash memory crystal grain.Be utilize four flash memory crystal grain to carry out stacking in the present embodiment, but the present invention is not limited thereto.In other embodiments, the flash memory crystal grain of any amount also can be utilized to carry out stacking.
In another embodiment of the invention, also different flash memory crystal grain can be selected to carry out stacking, by selecting the flash memory crystal grain of different capacity and characteristic, flash memory device can be made to provide enough capacity and characteristic specifically to apply to meet some.Fig. 2 display has stacking SPI-NOR flash memory crystal grain 21 and the Serial Peripheral Interface (SPI) flash memory device 20 of SPI-NAND flash memory crystal grain 22,23 and 24.Wherein above-mentioned SPI-NOR flash memory crystal grain 21 is specially adapted to the application of coding, such as local execution and code mapping, above-mentioned SPI-NAND flash memory crystal grain 22,23 and 24 is then specially adapted to data storing, and piles the density that poststack can provide very high.Flash memory crystal grain 21,22,23 and 24 comprises other crystal grain identification symbol, the order revised and steering logic to respond crystal grain selection instruction.Two SPI-NOR flash memory crystal grain and two SPI-NAND flash memory crystal grain can be carried out stacking by if desired random access memory faster, or additionally increase SPI-NOR flash memory.The SPI-NAND flash memory crystal grain (not shown) being applicable to code storage application also can replace SPI-NOR flash memory crystal grain 21, such as, can disclose SPI-NAND flash memory with reference to U.S. Patent Publication No. US2012/0084491.Memory array size in stacking each flash memory crystal grain can be identical or different, also or part is identical or part is different.For example, in the flash memory device 20 shown in Fig. 2, SPI-NOR flash memory crystal grain 21 does not need comparatively large, and for many general XIP and code mapping, such as 16-32Mb is enough; SPI-NAND flash memory crystal grain then can be comparatively large, and such as 1Gb, to provide the data storing that many application are generally enough.Above-mentioned capacity is only rough description, and it may increase because of the development of manufacturing technology.
Each flash memory crystal grain 21,22,23 and 24 is respectively configured with six Serial Peripheral Interface (SPI) pins, and power supply (Vcc) amounts to eight pins with ground connection (GND) etc.And flash memory crystal grain 21,22,23 and 24 such as can comprise NOR, NAND or any suitable flash memory crystal grain.
Disclosed Serial Peripheral Interface (SPI) flash memory device can provide the combination of what follows any one or multiple advantage, and may also have other advantages: (a) multiple stacking flash memory crystal grain only needs single one physical/CS pin; B () can perform eight pin encapsulation of all serial peripheral interface protocols, comprise quaternary serial peripheral interface protocol; C the operation of () some Serial Peripheral Interface (SPI)s can synchronous operation; D () only needs to carry out small part correction to existing Serial Peripheral Interface (SPI) flash memory die design; E () is applicable to traditional multi-die package technology; And (f) can the flash memory crystal grain of stacking heterogeneous (heterogeneous) to reach multi-functional and target usefulness.
Disclosed Serial Peripheral Interface (SPI) flash memory device uses stacking flash memory crystal grain to form, can be compatible with traditional flash memory instruction set, and expands by " crystal grain selection " instruction.For example, as shown in Figure 3, crystal grain selection instruction can be the instruction (such as C2 sexadecimal crystal grain select operational code (hexopcode)) of two hytes, and the crystal grain identification symbol of eight of continuing.Wherein, although the figure place needed for crystal grain identification symbol depends on the maximum number of stackable flash memory crystal grain in Serial Peripheral Interface (SPI) flash memory device, and it only needs two can specify four stacking flash memory crystal grain, but still the crystal grain identification symbol length of eight can be retained, accord with to make the crystal grain identification of call instruction and end at hyte border according to general custom.
Crystal grain selection instruction selects other any flash memory crystal grain in multiple grain stacked package in the following manner.Crystal grain selection instruction accords with the specific die identification of the flash memory crystal grain for accessing and is together sent to Serial Peripheral Interface (SPI) flash memory device by controller (not shown).Then; stacking all flash memory crystal grain all can run crystal grain selection instruction; the flash memory crystal grain wherein meeting described crystal grain identification symbol can be enabled as responding all Serial Peripheral Interface (SPI) instruction set (SPIinstructionset); other flash memory crystal grain then can be enabled as the subset only responding Serial Peripheral Interface (SPI) instruction set (refers to general subset of instructions herein; but do not respond other Serial Peripheral Interface (SPI) instruction set Universalinstructionsubset).If during for support synchronous operation, the order of non-selection crystal grain and steering logic can continue to perform any current ongoing built-in function.In the order that this function can be designed to each stacking flash memory crystal grain and steering logic.
Fig. 4 and Fig. 5 is an example of synchronous operation, and example is herein synchronous erasing and reads.For the sake of clarity, other signals multiple conventional during instruction sequence are omitted.Above-mentioned signal comprises/CS signal, and for example ,/CS signal is converted to low with selecting arrangement before each instruction, and is being converted to height when allowing internal erase, coding and write state working storage loop to complete instruction./ CS signal is used in this method together with crystal grain selection instruction by aforesaid way.
The instruction sequence that Fig. 4 illustrates starts from crystal grain and selects operational code DS, then be crystal grain identification symbol 0, then be erase operation code ER (being such as a wafer erasing instruction (ChipEraseinstruction)), make crystal grain 0 at/CS signal when low conversion is paramount, perform inner self-timing erase operation.Ensuing instruction sequence is that operational code DS selected by crystal grain, is then crystal grain identification symbol 1, is then read opcode RD, relevant address bit ADR and redundant digit DMY, makes crystal grain 1 perform read operation.Wherein, described read operation opens the beginning at/CS signal when being converted to low from height, and completes when low conversion is paramount at/CS signal.In this example, the time of read operation is longer than erase operation.Ensuing instruction sequence is that operational code DS selected by crystal grain, then be crystal grain identification symbol 0, then be reading state working storage operational code RSR, in order to the data (the BUSY position SO in such as state working storage 1) in reading state working storage, to confirm whether erase operation completes.For example, when Serial Peripheral Interface (SPI) flash memory crystal grain performs internal erase, coding or write state working storage loop, the only read bit of BUSY position for being set as 1.In this, crystal grain 0 is undertaken responding to represent that erase operation is no longer performed by the data in state working storage, and crystal grain 0 has been ready to perform other operations.
The instruction sequence that Fig. 5 illustrates starts from crystal grain and selects operational code DS, then for crystal grain identification accords with 0, is then erase operation code ER, makes crystal grain 0 at/CS signal when low conversion is paramount, performs inner self-timing erase operation.Ensuing instruction sequence is that operational code DS selected by crystal grain, is then crystal grain identification symbol 1, is then read opcode RD, relevant address bit ADR and redundant digit DMY, makes crystal grain 1 perform read operation.Wherein, described read operation opens the beginning at/CS signal when being converted to low from height, and completes when low conversion is paramount at/CS signal.In this example, the time of read operation is shorter than erase operation, and completes read operation before completing erase operation.Ensuing instruction sequence is that operational code DS selected by crystal grain, and being then crystal grain identification symbol 0, is then reading state working storage operational code RSR, in order to the data in reading state working storage, to confirm whether erase operation completes.Now, although the internal erase instruction of crystal grain 0 is still in execution, crystal grain 0 becomes the selected crystal grain selected because of response crystal grain selection instruction, and is undertaken responding to represent erase operation still in execution by the data in state working storage.Ensuing instruction sequence is another reading state working storage operational code RSR, in order to reaffirm the data in state working storage.Now, crystal grain 0 is undertaken responding to represent that erase operation is no longer performed by the data in state working storage, and crystal grain 0 has been ready to perform other operations.
Fig. 6 shows the flowchart of crystal grain selection instruction.First, crystal grain selection instruction (square 60) is received.Meanwhile, if there is any ongoing inner self-timing operation, then continue to carry out operating (square 61).Then, whether the crystal grain identification symbol comparing each crystal grain in stacked die meets crystal grain identification symbol (square 62) being connected in crystal grain selection instruction.If detect, both meet, then full serial Peripheral Interface instruction set execution mode (square 64) is put into or be retained in this flash memory crystal grain, above-mentioned full serial Peripheral Interface instruction set execution mode is the mode standard that flash memory crystal grain can respond all instructions in whole Serial Peripheral Interface (SPI) instruction set.If do not detect, both meet, then put into flash memory crystal grain or remain in universal command subset execution pattern (square 66).Above-mentioned universal command subset execution pattern is the new model that flash memory crystal grain only responds universal command." universal command " described in the present invention refers to a subset of Serial Peripheral Interface (SPI) instruction set, and described subset comprises crystal grain selection instruction and some stereotyped command (such as device replacement).Wherein, no matter whether flash memory crystal grain can respond whole Serial Peripheral Interface (SPI) instruction set, and it all can respond described subset.This execution flow process may be implemented in the method for any expectation, such as hardware, firmware, software, state machine, combination above-mentioned arbitrarily, or in any other method.
Stacking flash memory crystal grain can carry out much dissimilar synchronous operation.Because the time demand of the internal erase in flash memory, programming and write operation is different, the ability stacking flash memory crystal grain being had can perform different instruction respectively advantageously can increase data throughout (throughput) during general operation, and promotes during system manufacture high efficiency " coding is downloaded ".For example, synchronous operation is particularly conducive to " reading (ReadwhileWrite) during write ", and (state working storage writes, no matter be 0 to 1 or 1 to 0), " read during program/erase " (tcp data segment not comprising SPI-NOR programming instruction), and " multiple grain program/erase " (not comprising the tcp data segment of SPI-NOR programming instruction).Although be described with two synchronous operations at this, the present invention is not limited thereto, the quantity of synchronous operation also can with the quantity of stacking flash memory crystal grain as many.Each stacking flash memory crystal grain is by the indivedual activation of crystal grain selection instruction, and by reading state working storage to confirm its state, such as this crystal grain is performing write, programming or erase operation and cannot receive new instruction, or can receive new instruction.
When electric power starting, on demand a specific die (such as crystal grain identification symbol is the crystal grain of " 00 ") can be appointed as initiatively crystal grain.And before general operation, SFDP (SerialFlashDiscoverableParameters) instruction identification Serial Peripheral Interface (SPI) flash memory device can be used whether to have stacked die and support the function of " crystal grain selection ".In order to reach this object, the header (header) of a vendor-specific SFDP can be added in main SFDP form.
Unique crystal grain identification symbol can be assigned to each stacking flash memory crystal grain by any technology in the fabrication process.For example, different crystal grain identification symbol positions can be provided on demand in working storage, and carry out the stacking of crystal grain again after institute's rheme being programmed in advance in the fabrication process.Because working storage position is very little, punishment (spacepenalty) of therefore can not having living space.But it is noted that when stacked die must carefully stacking in the crystal grain identification symbol of all flash memory crystal grain do not repeat each other, and carry out stacking with suitable order.In addition, also crystal grain identification can be provided on flash memory crystal grain to accord with pin (DieIDpin) (being such as pad), and by rights above-mentioned pad is wire bonded to VCC or GND to set up other unique crystal grain identification symbol to the flash memory crystal grain in stacking.For example, when having two flash memory crystal grain, the crystal grain identification of the first flash memory crystal grain symbol pin can be wire bonded to GND to set up the first crystal grain identification symbol, and the crystal grain identification of the second flash memory crystal grain symbol pin be wire bonded to Vcc to set up the second crystal grain identification symbol, when having four flash memory crystal grain, two crystal grain identification symbol pins can be provided to each flash memory crystal grain, two crystal grain identification symbol pins of the first flash memory crystal grain are wire bonded to GND to set up the first crystal grain identification symbol, two crystal grain identification symbol pins of the second flash memory crystal grain are wire bonded to GND and Vcc respectively to set up the second crystal grain identification symbol, two crystal grain identification symbol pins of the 3rd flash memory crystal grain are wire bonded to Vcc and GND respectively to set up the 3rd crystal grain identification symbol, and two crystal grain identification symbol pins of the 4th flash memory crystal grain are wire bonded to Vcc to set up the 4th crystal grain identification symbol.When providing crystal grain identification to accord with working storage position, crystal grain identification symbol pin can in order to input as the logic being inputed to crystal grain identification symbol working storage position by other transmission gate pole.Although crystal grain identification symbol pin can cause space to punish (particularly when it is for weld pad), advantageously, the risk of specifying crystal grain identification to accord with mistakenly by this mode is very low.
Although stacking flash memory crystal grain may be positioned in the encapsulation more than eight pins, and the technology disclosed by the present invention can merge with other additional pins to be applied, but the technology disclosed by the present invention advantageously can make multiple stacking flash memory crystal grain be applicable to simply and have eight pins encapsulation of minimum floorage.Because the layout in system printed circuit board only accounts for minimum floorage, eight pin encapsulation (such as small outline integrated circuit encapsulation (SmallOutlineIntegratedCircuit, SOIC) and WSON (VeryVeryThinSmallOutlineNoLead)) are still widely used in string type flash memory device.
Fig. 7 schematically illustrates the side view that comprises the Serial Peripheral Interface (SPI) flash memory device 70 of two the stacking eight pin WSON types of flash memory crystal grain 72 and 74 in encapsulation main body 71.Although can use any applicable Stack Technology, the Serial Peripheral Interface (SPI) flash memory device of the present embodiment schematically uses spacer (spacerbody) 73 to guarantee there are enough spaces between the lead-in wire at the bottom of flash memory crystal grain 72 and the top of flash memory crystal grain 74 and corresponding bonding wire (wirebond) (such as go between 83,84 and corresponding bonding wire).Spacer 73 can be any suitable type, such as, for having the solid of the material of top and bottom bonding plane, thicker viscosity solid or other sticky materials.Flash memory crystal grain 74 uses any applicable technology to depend on cooling pad 76, such as, be sticker 75 or other sticky materials.Flash memory crystal grain 72 and 74 is wire bonded on multiple wires of lead frame (leadframe) and (such as passes through the bonding wire of lead-in wire 81,82,83,84 and correspondence).Multiple wires of lead frame are exposed to encapsulation main body 71 outer (as region 77 and 78) to provide pad to be connected to external circuit.
Fig. 8 schematically illustrates the side view that comprises the Serial Peripheral Interface (SPI) flash memory device 90 of two the stacking eight pin WSON types of flash memory crystal grain 92 and 94 in encapsulation main body 91.Serial Peripheral Interface (SPI) flash memory device 90 use stacking migration technology with avoid bottom flash memory crystal grain 92 and the lead-in wire at flash memory crystal grain 94 top and correspondence bonding wire (bonding wire of 99 and the correspondence of such as going between) between interference.Flash memory crystal grain 92 and 94 utilize any applicable material 93 be fixed on stacking among, be such as solid or the sticker of the material with top and bottom bonding plane.Flash memory crystal grain 94 utilizes any applicable technology to adhere to cooling pad 96, such as, be sticker 95 or other sticky materials.Flash memory crystal grain 92 and 94 is wire bonded on multiple wires of lead frame and (such as passes through the bonding wire of lead-in wire 98,99 and correspondence).Multiple wires of lead frame are exposed to encapsulation main body 91 outer (as region 97) to provide pad to be connected to external circuit.
Fig. 9 schematically illustrates the side view that comprises the Serial Peripheral Interface (SPI) flash memory device 100 of two the stacking eight pin WSON types of flash memory crystal grain 102 and 104 in encapsulation main body 101.Although can use any applicable Stack Technology, the Serial Peripheral Interface (SPI) flash memory device 100 of the present embodiment uses the crystal grain of different size or shape to avoid the interference between the lead-in wire at the bottom of flash memory crystal grain 102 and the top of flash memory crystal grain 104 and corresponding bonding wire (such as go between 113,114 and corresponding bonding wire).Flash memory crystal grain 102 and 104 utilize any applicable material 103 be fixed on stacking among, be such as solid or the sticker of the material with top and bottom bonding plane.Flash memory crystal grain 104 utilizes any applicable technology to adhere to cooling pad 106, such as, be sticker 105 or other sticky materials.Flash memory crystal grain 102 and 104 is wire bonded on multiple wires of lead frame and (such as passes through the bonding wire of lead-in wire 111,112,113,114 and correspondence).Multiple wires of lead frame are exposed to encapsulation main body 101 outer (as region 107 and 108) to provide pad to be connected to external circuit.
Do not need mutually exclusive in the Stack Technology described in the present invention and other Stack Technologies, and two or more above-mentioned technology can be used for the manufacture of any given stack.Prior art has disclosed many different Stack Technologies, such as can See U. S. Patent publication number No. US2011/0195529 content of taking off.Although the mode with wire bond in Fig. 7-9 is described, any other is applicable to the solder technology (such as boring a hole (via)) between crystal grain and encapsulation pin, also can in order to replace or to be combined with wire bond.
Embodiment disclosed by this instructions, is that patent requirements scope of the present invention is described, and is not used to limit scope of the present invention, and protection scope of the present invention is when being as the criterion with the claim person of defining.The amendment of embodiment disclosed in the present invention and be changed to feasible, and art technician is by reading the present invention with the object described in actual alternate embodiment.In addition, particular value described herein only exemplarily, and can according to required and change.Not departing from spirit of the present invention and scope, other changes or amendment can be done the embodiment disclosed by the present invention, also comprise the replacement of multiple elements of embodiment, and protection scope of the present invention only defined by claim.
Claims (13)
1. a flash memory device, is characterized in that, this flash memory device comprises:
One first Serial Peripheral Interface (SPI) flash memory crystal grain, has one first crystal grain identification symbol and one first Serial Peripheral Interface (SPI) pin group;
One second Serial Peripheral Interface (SPI) flash memory crystal grain, has one second crystal grain identification symbol and one second Serial Peripheral Interface (SPI) pin group; And
One encapsulation, has with the described first Serial Peripheral Interface (SPI) flash memory crystal grain of a stack arrangement arrangement and described second Serial Peripheral Interface (SPI) flash memory crystal grain, and has a Serial Peripheral Interface (SPI) encapsulation pin group;
Wherein, described Serial Peripheral Interface (SPI) encapsulation pin group coupled in parallel extremely described first Serial Peripheral Interface (SPI) pin group and described second Serial Peripheral Interface (SPI) pin group respectively.
2. flash memory device as claimed in claim 1, is characterized in that,
Described first Serial Peripheral Interface (SPI) flash memory crystal grain comprises one first order and steering logic, in order to according to a crystal grain selection instruction of the described first crystal grain identification symbol that continues so that a Serial Peripheral Interface (SPI) instruction set can be responded by described first Serial Peripheral Interface (SPI) flash memory crystal grain, and according to the described crystal grain selection instruction of the described first crystal grain identification symbol that do not continue so that can only respond a universal command subset of described Serial Peripheral Interface (SPI) instruction set by described first Serial Peripheral Interface (SPI) flash memory crystal grain; And
Described second Serial Peripheral Interface (SPI) flash memory crystal grain comprises one second order and steering logic, in order to according to the described crystal grain selection instruction of the described second crystal grain identification symbol that continues so that described Serial Peripheral Interface (SPI) instruction set can be responded by described second Serial Peripheral Interface (SPI) flash memory crystal grain, and according to the described crystal grain selection instruction of the above-mentioned second crystal grain identification symbol that do not continue so that can only respond the described universal command subset of described Serial Peripheral Interface (SPI) instruction set by described second Serial Peripheral Interface (SPI) flash memory crystal grain.
3. flash memory device as claimed in claim 2, it is characterized in that, this flash memory device also comprises:
Be positioned at the multiple first working storage positions on described first Serial Peripheral Interface (SPI) flash memory crystal grain, in order to store described first crystal grain identification symbol, described first order is coupled to described first working storage position with steering logic; And
Be positioned at the multiple second working storage positions on described second Serial Peripheral Interface (SPI) flash memory crystal grain, in order to store described second crystal grain identification symbol, described second order is coupled to described second working storage position with steering logic.
4. flash memory device as claimed in claim 1, is characterized in that,
Described first Serial Peripheral Interface (SPI) pin group, comprises one first wafer and selects pin, one first sequential pin and four the first configurable pins;
Described second Serial Peripheral Interface (SPI) pin group, comprises one second wafer and selects pin, one second sequential pin and four the second configurable pins; And
Described Serial Peripheral Interface (SPI) encapsulation pin group, comprises the wafer being coupled to described first wafer selection pin and described second wafer selection pin and selects pin, is coupled to one the 3rd sequential pin of described first sequential pin and described second sequential pin, is coupled to four the 3rd configurable pins of described four the first configurable pins and described four the second configurable pins.
5. flash memory device as claimed in claim 1, is characterized in that,
Described first Serial Peripheral Interface (SPI) flash memory crystal grain also comprises at least one first crystal grain identification symbol pin, and described first crystal grain identification symbol pin accords with to set up described first crystal grain identification at least in part with being coupled to; And
Described second Serial Peripheral Interface (SPI) flash memory crystal grain also comprises at least one second crystal grain identification symbol pin, and described second crystal grain identification symbol pin is coupled to power supply to set up described second crystal grain identification symbol at least in part.
6. flash memory device as claimed in claim 3, is characterized in that,
Described first Serial Peripheral Interface (SPI) flash memory crystal grain also comprises at least one first transmission gate and at least one first crystal grain identification symbol pin, and described first crystal grain identification symbol pin is coupled at least one of described first working storage position to set up described first crystal grain identification symbol at least in part by described first transmission gate; And
Described second Serial Peripheral Interface (SPI) flash memory crystal grain also comprises at least one second transmission gate and at least one second crystal grain identification symbol pin, and described second crystal grain identification symbol pin is coupled at least one of described second working storage position to set up described second crystal grain identification symbol at least in part by described second transmission gate.
7. flash memory device as claimed in claim 6, is characterized in that,
Described first crystal grain identification symbol pin is coupled to ground; And
Described second crystal grain identification symbol pin is coupled to power supply.
8. flash memory device as claimed in claim 1, it is characterized in that, this flash memory device also comprises:
One the 3rd Serial Peripheral Interface (SPI) flash memory crystal grain, has one the 3rd crystal grain identification symbol and one the 3rd Serial Peripheral Interface (SPI) pin group; And
One the 4th Serial Peripheral Interface (SPI) flash memory crystal grain, has one the 4th crystal grain identification symbol and one the 4th Serial Peripheral Interface (SPI) pin group;
Wherein said encapsulation also has the described 3rd Serial Peripheral Interface (SPI) flash memory crystal grain and described 4th Serial Peripheral Interface (SPI) flash memory crystal grain that arrange with described stack arrangement.
9. flash memory device as claimed in claim 8, is characterized in that,
Described first Serial Peripheral Interface (SPI) flash memory crystal grain also has two crystal grain identification symbol pins, in order to accord with to set up described first crystal grain identification with being coupled to;
Described second Serial Peripheral Interface (SPI) flash memory crystal grain also has two crystal grain identifications symbol pins, in order to be coupled to ground and power supply respectively to set up described second crystal grain identification symbol;
Described 3rd Serial Peripheral Interface (SPI) flash memory crystal grain also has two crystal grain identifications symbol pins, in order to be coupled to power supply and ground respectively to set up described 3rd crystal grain identification symbol; And
Described 4th Serial Peripheral Interface (SPI) flash memory crystal grain also has two crystal grain identification symbol pins, in order to be coupled to power supply to set up described 4th crystal grain identification symbol.
10. flash memory device as claimed in claim 1, is characterized in that,
Described first Serial Peripheral Interface (SPI) flash memory crystal grain comprises SPI-NOR flash memory; And
Described second Serial Peripheral Interface (SPI) flash memory crystal grain comprises SPI-NOR flash memory.
11. flash memory devices as claimed in claim 1, is characterized in that,
Described first Serial Peripheral Interface (SPI) flash memory crystal grain comprises SPI-NAND flash memory; And
Described second Serial Peripheral Interface (SPI) flash memory crystal grain comprises SPI-NAND flash memory.
12. flash memory devices as claimed in claim 1, is characterized in that,
Described first Serial Peripheral Interface (SPI) flash memory crystal grain comprises SPI-NOR flash memory; And
Described second Serial Peripheral Interface (SPI) flash memory crystal grain comprises SPI-NAND flash memory.
13. 1 kinds of methods performing synchronous operation, be applicable to a Serial Peripheral Interface (SPI) flash memory device, described Serial Peripheral Interface (SPI) flash memory device has the Serial Peripheral Interface (SPI) encapsulation pin group comprising a wafer selection pin, and it is characterized in that, the method for this execution synchronous operation comprises:
Described wafer in described Serial Peripheral Interface (SPI) flash memory device selects pin to receive one first wafer selection active signal, and wherein said Serial Peripheral Interface (SPI) flash memory device comprises:
One first Serial Peripheral Interface (SPI) flash memory crystal grain, has one first crystal grain identification symbol and one first Serial Peripheral Interface (SPI) pin group; And
One second Serial Peripheral Interface (SPI) flash memory crystal grain, has one second crystal grain identification symbol and one second Serial Peripheral Interface (SPI) pin group;
Described first Serial Peripheral Interface (SPI) flash memory crystal grain and described second Serial Peripheral Interface (SPI) flash memory crystal grain stacking, and described first Serial Peripheral Interface (SPI) pin group and described second Serial Peripheral Interface (SPI) pin group coupled in parallel are to described Serial Peripheral Interface (SPI) encapsulation pin group; And
Described first wafer selects that active signal is parallel is provided to described first Serial Peripheral Interface (SPI) flash memory crystal grain and described second Serial Peripheral Interface (SPI) flash memory crystal grain;
In conjunction with the step receiving described first wafer selection active signal, one first crystal grain selection instruction is performed on described first Serial Peripheral Interface (SPI) flash memory crystal grain and described second Serial Peripheral Interface (SPI) flash memory crystal grain, so that a Serial Peripheral Interface (SPI) instruction set can be responded by described first Serial Peripheral Interface (SPI) flash memory crystal grain, and the second Serial Peripheral Interface (SPI) flash memory crystal grain only responds a universal command subset of described Serial Peripheral Interface (SPI) instruction set described in activation, wherein said first crystal grain selection instruction specifies one first crystal grain identification to accord with to described serial circumference flash memory device, and described universal command subset comprises crystal grain selection instruction,
Described wafer in described Serial Peripheral Interface (SPI) flash memory device selects pin to receive one first wafer selection stop signal, to stop the execution of described first crystal grain selection instruction on described first Serial Peripheral Interface (SPI) flash memory crystal grain and described second Serial Peripheral Interface (SPI) flash memory crystal grain;
When described first Serial Peripheral Interface (SPI) flash memory crystal grain is enabled the described Serial Peripheral Interface (SPI) instruction set of response, select pin to receive one second wafer in the described wafer of described Serial Peripheral Interface (SPI) flash memory device and select active signal, described second wafer selects that active signal is parallel is provided to described first Serial Peripheral Interface (SPI) flash memory crystal grain and described second Serial Peripheral Interface (SPI) flash memory crystal grain;
In conjunction with the step receiving described second wafer selection active signal, on described first Serial Peripheral Interface (SPI) flash memory crystal grain, perform one first Serial Peripheral Interface (SPI) instruction of a non-universal command, described first Serial Peripheral Interface (SPI) instruction causes the execution of an inner self-timing operation;
Described wafer in described Serial Peripheral Interface (SPI) flash memory device selects pin to receive one second wafer selection stop signal, to stop described first Serial Peripheral Interface (SPI) instruction on described first Serial Peripheral Interface (SPI) flash memory crystal grain, but do not stop described inner self-timing operation;
Select pin to receive a wafer in the described wafer of described Serial Peripheral Interface (SPI) flash memory device and select active signal, described wafer selects that active signal is parallel is provided to described first Serial Peripheral Interface (SPI) flash memory crystal grain and described second Serial Peripheral Interface (SPI) flash memory crystal grain;
In conjunction with the step receiving described wafer selection active signal, one second crystal grain selection instruction is performed on described first Serial Peripheral Interface (SPI) flash memory crystal grain and described second Serial Peripheral Interface (SPI) flash memory crystal grain, so that described Serial Peripheral Interface (SPI) instruction set can be responded by described second Serial Peripheral Interface (SPI) flash memory crystal grain, and the first Serial Peripheral Interface (SPI) flash memory crystal grain only responds described universal command subset described in activation, wherein said second crystal grain selection instruction specifies one second crystal grain identification to accord with to described serial circumference flash memory device;
Described wafer in described Serial Peripheral Interface (SPI) flash memory device selects pin to receive a wafer selection stop signal, to stop the execution of described second crystal grain selection instruction on described first Serial Peripheral Interface (SPI) flash memory crystal grain and described second Serial Peripheral Interface (SPI) flash memory crystal grain;
When described second Serial Peripheral Interface (SPI) flash memory crystal grain is enabled the described Serial Peripheral Interface (SPI) instruction set of response, select pin to receive one the 4th wafer in the described wafer of described Serial Peripheral Interface (SPI) flash memory device and select active signal, described 4th wafer selects that active signal is parallel is provided to described first Serial Peripheral Interface (SPI) flash memory crystal grain and described second Serial Peripheral Interface (SPI) flash memory crystal grain;
In conjunction with the step receiving described 4th wafer selection active signal, on described second Serial Peripheral Interface (SPI) flash memory crystal grain, perform one second Serial Peripheral Interface (SPI) instruction, and be synchronized with on described first Serial Peripheral Interface (SPI) flash memory crystal grain and perform described inner self-timing operation; And
Described wafer in described Serial Peripheral Interface (SPI) flash memory device selects pin to receive one the 4th wafer selection stop signal, to stop described second Serial Peripheral Interface (SPI) instruction.
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