CN105302755B - A kind of PCIE boards and its monitoring method with monitoring function - Google Patents
A kind of PCIE boards and its monitoring method with monitoring function Download PDFInfo
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- CN105302755B CN105302755B CN201410302597.5A CN201410302597A CN105302755B CN 105302755 B CN105302755 B CN 105302755B CN 201410302597 A CN201410302597 A CN 201410302597A CN 105302755 B CN105302755 B CN 105302755B
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Abstract
The present invention relates to a kind of design and its monitoring method of PCIE boards, the board is connected by connector with mainboard, and the mainboard is equipped with the platform courses exchanger and baseboard management controller being connected with each other；The board includes the multiple PCIE slots being arranged on the board or equipment, two groups of row's needles and iic bus interface IO expensive chips；Needle is arranged described in one of which realizes the identification of BIOS automated intelligents and adaptive different PCIE boards by being connected from the platform courses exchanger；Needle is arranged described in another group realizes that BMC automated intelligents identify different PCIE boards by being connected from the baseboard management controller.This method includes the consistency of the consistency of PCIE device quantity and PCIE bus bit wides by data of both comparative analysis, realizes failure monitoring and warning function.Technical scheme of the present invention is simple, practical, can realize the monitoring function more flexible to board and more accurate fault location ability.
Description
Technical field：
The present invention relates to a kind of PCIE boards, are more particularly to a kind of PCIE boards and its monitoring side with monitoring function
Method.
Background technology：
PCI (PeripheralComponentInterconnect, Peripheral Component Interconnect) Express is advocated by Intel
The processor system bus of exploitation is a kind of serial interlinkage technology, is received and is become by PCISIG (PCI special interest groups) at present
The successor of PCI, PCI-X (PCIextended, PCI extend), target are complete substitution PCI and PCI-X.With
The publication of PCIExpress (abbreviation PCIE) specification, more and more producers start the chip released based on PCIE specifications and are based on
The exchanger of PCIE.The exchanger of PCIE can connect many equipment in a system, and the communication based on PCIE exchangers is set
Standby (such as router, interchanger, gateway) also becomes a kind of selection.
PCI Express Bus (PCIE) occupy more and more important position in the development of current IT technologies.Now absolutely
Most of CPU is integrated in PCIE bus inside CPU, and the maximum PCIE Lane numbers supported is very heavy as one
The technical indicator wanted.The monitoring technology of PCIE boards is too simple at present, only merely BIOS and OS itself is relied on to monitor
Information alert lacks flexibility, intuitive, accuracy, is short of more accurate fault location ability.Present invention design is a set of more
The method for effectively monitoring and managing PCIE boards, to overcome current defect or deficiency.
Invention content：
The object of the present invention is to provide a kind of PCIE boards and its monitoring method with monitoring function, technologies of the invention
Scheme is simple, practical, can realize the monitoring function more flexible to board and more accurate fault location ability.
To achieve the above object, the present invention uses following technical scheme：A kind of PCIE boards with monitoring function, it is described
Its PCIE Lane are connected by board by connector with mainboard, and the mainboard is equipped with the platform courses exchanger being connected with each other
And baseboard management controller；The board includes at least one PCIE slots being arranged on board or PCIE device, two groups of row's needles
With the iic bus interface IO expensive chips being connect with the PCIE slots or PCIE device；Described in one of which arrange needle by with
The identification of BIOS automated intelligents and adaptive different PCIE boards are realized in the platform courses exchanger connection；It is arranged described in another group
Needle realizes that BMC automated intelligents identify different PCIE boards by being connected from the baseboard management controller.
A kind of a kind of PCIE boards with monitoring function as described in claim 1 provided by the invention, it is described another
Group row's needle is connect by iic bus interface IO expensive chips and connector with the baseboard management controller of the mainboard.
A kind of PCIE boards with monitoring function provided by the invention, the row's needle being connect with the platform courses exchanger
Group includes at least one row's needle；Row's needle includes being connect with the accessory power supply being arranged on the board by pull-up resistor
Stitch, the stitch being connected to the bandwidth signal of PCIE boards on the GPIO stitch of the platform courses exchanger and with setting exist
The stitch of ground connection on the board.
Another preferred a kind of PCIE boards with monitoring function provided by the invention, with the baseboard management controller
Row's needle group of connection includes at least one row's needle；Row's needle includes by pull-up resistor and the auxiliary being arranged on the board
The ID of PCIE boards is signally attached on the IO stitch of the iic bus interface IO expensive chips by the stitch of power supply connection
Stitch and the stitch being connect with the ground being arranged on the board.
Another preferred a kind of PCIE boards with monitoring function provided by the invention, by the PCIE slots or PCIE
The present signals PCIE_SLOTx_PRSNT_N of equipment is introduced on the IO stitch of the iic bus interface IO expensive chips,
State in place for detecting each slot or equipment.
Another preferred a kind of PCIE boards with monitoring function provided by the invention, the mainboard include being put down with described
Platform controls the CPU of exchanger connection, and the CPU is connect with the PCIE slots or PCIE device, the BIOS letters that the CPU is collected
Breath passes to the baseboard management controller by DMI2 and LPC links.
Another preferred a kind of PCIE boards with monitoring function provided by the invention, the baseboard management controller are logical
Ethernet interface is crossed to connect with the terminal computer；The information of monitoring is constantly transferred to terminal electricity by the baseboard management controller
Show on brain and with boundary's user oriented, realizes the function of intelligent monitoring PCIE boards.
Another preferred a kind of PCIE boards with monitoring function provided by the invention, the number n1 of row's needle and institute
The relationship stated between the combination type m1 of PCIE buses is：2(n1-1)<=m1<=2n1。
Another preferred a kind of PCIE boards with monitoring function provided by the invention, the number n2 of row's needle and institute
The relationship stated between PCIE board numbers m2 is：2(n2-1)<=m2<=2n2。
A kind of method of PCIE boards with monitoring function comprising above-mentioned technology contents provided by the invention, the side
Method includes the following steps：
1) board ID databases are established to PCIE boards in the program data base of the Management Controller；
2) PCIE combination code WD databases are established to the distribution combination of PCIE boards in the program data base of BIOS；
3) row's needle of the PCIE boards is configured；And PCIE boards are inserted into mainboard；
4) when being not keyed up, the mainboard makes the baseboard management controller work normally by accessory power supply；
5) baseboard management controller reads the I/O interface deposit of iic bus interface IO expensive chips by SMB buses
Device, the baseboard management controller recall corresponding PCIE boards according to the ID number read in the program data base of oneself
PCIE Lane forms of distribution and PCIE slots or PCIE device quantity information；
6) the mainboard booting, the platform courses exchanger read row by signal wire PCIE_LINK_WIDTH_IDx
The level of needle determines the required PCIE Lane forms of distribution of PCIE boards, completes BIOS and carries out division and phase to PCIELane
The initialization answered；
7) after the completion of the mainboard booting, the baseboard management controller is read by lpc bus in the mainboard BIOS
The quantity of PCIE device and PCIE bus bit wides in POST information；
8) baseboard management controller obtains relevant monitoring and analysis data by comparative analysis data；
9) terminal computer reads the information of the baseboard management controller monitoring by Ethernet, with friendly boundary
User oriented shows, and realizes intelligent monitoring PCIE board functions.
Another preferred a kind of monitoring method of the PCIE boards with monitoring function provided by the invention, the ID data
Library includes the ID number of each PCIE board, PCIE Lane forms of distribution and PCIE slots or PCIE device quantity information；The WD numbers
Include No. WD, PCIE Lane forms of distribution of each PCIE distribution combinations according to library.
Another preferred a kind of monitoring method of the PCIE boards with monitoring function provided by the invention, the step 5)
In by reading the level of each PCIE_CARD_IDx signals, be combined into the ID number of PCIE boards and by each signal in place
The level of PCIE_SLOTx_PRSNT_N determines the information in place of corresponding PCIE plug-in cards or PCIE device.
Another preferred a kind of monitoring method of the PCIE boards with monitoring function provided by the invention, the step 8)
Middle comparative analysis data include whether the quantity of PCIE device consistent consistent with the bit wide of PCIE buses；Wherein, the base
The PCIE device quantity information that board management controller is obtained from the BIOS POST information is believed in place with from the PCIE boards
Number PCIE device quantity information learnt is compared, and is shown to occur PCIE plug-in cards if inconsistent and is not seated or PCIE device
Initialization mistake or PCIE device damage fault condition；
PCIE device bus bit wide information that the baseboard management controller is obtained from the BIOSPOST information with from
The PCIE device bus bit wide information that the PCIE boards ID symbol lookups are learnt is compared, and shows occur if inconsistent
PCIE bit wides row needle setting mistake or PCIE plug-in cards are not seated or PCIE device initializes mistake or PCIE device damage failure feelings
Condition.
With immediate prior art ratio, the present invention, which provides technical solution, has following excellent effect
1, the method for salary distribution that can intelligently report to BIOS PCIE buses in the present invention according to different PCIE boards, makes
BIOS can successfully initialize PCIE boards, therefore the diversification of the PCIE boards on same mainboard may be implemented；
2, the present invention can uniquely determine PCIE board ID numbers, therefore BMC (Baseboard Management
Controller) it is able to know that the configuring condition of PCIE boards；
3, BMC of the present invention, which can be realized using lpc bus from BIOS, reads PCIE board information；BMC can also pass through SMB
(System Management Bus) bus reads the information of PCIE boards；The information obtained by two aspect of comparison, Ke Yishi
The monitoring management of existing PCIE boards, the function of fault alarm；
4, board of the invention has the characteristics that flexibility, intuitive, accuracy, has more accurate fault location energy
Power.
Description of the drawings
Fig. 1 is the board structure schematic diagram of the present invention；
Wherein, 1- mainboards, 2-PCIE boards, 3- terminal computers, 4- connectors；
101-CPU, 102- memory, 103-PCH, 104-BMC；
201-PCIE slots or PCIE device, 202-IIC bus interface IO expensive chips, 203- row's needles, 204- pull-up resistors,
205-3.3V accessory power supplys, 206-.
Specific implementation mode
With reference to embodiment, the invention will be described in further detail.
Embodiment 1：
As shown in Figure 1, PCIE buses are connected by the invention PCIE boards of this example by connector 4 with mainboard 1, the mainboard
1 is equipped with the platform courses exchanger PCH103 being connected with each other and baseboard management controller BMC104；The PCIE boards 2 include setting
Set 201, two groups of row's needles 203 of at least one PCIE slots or PCIE device on the board and with the PCIE slots or PCIE device
201 and one of which row needle 203 connect iic bus interface IO expensive chips 202；Described in one of which arrange needle 203 by with
The platform courses exchanger connection identifies with realizing BIOS automated intelligents and adaptive different PCIE boards 2；Another group of institute
The row's of stating needle 203 identifies different PCIE boards 2 with realizing BMC automated intelligents by being connected from the baseboard management controller.Institute
State baseboard management controller of another group of row's needle by iic bus interface IO expensive chips 202 and connector 4 and the mainboard 1
Connection.
The distribution and identification of PCIE Lane
PCIE buses have very flexible dividing mode, the classified types that can specifically support to depend on corresponding chip.
The present embodiment illustrates technical scheme of the present invention using Intel Haswell-EP CPU101, but is not limited solely to this CPU.
Haswell-EP CPU are total 40lane PCIE3.0 signals, possesses 3 PCIE interfaces.According to the rule of Haswell-EP CPU
Model, each PORT mouthfuls can be divided into such as the combination in table 1.PORT1 and PORT2 can have 4 kinds of combinations, PORT3 that can have 2 kinds
Combination can also have 32 kinds of PCIE Lane combinations so sharing 32 (4*4*2) kind combinations.
For the flexibility for making full use of PCIE buses to divide, mainboard 1 of the invention is by connector 4 Haswell-
PCIE lane signals all EP CPU101 are all introduced on PCIE boards 2, can be realized on same mainboard 1 so more
Up to 32 kinds of PCIE Lane combinations, the demand of different application occasion disclosure satisfy that.As shown in Figure 1, Haswell-EP
CPU101 is signally attached to by PCIEx40 on multiple PCIE slots or PCIE device 201.If applied for GPU, PCIE
Bus can be designed to 2 PCIE x16 and 1 PCIE x8.If it is slotting that some occasions do not require PCIE band merits to only require
Enter more PCIE devices, then PCIE buses can be designed to 10 PCIE x4.
The method of salary distribution of table 1PCIE x40bus
The connection structure of the above mainboard 1 and PCIE boards 2 ensure that system can possess changeable multiduty PCIE boards 2
Design, but also need to solve the problems, such as that different PCIE Lane combinations smoothly can be identified and initialized by BIOS.
A unique binary code, referred to as PCIE combinations code WD, solidification are compiled to each PCIE combination
On each PCIE boards 2, before BIOS initialization PCIE bus, WD is read by PCH103 first, then according to reading
WD the PCIE Lane of CPU101 reasonably divide and initialize, realize BIOS can identify to automated intelligent and from
Adapt to different PCIE boards 2.WD codes have several several row's needles 203, each binary digits of WD is just used to correspond to row's needle
203.On PCIE boards 2, each needle piece signal wire of extraction of arranging is connected to mainboard by connector 4 for these row's needle designs
On the GPIO feet of PCH103.And it arranges the signal wire that needle 203 can draw it and is set as high level or low level.According to
The value of WD every, setting respective row needle 203 is high level or low level, is achieved that WD is solidificated on PCIE boards 2.So
PCH103 can just can recognize that WD by reading the low and high level of row's needle on PCIE boards 2.
Row's needle 203 that multiple 3 needles are designed on PCIE boards 2, it is 4.7 thousand to arrange the 1st stitch of needle by a resistance value
The pull-up resistor 204 of ohm is pulled upward to accessory power supply 3.3V_AUX205, and the signal of the 2nd stitch is set as PCIE bandwidth signals
(PCIE_LINK_WIDTH_ID1 ..., PCIE_LINK_WIDTH_IDn) is connected on the GPIO stitch of Intel PCH103, the
3 stitch pull down to ground 206, that is, pull down to zero level.It, can be PCIE when jump cap is mounted on the 1st stitch and the 2nd stitch
Bandwidth signal is drawn high, and when jump cap is mounted on the 2nd stitch and the 3rd stitch, PCIE bandwidth signals can be dragged down.Assuming that PCIE
The combination of bus has m1 kinds, then needs n1 row's needle, and m1 and n1 need satisfaction 2(n1-1)<=m1<=2n1.For
For Haswell-EPCPU101, at least 32 kinds of PCIE combinations, so at least needing to be distinguished with 5 row's needles 203.Profit
Each PCIE bandwidth signals are drawn high or dragged down with this 5 row's needles 203, are realized to each combination side PCIE Lane
Formula carries out unique binary coding, this coding is known as PCIE combination codes WD.BIOS accordingly WD can uniquely distinguish and
Determine the PCIE methods of salary distribution of each PCIE board 2, as shown in table 2.Certainly in the design of actual system, these combination sides
Formula can not possibly be used all, it is possible to the usage quantity of the row's of reduction needle 203.After mainboard 1 is switched on, PCH103 passes through signal
Line PCIE_LINK_WIDTH_IDx (x=1~n1) checks the level of row's needle 203, to make BIOS learn needed for PCIE boards 2
PCIE bus assignment modes, then to PCIE buses carry out accordingly divide and initialize.
The bandwidth signal code (WD) of table 2PCIE boards
The design and identification of PCIE boards ID
In order to preferably monitor PCIE boards 2, need to assign a unique binary system to each PCIE boards 2
Identifier, referred to as PCIE boards ID.PCIE boards ID is solidificated on each PCIE boards 2, and BMC104 is by means of SMB Bus
(System Management Bus) reads each PCIE boards ID, then according to the ID of reading in BMC104 program data bases
In transfer the relevant information of corresponding board, realize that BMC104 can identify to automated intelligent different PCIE boards 2.ID codes have
Several just use several row's needles 203, each binary digits of ID to correspond to row's needle 203.These row's designs of needle 203 are in PCIE boards
On 2, each needle 203 of arranging draws a signal wire connection iic bus interface IO expensive chip 202.And row's needle 203 can be
Its signal wire drawn is set as high level or low level.According to every value of ID, setting respective row needle 203 is high level
Or low level, it is achieved that ID is solidificated on PCIE boards 2.IO expensive chips pass through connector 4 and BMC104 using SMB buses
It is connected.So the low and high level that BMC104 can read row's needle 203 on PCIE boards 2 by the IO expensive chips can be known
ID is not gone out.
Thus in PCIE boards 2, row's needle 203 of multiple 3 needles is designed, the 1st stitch of row's needle 203 passes through one
Resistance value is that 4.7 kilohms of pull-up resistor 204 is pulled upward to accessory power supply 3.3V_AUX205, and the signal of the 2nd stitch is set as
PCIE board ID signals (PCIE_CARD_ID1 ..., PCIE_CARD_IDn) are connected to an iic bus interface IO expensive chip
On 202 IO stitch, the 3rd stitch pulls down to ground 206, that is, pulls down to zero level.When jump cap is mounted on the 1st stitch and the 2nd
When a stitch, PCIE board ID signals can be drawn high, it, can be PCIE plates when jump cap is mounted on the 2nd stitch and the 3rd stitch
Card ID signals drag down.Assuming that PCIE boards there are m2, then n2 row's needle is needed, and m2 and 2n need satisfaction 2(n2-1)<=m2<=
2n2.Each PCIE boards ID signals are drawn high or dragged down using these row's needles 203, are united for each PCIE boards 2
One number, identifies a unique binary system ID number, and then BMC104 can uniquely be distinguished according to ID number and be determined each
PCIE boards 2.It should be noted that the method for salary distribution of each PCIE bus is possible to correspond to a variety of PCIE boards 2 namely PCIE
The ID number of board 2 can uniquely determine every piece of PCIE board 2, rather than be determined according to each PCIE bus assignments mode.
The present signals PCIE_SLOTx_PRSNT_N of each PCIE slots or PCIE device 201 on PCIE boards 2
(x=1~n) is introduced on the IO stitch of iic bus interface IO expensive chips 202, the state in place for detecting each equipment.
In the presence of PCIE device, PCIE_SLOTx_PRSNT_N signal levels can be lower, and IO expensive chips can detect low level, in
It is to judge to be already inserted into PCIe card on PCIE slots, or there are PCIE devices, otherwise PCIE_SLOTx_PRSNT_N signals should
For high level.
Iic bus interface IO expensive chips 202 are connected by SMB buses with BMC104.The BMC104 passes through SMB buses
The information for reading PCIE boards id information and PCIE device that IO expensive chips detect, to the prison for entire PCIE boards 2
Control provides basic data.
The design of mainboard monitoring system
Intel Haswell-EP CPU101 by DMI2 (Direct Media Interface Gen2) buses with
PCH103 connections, PCH103 are connect by LPC (Low Pin Count Bus) bus with BMC104.What the CPU101 was collected
BIOS information passes to BMC104 by DMI2 and LPC links.
The BMC104 is connected by the Ethernet interface of oneself with terminal computer 3, the letter that BMC chip can be monitored
Breath is constantly transferred on terminal computer 3, and is showed with friendly boundary's user oriented, realizes the function of intelligent monitoring PCIE boards 2.
The BMC chip is worked using accessory power supply, i.e., when mainboard 1 is not keyed up but has accessory power supply, BMC104 can be with
Normal work.
The monitoring of PCIE board information
The monitoring method of PCIE board information is as follows：
1) board ID databases are established to each PCIE board 2 in the program data base of BMC104, includes at least each
The information such as ID number, PCIE Lane forms of distribution, PCIE slots or the PCIE device quantity 201 of PCIE boards.
2) in the program data base of BIOS PCIE combinations code W is established to each PCIE distribution combinations) database,
Including at least No. WD, PCIE Lane forms of distribution of each PCIE distribution combinations.
3) according to 2 actual design conditions of PCIE boards, ID rows needle, the WD row's needles of each PCIE board 2 are carried out correct
Setting.It is inserted into mainboard 1.
4) when being not keyed up, the mainboard 1 makes BMC104 work normally by accessory power supply.
5) BMC104 reads the I/O interface register of iic bus interface IO expensive chips 202 by SMB buses, on the one hand
The level that can learn each PCIE_CARD_IDx signals, is then combined into the ID number of PCIE boards, on the other hand can learn
The level of each in place signal PCIE_SLOTx_PRSNT_N, it is possible thereby to know corresponding PCIE plug-in cards or PCIE device
Position information.BMC104 recalls the PCIE of corresponding PCIE boards 2 according to the ID number read in the program data base of oneself
The information such as 201 quantity of Lane forms of distribution, PCIE slots or PCIE device.
6) mainboard 1 is switched on, and PCH103 reads the level of row's needle 203 by signal wire PCIE_LINK_WIDTH_IDx first,
To learn this 2 required PCIELane forms of distribution of PCIE boards.BIOS then accordingly to PCIE buses carry out divide and
Corresponding initialization.
7) after the completion of mainboard 1 is switched on, BMC104 can read mainboard BIOS POST (Power On by lpc bus
Self Test, power-on self-test) information, these information include the quantity of PCIE device, PCIE bus bit wides etc..
8) data of both BMC104 comparative analyses obtain relevant monitoring and analysis data.
The comparison of one side is whether the quantity of PCIE device is consistent.BMC104 obtain from BIOS POST information
PCIE device quantity information (i.e. the 7th step) and the PCIE device quantity information the (the i.e. the 5th learnt from 2 signal in place of PCIE boards
Step) compared, show to occur if inconsistent PCIE plug-in cards be not seated or PCIE device initialization mistake or
The fault conditions such as PCIE device damage.
The comparison of other side is whether the bit wide of PCIE buses is consistent.BMC104 obtain from BIOS POST information
The PCIE device bus bit wide gone out information (i.e. the 7th step) and the PCIE device bus bit wide learnt from PCIE board ID symbol lookups
Information (i.e. the 5th step) is compared, and shows that PCIE bit wides (WD) row needle setting mistake or PCIE occur inserts if inconsistent
Card is not seated or the fault conditions such as PCIE device initialization mistake or PCIE device damage.
9) terminal computer 3 reads the information (i.e. the 8th step information) of BMC104 monitoring by Ethernet
Showed with friendly boundary's user oriented, realizes intelligent monitoring PCIE board functions.
Finally it should be noted that：The above embodiments are merely illustrative of the technical scheme of the present invention and are not intended to be limiting thereof, institute
The those of ordinary skill in category field although with reference to above-described embodiment should manage still can to the specific implementation mode of the present invention into
Row modification either equivalent replacement these without departing from any modification of spirit and scope of the invention or equivalent replacement, applying
Within the claims of the pending present invention.
Claims (12)
1. a kind of monitoring method of the PCIE boards with monitoring function, the board is connected by connector with mainboard, described
Mainboard is equipped with the platform courses exchanger and baseboard management controller being connected with each other；The board includes being arranged on board extremely
A few PCIE slot or PCIE device, two groups of row's needles and the iic bus interface IO that is connect with the PCIE slots or PCIE device are opened up
Open up chip；Described in one of which arrange needle by connect with the platform courses exchanger realize BIOS automated intelligents identify and it is adaptive
Answer different PCIE boards；Needle is arranged described in another group realizes baseboard management controller by being connect with the baseboard management controller
Automated intelligent identifies different PCIE boards；
It is characterized in that：It the described method comprises the following steps：
1) board ID databases are established to PCIE boards in the program data base of the baseboard management controller；
2) PCIE combination code WD databases are established to the distribution combination of PCIE boards in the program data base of BIOS；
3) two groups of row's needles of the PCIE boards are configured；And PCIE boards are inserted into mainboard；
4) when being not keyed up, the mainboard makes the baseboard management controller work normally by accessory power supply；
5) baseboard management controller reads the I/O interface register of iic bus interface IO expensive chips, institute by SMB buses
State the PCIE that baseboard management controller recalls corresponding PCIE boards according to the ID number read in the program data base of oneself
Lane forms of distribution and PCIE slots or PCIE device quantity information；
6) the mainboard booting, the platform courses exchanger read row's needle by signal wire PCIE_LINK_WIDTH_IDx
Level, determines the required PCIE Lane forms of distribution of PCIE boards, completes BIOS and to PCIE Lane divide and corresponding
Initialization；
7) after the completion of the mainboard booting, the baseboard management controller is read by lpc bus in the mainboard BIOS POST
The quantity of PCIE device and PCIE bus bit wides in information；
8) baseboard management controller obtains relevant monitoring and analysis data by comparative analysis data；
9) terminal computer reads the information of the baseboard management controller monitoring by Ethernet, with friendly boundary's user oriented
Show, realizes intelligent monitoring PCIE board functions.
2. a kind of monitoring method of the PCIE boards with monitoring function as described in claim 1, it is characterised in that：It is described another
One group of row's needle is connect by iic bus interface IO expensive chips and connector with the baseboard management controller of the mainboard.
3. a kind of monitoring method of the PCIE boards with monitoring function as described in claim 1, it is characterised in that：With it is described
Row's needle group of platform courses exchanger connection includes at least one row's needle；Row's needle includes with setting by pull-up resistor in institute
It states the stitch of the connection of the accessory power supply on board, the bandwidth signal of PCIE boards is connected to the platform courses exchanger
Stitch on GPIO stitch and the stitch being connect with the ground being arranged on the board.
4. a kind of monitoring method of the PCIE boards with monitoring function as claimed in claim 2, it is characterised in that：With it is described
Row's needle group of baseboard management controller connection includes at least one row's needle；Row's needle includes with setting by pull-up resistor in institute
It states the stitch of the connection of the accessory power supply on board, the ID of PCIE boards is signally attached to the iic bus interface IO expansions core
Stitch on the IO stitch of piece and the stitch being connect with the ground being arranged on the board.
5. a kind of monitoring method of the PCIE boards with monitoring function as claimed in claim 2, it is characterised in that：It will be described
PCIE slots or the present signals PCIE_SLOTx_PRSNT_N of PCIE device are introduced into the iic bus interface IO and expand
On the IO stitch of chip, the state in place for detecting each slot or equipment.
6. a kind of monitoring method of the PCIE boards with monitoring function as claimed in claim 5, it is characterised in that：The master
Plate includes the CPU being connect with the platform courses exchanger, the CPU with it is described
PCIE slots or PCIE device connection, the BIOS information that the CPU is collected pass to the base by DMI2 and LPC links
Board management controller.
7. a kind of monitoring method of the PCIE boards with monitoring function as described in claim 1, it is characterised in that：The base
Board management controller is connect by Ethernet interface with terminal computer；The baseboard management controller passes the information of monitoring in real time
It is defeated to show on terminal computer and with boundary's user oriented, realize the function of intelligent monitoring PCIE boards.
8. a kind of monitoring method of the PCIE boards with monitoring function as claimed in claim 3, it is characterised in that：The row
Relationship between the number n1 of needle and the combination type m1 of the PCIE buses is：2(n1-1)<=m1<=2n1。
9. a kind of monitoring method of the PCIE boards with monitoring function as claimed in claim 4, it is characterised in that：The row
Relationship between the number n2 of needle and the PCIE boards number m2 is：2(n2-1)<=m2<=2n2。
10. a kind of monitoring method of the PCIE boards with monitoring function as described in claim 1, it is characterised in that：It is described
ID databases include the ID number of each PCIE board, PCIE Lane forms of distribution and PCIE slots or PCIE device quantity information；Institute
State No. WD, the PCIE Lane forms of distribution that WD databases include each PCIE distribution combinations.
11. a kind of monitoring method of the PCIE boards with monitoring function as claimed in claim 10, it is characterised in that：It is described
By reading the level of each PCIE_CARD_IDx signals in step 5), be combined into PCIE boards ID number and by it is each
The level of position signal PCIE_SLOTx_PRSNT_N determines the information in place of corresponding PCIE plug-in cards or PCIE device.
12. a kind of monitoring method of the PCIE boards with monitoring function as claimed in claim 11, it is characterised in that：It is described
Comparative analysis data include whether the quantity of PCIE device consistent consistent with the bit wide of PCIE buses in step 8)；Wherein,
PCIE device quantity information that the baseboard management controller is obtained from the BIOS POST information with from the PCIE boards
The PCIE device quantity information that signal in place is learnt is compared, show to occur if inconsistent PCIE plug-in cards be not seated or
PCIE device initialization mistake or PCIE device damage fault condition；
The PCIE device bus bit wide information that the baseboard management controller is obtained from the BIOS POST information with from described
The PCIE device bus bit wide information that PCIE board ID symbol lookups are learnt is compared, and shows PCIE occur if inconsistent
Bit wide row needle setting mistake or PCIE plug-in cards are not seated or PCIE device initializes mistake or PCIE device damage fault condition.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410302597.5A CN105302755B (en) | 2014-06-27 | 2014-06-27 | A kind of PCIE boards and its monitoring method with monitoring function |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410302597.5A CN105302755B (en) | 2014-06-27 | 2014-06-27 | A kind of PCIE boards and its monitoring method with monitoring function |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105302755A CN105302755A (en) | 2016-02-03 |
| CN105302755B true CN105302755B (en) | 2018-08-14 |
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