CN105259843B

CN105259843B - A kind of outlet logic circuit of reactive-load compensation intelligent controlling device

Info

Publication number: CN105259843B
Application number: CN201510783748.8A
Authority: CN
Inventors: 王成友; 闫红华; 王俊杰
Original assignee: University of Jinan
Current assignee: University of Jinan
Priority date: 2015-11-13
Filing date: 2015-11-13
Publication date: 2017-04-05
Anticipated expiration: 2035-11-13
Also published as: CN105259843A

Abstract

The invention discloses a kind of outlet logic circuit of reactive-load compensation intelligent controlling device, including CPU, FPGA and reset chip, in the parallel bus access FPGA of CPU, the reset signal of reset chip accesses FPGA；Include decoding circuit, two d type flip flops and logic gates inside FPGA；Address bus in parallel bus and control signal access decoding circuit, generate two independent chip selection signals, by the data/address bus in chip selection signal and parallel bus can independent control each d type flip flop output；The output signal of two d type flip flops accesses logic gates, and the output of logic gates connects the output pin of FPGA, and then the on-off circuit outside driving；The reset signal of reset chip connects the control end of two d type flip flops.FPGA is introduced in the design of outlet logic circuit, can accomplish that internal circuit flexible programming, external terminal are flexibly exported, improve the motility of design, designed circuit has little a, low cost that accounts for plate suqare, strong antijamming capability, the characteristics of reliability is high.

Description

A kind of outlet logic circuit of reactive-load compensation intelligent controlling device

Technical field

The present invention relates to outlet logic field of circuit technology, more particularly to a kind of outlet of reactive-load compensation intelligent controlling device Logic circuit.

Background technology

In the electrical network of China, alternating current is sent from electromotor, through multistage defeated change distribution, finally reaches electrical equipment. Electrical equipment majority is the inductive loads such as motor, transformator, if no Measures of Reactive Compensation, substantial amounts of reactive power will Electrical equipment is flowed to from electromotor, idle flowing is just filled with from top to bottom, make it is defeated, become, with, electricity system loss increase, defeated Ability reduction, bad stability are sent, or even causes system crash.Current Measures of Reactive Compensation is mainly entered by switched capacitor Row compensation.In addition, there is the electromagnetic interference that cause such as switch switching in network system in a large number, also occur once in a while overvoltage, The temporary faults such as low-voltage, overcurrent.The presence of electromagnetic interference should not cause capacitor miscarrying and cut, in electrical network temporary fault situation Lower capacitor does not answer switching.

Outlet logic circuit is the nucleus module of reactive-load compensation intelligent controlling device.It carries out operational control by CPU, passes through The on-off circuits such as order, control relay are sent out after certain sequential or logic, and then controls the switching of capacitor.

Known by more than, the height of outlet logic circuit performance directly affects the reliability of capacitor actions, Jin Erying Ring the stable operation of network system.But current outlet logic circuit generally adopts special d type flip flop or latch chip to constitute, After the parallel bus write-once of CPU, directly control outlet output.This circuit has poor anti jamming capability, accounts for plate Area is big, costly, the shortcoming that confidentiality is poor.

The content of the invention

The purpose of the present invention is exactly to solve the above problems, there is provided a kind of outlet of reactive-load compensation intelligent controlling device is patrolled Circuit is collected, FPGA is introduced in the design of outlet logic circuit, can be accomplished that internal circuit flexible programming, external terminal are flexibly defeated Go out, improve the motility of design.

To achieve these goals, the present invention is adopted the following technical scheme that：

A kind of outlet logic circuit of reactive-load compensation intelligent controlling device, including CPU, FPGA and reset chip, the CPU Parallel bus access in FPGA, the reset signal of reset chip accesses FPGA；

The FPGA includes decoding circuit, and the parallel bus accesses decoding circuit, generates multiple independent chip selection signals； Each chip selection signal connects a d type flip flop respectively, and the output signal of d type flip flop accesses logic gates, the logic gates Output connect the output pin of FPGA, and then the on-off circuit outside driving.

The parallel bus includes data/address bus, address bus and control signal.

The digit of d type flip flop is identical with the width of data/address bus, and the d type flip flop includes two, respectively d type flip flop U1 With d type flip flop U2.

The address bus and control signal generate two independent chip selection signals, two chip selection signals by decoding circuit The D ends for meeting the CLK ends of d type flip flop U1 and d type flip flop U2, d type flip flop U1 and d type flip flop U2 respectively all connect data/address bus, D triggerings The outfan of device U1 and d type flip flop U2 exports Q1 and Q2 signals respectively.

Output of the input of the logic gates from two triggers, its logic isThe output of A ends is arrived FPGA pins, and then the on-off circuit outside driving.

The reset signal of reset chip connects the clear terminal of the set end of d type flip flop U1 and d type flip flop U2, and reset chip resets When export reset signal, it is ensured that d type flip flop exports stable signal, so that it is guaranteed that exporting stable in powered on moment FPGA pins State.

Beneficial effects of the present invention：

FPGA is introduced in the design of outlet logic circuit, can accomplish that internal circuit flexible programming, external terminal are flexibly defeated Go out, improve the motility of design.

FPGA internal processes are difficult to be decrypted, and corresponding printed board is difficult to be plagiarized, replicates, and improves the confidentiality of design And safety.

In the case where system requirements outlet is more, if using traditional design, many triggers or lock will be increased Storage chip simultaneously increases the area for taking printed board, and adopts FPGA design outlet logic circuit, and only one chip is completed enough, Greatly reduce cost.

Internally in circuit, the only output of two triggers outlet ability action under the opposite logic of regulation is improved The threshold of outlet action, so as to enhance capacity of resisting disturbance.

The reset signal of reset chip is introduced into the design of outlet logic circuit, in the case of electrification reset, at trigger In it is determined that state, it is to avoid the probability of upper electric misoperation, reliability is further increased.

Description of the drawings

Fig. 1 is the general structure schematic diagram of the present invention.

Fig. 2 is the physical circuit schematic diagram of the present invention.

Specific embodiment

The invention will be further described with embodiment below in conjunction with the accompanying drawings.

As shown in Figure 1, whole system is constituted by CPU, reset chip and FPGA.FPGA is using Mi crosemi companies The A3P125 of ProASIC3 series, as using non-volatile FLASH technologies, A3P125 has safety, low-power consumption, upper electricity at once The features such as.CPU using TI companies TMS320F28335, it possess parallel bus output ability, including 16 bit data bus, 19 bit address buses and control signal wire etc..TPS3705-33D of the reset chip using TI companies, the reset signal of output is low Level.The reset signal of the parallel bus of CPU, reset chip is connected to into FPGA, logic circuits of the FPGA inside is defeated Go out signal to FPGA pins, output is to on-off circuits such as external drive relays afterwards.

As shown in Figure 2, the address bus and control signal wire (chip selection signal CS, write signal WR) from CPU is through translating Code two independent pieces of circuit evolving select OUTCS1 and OUTCS2.In FPGA indoor designs two independent d type flip flop U1, U2, U1, U2 are the trigger of 16, are consistent with the data-bus width of CPU.The D ends of two of which trigger fetch certainly The CLK termination OUTCS2 of the CLK termination OUTCS1 of the data/address bus DB of CPU, U1, U2.Output Q1, Q2 of trigger U1 and U2 point Not Jie Ru gate circuit U3 two ends, the gate logic of gate circuit U3 is：By the pin of A outputs to FPGA.So lead to The rising edge of chip selection signal is crossed, the value of data/address bus write Q ends so as to change the value of A, and then outside relay can be exported to Device loop, controls the switching of capacitor.

General provision A is output as actuating of relay when " 0 ".If it is desired that A is output as " 0 ", Q1 outputs should be " 0 ", and Q2 is defeated Go out should be " 1 ", that is to say, that trigger U1, U2 should export the value of regulation and two values just must can make the actuating of relay on the contrary, The threshold of the actuating of relay compared with single trigger or latch circuit, is improve, the difficulty of the actuating of relay is increased, So as to enhance the capacity of resisting disturbance of circuit.

The reset signal of reset chip connects the reset terminal of the set end and U2 of U1.So, during reset chip reset, U1 Output Q1 be " 1 ", the output Q2 of U2 is " 0 ", then it is " 1 " to export A, it is ensured that the state that A outputs determine, and ensure it is outside after Electrical equipment is failure to actuate, so as to improve the reliability of circuit.

Although the above-mentioned accompanying drawing that combines is described to the specific embodiment of the present invention, not to present invention protection model The restriction enclosed, one of ordinary skill in the art should be understood that on the basis of technical scheme those skilled in the art are not The various modifications made by needing to pay creative work or deformation are still within protection scope of the present invention.

Claims

1. a kind of outlet logic circuit of reactive-load compensation intelligent controlling device, is characterized in that, including CPU, FPGA and reset chip, The parallel bus of the CPU is accessed in FPGA, and the reset signal of reset chip accesses FPGA；The FPGA includes decoding circuit, The parallel bus accesses decoding circuit, generates multiple independent chip selection signals；Each chip selection signal connects a D triggering respectively Device, the output signal of d type flip flop access logic gates, and the output of the logic gates connects an output pin of FPGA, And then the on-off circuit outside driving；

The parallel bus includes data/address bus, address bus and control signal；The digit of d type flip flop and the width of data/address bus Identical, the d type flip flop includes two, respectively d type flip flop U1 and d type flip flop U2；The address bus and control signal are logical Cross decoding circuit and generate two independent chip selection signals, two chip selection signals meet the CLK of d type flip flop U1 and d type flip flop U2 respectively End, the D ends of d type flip flop U1 and d type flip flop U2 all connect the outfan of data/address bus, d type flip flop U1 and d type flip flop U2 and export respectively Q1 and Q2 signals.

2. a kind of outlet logic circuit of reactive-load compensation intelligent controlling device as claimed in claim 1, is characterized in that, the logic Output of the input of gate circuit from two triggers, its logic isThe output of A ends is to FPGA pins, and then drives Move outside on-off circuit.

3. a kind of outlet logic circuit of reactive-load compensation intelligent controlling device as claimed in claim 2, is characterized in that, reset chip Reset signal connect d type flip flop U1 set end and d type flip flop U2 clear terminal, reset chip reset when export reset signal, Guarantee that d type flip flop exports stable signal, so that it is guaranteed that stable state is exported in powered on moment FPGA pins.