CN105259843A

CN105259843A - Outlet logic circuit of reactive power compensation type intelligent control device

Info

Publication number: CN105259843A
Application number: CN201510783748.8A
Authority: CN
Inventors: 王成友; 闫红华; 王俊杰
Original assignee: University of Jinan
Current assignee: University of Jinan
Priority date: 2015-11-13
Filing date: 2015-11-13
Publication date: 2016-01-20
Anticipated expiration: 2035-11-13
Also published as: CN105259843B

Abstract

The invention discloses an outlet logic circuit of a reactive power compensation type intelligent control device. The circuit comprises a CPU, an FPGA, and a reset chip. The parallel bus of the CPU is accessed to an FPGA. The reset signal of the reset chip is also accessed to the FPGA. The interior of the FPGA comprises a decoding circuit, two D triggers and a logic gate circuit. The address bus and the control signal, in the above parallel bus, are accessed to the decoding circuit to generate two independent chip selection signals. The data bus that passes through the chip selection signals and the parallel bus can independently control the output of each D trigger. The output signals of the two D triggers are accessed to the logic gate circuit. The output of the logic gate circuit is accessed to the output pin of the FPGA so as to drive an external switching circuit. The reset signal of the reset chip is connected with the control ends of the two D triggers. Since the FPGA is accessed to the design of the outlet logic circuit, the flexible programming of an interior circuit and the flexible output of an external pin are realized. The design flexibility is improved. The designed circuit is small in occupation area, low in cost, strong in anti-interference capability and high in reliability.

Description

A kind of outlet logic circuit of reactive-load compensation intelligent controlling device

Technical field

The present invention relates to outlet logic circuit engineering field, particularly relate to a kind of outlet logic circuit of reactive-load compensation intelligent controlling device.

Background technology

In the electrical network of China, alternating current sends from generator, through multistage defeated change distribution, finally arrives consumer.Consumer majority is the inductive load such as motor, transformer, if there is no Measures of Reactive Compensation, a large amount of reactive powers will flow to consumer from generator, just be filled with idle flowing from top to bottom, make defeated, become, join, using electricity system loss increase, transport capacity reduce, bad stability, even cause system crash.Current Measures of Reactive Compensation compensates mainly through switched capacitor.In addition, in network system, there is the electromagnetic interference (EMI) that switching over etc. causes in a large number, also the temporary faults such as superpotential, low-voltage, excess current occur once in a while.The existence of electromagnetic interference (EMI) should not cause capacitor miscarrying to cut, and in electrical network temporary fault situation, capacitor does not answer switching.

Outlet logic circuit is the nucleus module of reactive-load compensation intelligent controlling device.It carries out operation by CPU and controls, through certain sequential or logic is backward outer gives an order, the on-off circuits such as pilot relay, and then the switching of control capacitor.

Known to above, the height of outlet logic circuit performance directly affects the reliability of capacitor actions, and then affects the stable operation of network system.But current outlet logic circuit generally adopts special d type flip flop or latch chip to form, after the parallel bus write-once of CPU, directly control outlet and export.This circuit also exists poor anti jamming capability, account for plate area greatly, costly, the shortcoming of confidentiality difference.

Summary of the invention

Object of the present invention is exactly to solve the problem, a kind of outlet logic circuit of reactive-load compensation intelligent controlling device is provided, FPGA is introduced in the design of outlet logic circuit, internal circuit flexible programming can be accomplished, external terminal exports flexibly, improve the dirigibility of design.

To achieve these goals, the present invention adopts following technical scheme:

An outlet logic circuit for reactive-load compensation intelligent controlling device, comprises CPU, FPGA and reset chip, in the parallel bus access FPGA of described CPU, and the reset signal access FPGA of reset chip;

Described FPGA comprises decoding scheme, and described parallel bus access decoding scheme, generates multiple independently chip selection signal; Each chip selection signal connects a d type flip flop respectively, and the output signal access logic gates of d type flip flop, the output of described logic gates connects an output pin of FPGA, and then drives outside on-off circuit.

Described parallel bus comprises data bus, address bus and control signal.

The figure place of d type flip flop is identical with the width of data bus, and described d type flip flop comprises two, is respectively d type flip flop U1 and d type flip flop U2.

Described address bus and control signal generate two independently chip selection signals by decoding scheme, two chip selection signals connect the CLK end of d type flip flop U1 and d type flip flop U2 respectively, the D end of d type flip flop U1 and d type flip flop U2 all connects data bus, and the output terminal of d type flip flop U1 and d type flip flop U2 exports Q1 and Q2 signal respectively.

The input of described logic gates is from the output of two triggers, and its logic is that A=Q1+/Q2, A end outputs to FPGA pin, and then drives outside on-off circuit.

The reset signal of reset chip connects the set end of d type flip flop U1 and the clear terminal of d type flip flop U2, exports reset signal, guarantee the signal of d type flip flop stable output, thus guarantee the state at powered on moment FPGA pin stable output when reset chip resets.

Beneficial effect of the present invention:

FPGA is introduced in the design of outlet logic circuit, internal circuit flexible programming can be accomplished, external terminal exports flexibly, improve the dirigibility of design.

FPGA internal processes is difficult to be decrypted, and corresponding printed board is difficult to be plagiarized, copy, and improves confidentiality and the security of design.

When system requirements exports more, if use traditional design, a lot of trigger of increase or latch chip are also increased the area taking printed board, and adopts FPGA to design outlet logical circuit, only a chip enough completes, and greatly reduces cost.

In internal circuit, only have the output of two triggers outlet ability action under the opposite logic of regulation, improve the threshold of outlet action, thus enhance antijamming capability.

The reset signal of reset chip is introduced the design of outlet logic circuit, in electrification reset situation, trigger is in determines state, avoids the possibility of the misoperation that powers on, further increases reliability.

Accompanying drawing explanation

Fig. 1 is general structure schematic diagram of the present invention.

Fig. 2 is physical circuit schematic diagram of the present invention.

Embodiment

Below in conjunction with accompanying drawing and embodiment, the invention will be further described.

As shown in Figure 1, whole system is formed by CPU, reset chip and FPGA.FPGA adopts the A3P125 of ProASIC3 series of Microsemi company, and owing to adopting non-volatile FLASH technology, A3P125 has security, low-power consumption, power on the feature such as at once.CPU adopts the TMS320F28335 of TI company, and it possesses the ability that parallel bus exports, and comprises 16 bit data bus, 19 bit address buses and control signal wire etc.Reset chip adopts the TPS3705-33D of TI company, and the reset signal of output is low level.The parallel bus of CPU, the reset signal of reset chip are all connected to FPGA, and FPGA to FPGA pin, outputs to the on-off circuits such as external drive relay through inner logic circuit output signal afterwards.

As shown in Figure 2, from the address bus of CPU and control signal wire (chip selection signal CS, write signal WR) through decoding scheme generate two independently sheet select OUTCS1 and OUTCS2.At FPGA indoor design two independently d type flip flop U1, U2, U1, U2 are the trigger of 16, are consistent with the data-bus width of CPU.Wherein the D of two triggers holds the data bus DB all fetched from CPU, the CLK termination OUTCS2 of the CLK termination OUTCS1 of U1, U2.Output Q1, Q2 of trigger U1 and U2 access the two ends of gate circuit U3 respectively, and the gate logic of gate circuit U3 is: A=Q1+/Q2.A is outputted to the pin of FPGA.Like this by the rising edge of chip selection signal, by the value of data bus write Q end, thus the value of A can be changed, and then output to outside relay circuit, the switching of control capacitor.

General provision A exports as actuating of relay time " 0 ".If make A export as " 0 ", Q1 exports and should be " 0 ", Q2 exports and should be " 1 ", that is, trigger U1, U2 should export the value of regulation and two values just must can make the actuating of relay on the contrary, compared with single trigger or latch circuit, improves the threshold of the actuating of relay, increase the difficulty of the actuating of relay, thus enhance the antijamming capability of circuit.

The reset signal of reset chip connects the set end of U1 and the reset terminal of U2.Like this, at reset chip reseting period, the output Q1 of U1 is " 1 ", and the output Q2 of U2 is " 0 ", then exporting A is " 1 ", can ensure that A exports the state determined, and ensure that outside relay is failure to actuate, thus improve the reliability of circuit.

By reference to the accompanying drawings the specific embodiment of the present invention is described although above-mentioned; but not limiting the scope of the invention; one of ordinary skill in the art should be understood that; on the basis of technical scheme of the present invention, those skilled in the art do not need to pay various amendment or distortion that creative work can make still within protection scope of the present invention.

Claims

1. an outlet logic circuit for reactive-load compensation intelligent controlling device, is characterized in that, comprises CPU, FPGA and reset chip, in the parallel bus access FPGA of described CPU, and the reset signal access FPGA of reset chip;

2. the outlet logic circuit of a kind of reactive-load compensation intelligent controlling device as claimed in claim 1, it is characterized in that, described parallel bus comprises data bus, address bus and control signal.

3. the outlet logic circuit of a kind of reactive-load compensation intelligent controlling device as claimed in claim 2, it is characterized in that, the figure place of d type flip flop is identical with the width of data bus, and described d type flip flop comprises two, is respectively d type flip flop U1 and d type flip flop U2.

4. the outlet logic circuit of a kind of reactive-load compensation intelligent controlling device as claimed in claim 3, it is characterized in that, described address bus and control signal generate two independently chip selection signals by decoding scheme, two chip selection signals connect the CLK end of d type flip flop U1 and d type flip flop U2 respectively, the D end of d type flip flop U1 and d type flip flop U2 all connects data bus, and the output terminal of d type flip flop U1 and d type flip flop U2 exports Q1 and Q2 signal respectively.

5. the outlet logic circuit of a kind of reactive-load compensation intelligent controlling device as claimed in claim 4, it is characterized in that, the input of described logic gates is from the output of two triggers, and its logic is A=Q1+/Q2, A end outputs to FPGA pin, and then drives outside on-off circuit.

6. the outlet logic circuit of a kind of reactive-load compensation intelligent controlling device as claimed in claim 3, it is characterized in that, the reset signal of reset chip connects the set end of d type flip flop U1 and the clear terminal of d type flip flop U2, reset signal is exported when reset chip resets, guarantee the signal of d type flip flop stable output, thus guarantee the state at powered on moment FPGA pin stable output.