CN105259723A - Array substrate for liquid crystal display panel and manufacture method thereof - Google Patents
Array substrate for liquid crystal display panel and manufacture method thereof Download PDFInfo
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- CN105259723A CN105259723A CN201510824948.3A CN201510824948A CN105259723A CN 105259723 A CN105259723 A CN 105259723A CN 201510824948 A CN201510824948 A CN 201510824948A CN 105259723 A CN105259723 A CN 105259723A
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- insulation course
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- flatness layer
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/136295—Materials; Compositions; Manufacture processes
Abstract
The invention discloses an array substrate for a liquid crystal display panel. The array substrate comprises a display area (1) and an edge area (2) surrounding the display area (1), wherein the display area (1) and the edge area (2) are each provided with a flat layer (110) inside; each flat layer (110) is internally provided with a first groove (111a) and a second groove (111b) which is concaved down from the bottom of the first groove (111a), and a step difference exists between the first groove (111a) and the second groove (111b). The invention further discloses a manufacture method of the array substrate. According to the array substrate, two grooves with a step height difference are formed in each flat layer, so the height of the inner wall of each groove is effectively lowered, materials forming pixel electrodes in the edge area are prevented from remaining in the grooves, and meanwhile the situation that pixel electrodes in the display area are disconnected in the inner walls of the grooves can be prevented.
Description
Technical field
The invention belongs to technical field of liquid crystal display, specifically, relate to a kind of low temperature polycrystalline silicon (LowerTemperaturePolycrystalSilicon for liquid crystal panel, LTPS) thin film transistor (TFT) (ThinFilmTransistor, TFT) array base palte and preparation method thereof.
Background technology
Along with the evolution of photoelectricity and semiconductor technology, also the flourish of flat-panel monitor (FlatPanelDisplay) has been driven, and in many flat-panel monitors, liquid crystal display (LiquidCrystalDisplay, be called for short LCD) because having many advantageous characteristic such as high spatial utilization ratio, low consumpting power, radiationless and low EMI, become the main flow in market.
At present, as LCD on-off element and that extensively adopt is amorphous silicon membrane triode (a-SiTFT), but a-SiTFTLCD requires still to be restricted meeting slim, light weight, high-fineness, high brightness, high reliability, low-power consumption etc.Low temperature polycrystalline silicon (LowerTemperaturePolycrystalSilicon, LTPS) TFTLCD and a-SiTFTLCD compares, and meeting in above-mentioned requirements, has clear superiority.
In existing LTPSTFTLCD, generally include the liquid crystal panel with low-temperature polysilicon film transistor array base palte (being called for short Array substrate), box-like become by colored filter substrate (being called for short CF substrate).Array substrate has organic planarization layer usually, wherein, this organic planarization layer on the one hand can as the planarization depositional plane of pixel electrode, low-temperature polysilicon film transistor and pixel electrode can be isolated on the other hand, mutually disturb to prevent the electric field between low-temperature polysilicon film transistor and pixel electrode.
Usually, groove is provided with in this organic planarization layer, wherein, the groove being arranged in the organic planarization floor of viewing area (AA district) can make to be deposited on pixel electrode on this organic planarization floor drain contact by this groove and low-temperature polysilicon film transistor; But, because this organic planarization layer is thicker, easily cause at the slope place of this groove the material (such as tin indium oxide ITO) of pixel electrode to remain, thus easily cause the generation of leaky, and then affect the display quality of liquid crystal panel.
Summary of the invention
In order to solve above-mentioned prior art Problems existing, the object of the present invention is to provide a kind of array base palte for liquid crystal panel, comprise: viewing area and the edge district around described viewing area, all there is flatness layer in described viewing area and described edge district, there is the first groove and by recessed the second groove in the bottom of described first groove in described flatness layer, wherein, between described first groove and described second groove, there is step difference.
Further, described second groove is positioned at the centre position of the bottom of described first groove.
Further, the ratio of the degree of depth of described first groove and the degree of depth of described second groove is 4:1.
Another object of the present invention is also the method for making providing a kind of array base palte for liquid crystal panel, and described array base palte comprises: viewing area and the edge district around described viewing area, and wherein, described method for making comprises: provide a substrate; On the substrate of described viewing area, form low-temperature polysilicon film transistor, and on the substrate in described edge district, form the second insulation course, gate electrode, the 3rd insulation course and the second metal level successively; Form the flatness layer covering described low-temperature polysilicon film transistor and described second metal level; The first groove is formed and by recessed the second groove in the bottom of described first groove in described flatness layer; Wherein, expose the drain electrode of described low-temperature polysilicon film transistor at the second groove of described viewing area, expose described second metal level at second groove in described edge district; Passivation layer is formed on described flatness layer; Pixel electrode is formed on the passivation layer of described viewing area and in described first groove and described second groove; Wherein, described pixel electrode is by the drain electrode of low-temperature polysilicon film transistor described in described first groove and described second trench contact.
Further, described second groove is positioned at the centre position of the bottom of described first groove.
Further, the ratio of the degree of depth of described first groove and the degree of depth of described second groove is 4:1.
Further, the concrete grammar forming described first groove and described second groove in described flatness layer comprises: utilize exposure light shield to expose described flatness layer, to determine the first exposure area in described flatness layer; Mobile described exposure light shield; Wherein, the displacement of described exposure light shield is less than the width of described first exposure area; Described exposure light shield is utilized again to expose described flatness layer, to determine the second exposure area in described flatness layer; Wherein, described first exposure area and described second exposure area partially overlap; Described flatness layer after exposure is developed, removes with the flatness layer that will be in described first exposure area and described second exposure area, thus form described first groove and described second groove.
Further, described method for making also comprises: form light shield layer between the substrate in described viewing area and described low-temperature polysilicon film transistor; Wherein, described light shield layer and described low-temperature polysilicon film transistor are just oppositely arranged.
Further, described method for making also comprises: form the first insulation course between the substrate between described light shield layer and described low-temperature polysilicon film transistor and in described edge district and described second insulation course; Wherein, the first insulation course between described light shield layer and described low-temperature polysilicon film transistor covers described light shield layer.
Further, the method for making of described low-temperature polysilicon film transistor specifically comprises: on described first insulation course, form polysilicon layer; The second insulation course covering described polysilicon layer is formed on described first insulation course; Gate electrode is formed on described second insulation course; The 3rd insulation course covering described gate electrode is formed on described second insulation course; The first through hole and the second through hole is formed in described 3rd insulation course and described second insulation course; Wherein, described first through hole and described second through hole expose the surface of described polysilicon layer; Source electrode and drain electrode is formed on described 3rd insulation course; Wherein, described source electrode is filled described first through hole and is contacted the surface of described polysilicon layer, and described drain electrode is filled described second through hole and contacted the surface of described polysilicon layer.
Beneficial effect of the present invention: the present invention is by once moving and the double exposure of mobile front and back to flatness layer exposure light shield, form two grooves with bench height difference at the flatness layer being arranged in viewing area and edge district simultaneously, it is compared with the single groove formed in the flatness layer of prior art, significantly reduce the height of trench wall, avoiding the material forming pixel electrode in edge district remains in groove, can prevent the pixel electrode in viewing area from trench wall, occurring situation about breaking simultaneously.
Accompanying drawing explanation
The following description carried out in conjunction with the drawings, the above-mentioned and other side of embodiments of the invention, feature and advantage will become clearly, in accompanying drawing:
Fig. 1 is the schematic top plan view of low-temperature polysilicon film transistor array base palte according to an embodiment of the invention;
Fig. 2 is the sectional view in the edge district of low-temperature polysilicon film transistor array base palte according to an embodiment of the invention;
Fig. 3 is the schematic diagram forming the first groove and the second groove in the flatness layer according to an embodiment of the invention in edge district;
Fig. 4 is the sectional view of the viewing area of low-temperature polysilicon film transistor array base palte according to an embodiment of the invention;
Fig. 5 is the schematic diagram forming the first groove and the second groove according to an embodiment of the invention in flatness layer in the display area.
Embodiment
Below, embodiments of the invention are described in detail with reference to the accompanying drawings.But, the present invention can be implemented in many different forms, and the present invention should not be interpreted as being limited to the specific embodiment of setting forth here.On the contrary, provide these embodiments to be to explain principle of the present invention and practical application thereof, thus enable others skilled in the art understand various embodiment of the present invention and be suitable for the various amendments of certain expected application.
In the accompanying drawings, in order to know device, exaggerate the thickness in layer and region, identical label can be used to represent identical element in whole instructions with accompanying drawing.
Although will be appreciated that and term " first ", " second ", " the 3rd " etc. can be used here to describe various element, these elements should by the restriction of these terms.These terms are only for separating an element and another element region.
Also will be appreciated that when one deck or element are called as or be formed in another layer or substrate " on " or " on ", it can directly or be formed on this another layer or substrate, or also can there is middle layer.
Fig. 1 is the schematic top plan view of low-temperature polysilicon film transistor array base palte according to an embodiment of the invention.
With reference to Fig. 1, low-temperature polysilicon film transistor array base palte comprises according to an embodiment of the invention: viewing area (i.e. AA district) 1, around viewing area 1 edge district 2 and be positioned at side, viewing area 1 and be positioned at the IC district 3 beyond edge district 2.In the present embodiment, in edge district 2 and viewing area 1, all deposition is formed with organic planarization floor, and the organic planarization floor being arranged in edge district 2 and viewing area 1 is all formed with groove.Wherein, the groove of the organic planarization layer of viewing area 1 is arranged in for making drain electrode and the pixel electrode electrical contact of low-temperature polysilicon film transistor; And the groove being arranged in the organic planarization floor in edge district 2 is for improving the firmness of the frame glue be filled in wherein.
Below first the forming process of the organic planarization floor in edge district 2 is described.
Fig. 2 is the sectional view in the edge district of low-temperature polysilicon film transistor array base palte according to an embodiment of the invention.
With reference to Fig. 2, provide a substrate 101.In the present embodiment, substrate 101 can be transparent glass substrate, but the present invention is not restricted to this, and such as substrate 101 also can be transparent resin substrate.
The substrate 101 in edge district 2 is formed the first insulation course 103.In the present embodiment, the first insulation course 103 is formed by silicon nitride and monox, but the present invention is not restricted to this.
The second insulation course 105 is formed on first insulation course 103 in edge district 2; Wherein, in the present embodiment, the second insulation course 105 is formed by silicon nitride and monox, but the present invention is not restricted to this.
Gate electrode 106 is formed on second insulation course 105 in edge district 2.In the present embodiment, gate electrode 106 is formed by conducting metal, such as chromium, nickel etc.
The gate electrode 106 in edge district 2 forms the 3rd insulation course 107; Wherein, in the present embodiment, the 3rd insulation course 107 is formed by silicon nitride and monox, but the present invention is not restricted to this.
The second metal level 109 is formed on the 3rd insulation course 107 in edge district 2.Wherein, the second metal level 109 in viewing area 1 forms source electrode 109a and drain electrode 109b.In the present embodiment, the second metal level 109 is formed by conducting metal, such as chromium, nickel etc.
Flatness layer 110 is formed on second metal level 109 in edge district 2.Wherein, flatness layer 110 is formed by organic material.
The first groove 111a is formed and by the second groove 111b of the first groove 111a to lower recess in the flatness layer 110 in edge district 2.Wherein, the second groove 111b exposes the second metal level 109.
The flatness layer 110 in edge district 2 forms passivation layer 112.Wherein, in the first groove 111a and the second groove 111b, passivation layer 112 is not had.First groove 111a will be formed to the flatness layer 110 being arranged in edge district 2 and the second groove 111b is described in detail below.
Fig. 3 is the schematic diagram forming the first groove and the second groove in the flatness layer according to an embodiment of the invention in edge district.
With reference to Fig. 3, form flatness layer 110 on second metal level 109 in edge district 2 after, the flatness layer 110 in exposure light shield 200 pairs of edges district 2 is utilized to expose, to determine the first exposure area A in flatness layer 110.
Moving exposure light shield 200; Wherein, the displacement of exposure light shield 200 is less than the width of the first exposure area A.In the present embodiment, towards left moving exposure light shield 200, but the present invention is not restricted to this, such as also can towards right moving exposure light shield 200.
After exposure light shield 200 moves, exposure light shield 200 is utilized again to expose the flatness layer 110 in edge district 2, to determine the second exposure area B in the flatness layer 110 in edge district 2; Wherein, the first exposure area A overlaps with the second exposure area part B, that is, the intersection of the first exposure area A and the second exposure area B is double exposed.
The flatness layer 110 in the edge district 2 after exposure is developed, removes with the flatness layer 110 in the edge district 2 by the first exposure area A and the second exposure area B.Here, because the intersection of the first exposure area A and the second exposure area B is double exposed, it is more that the flatness layer 110 in the edge district 2 than other regions is removed by the flatness layer 110 being therefore in the edge district 2 of this overlapping region, thus the recessed formation second in the bottom groove 111b of the first groove 111a formed.Further, the recessed formation second in the centre position groove 111b of the bottom of the first groove 111a.
That is, in the flatness layer 110 in edge district 2, the first groove 111a with step and the second groove 111b is formed therebetween; Wherein, the degree of depth (or claiming height) of the first groove 111a is not less than 1:1 with the ratio of the degree of depth (or claiming height) of the second groove 111b and is not more than 5:1.Preferably, in the present embodiment, the degree of depth (or claiming height) of the first groove 111a is 4:1 with the ratio of the degree of depth (or claiming height) of the second groove 111b.Here, the degree of depth of the first groove 111a (or claiming height) refers to the distance between the upper surface of flatness layer 110 and described step, and the distance between the bottom that the degree of depth of the second groove 111b (or claiming height) refers to described step and the second groove 111b.
Like this, when etching the material of the formation pixel electrode 113 (shown in Fig. 4) on the flatness layer 110 in edge district 2, owing to there is difference in height between the first groove 111a and the second groove 111b, therefore can be clean by the material etch of the formation pixel electrode 113 in the first groove 111a and the second groove 111b, avoid that the material forming pixel electrode 113 remains and the leaky that causes occurs.
Then, the forming process of the organic planarization layer in viewing area 1 is described.
Fig. 4 is the sectional view of the viewing area of low-temperature polysilicon film transistor array base palte according to an embodiment of the invention.
With reference to Fig. 4, provide a substrate 101.In the present embodiment, substrate 101 can be transparent glass substrate, but the present invention is not restricted to this, and such as substrate 101 also can be transparent resin substrate.
The substrate 101 of viewing area 1 forms light shield layer 102.In the present embodiment, light shield layer 102 is oppositely arranged with the low-temperature polysilicon film transistor that will be formed, to make the raceway groove of light shield layer 102 pairs of low-temperature polysilicon film transistors carry out shading, thus prevent low-temperature polysilicon film transistor from producing leakage current because of illumination.
Further, light shield layer 102 and low-temperature polysilicon film transistor are just oppositely arranged.That is, see from bottom to top, light shield layer 102 blocks low-temperature polysilicon film transistor completely.
The substrate 101 of viewing area 1 is formed the first insulation course 103 covering light shield layer 102.That is, on the substrate 101 that light shield layer 102 is formed directly into viewing area 1, the substrate 101 that the first insulation course 103 is formed directly into viewing area 1 is gone up and covers light shield layer 102, and low-temperature polysilicon film transistor is formed directly on the first insulation course 103.In the present embodiment, the first insulation course 103 is formed by silicon nitride and monox, but the present invention is not restricted to this.Like this, the first insulation course 103 is formed in viewing area 1 and edge district 2 simultaneously.
Referring to Fig. 4, the formation of low-temperature polysilicon film transistor is specifically described.
Continue, with reference to Fig. 4, on the first insulation course 103 of viewing area 1, to form polysilicon layer 104; Wherein, polysilicon layer 104 is used for forming charge carrier movable passageway.
The second insulation course 105 covering polysilicon layer 104 is formed on the first insulation course 103 of viewing area 1; Wherein, in the present embodiment, the second insulation course 105 is formed by silicon nitride and monox, but the present invention is not restricted to this.Like this, the second insulation course 105 is formed in viewing area 1 and edge district 2 simultaneously.
Gate electrode 106 is formed on the second insulation course 105 of viewing area 1.In the present embodiment, gate electrode 106 is formed by conducting metal, such as chromium, nickel etc.Like this, gate electrode 106 is formed in viewing area 1 and edge district 2 simultaneously.
The 3rd insulation course 107 of covering grid electrode 106 is formed on the second insulation course 105 of viewing area 1; Wherein, in the present embodiment, the 3rd insulation course 107 is formed by silicon nitride and monox, but the present invention is not restricted to this.Like this, the 3rd insulation course 107 is formed in viewing area 1 and edge district 2 simultaneously.
The first through hole 108a and the second through hole 108b is formed in the 3rd insulation course 107 of viewing area 1 and the second insulation course 105 of viewing area 1; Wherein, the first through hole 108a and the second through hole 108b exposes the surface of polysilicon layer 104.
On the 3rd insulation course 107 of viewing area 1, form source electrode 109a and drain electrode 109b, here, the second metal level 109 on the 3rd insulation course 107 being deposited on viewing area 1 forms source electrode 109a and drain electrode 109b; Wherein, source electrode 109a fills the first through hole 108a and contacts the surface of polysilicon layer 104, and drain electrode 109b fills the second through hole 108b and contacts the surface of polysilicon layer 104.Like this, the second metal level 109 is formed in viewing area 1 and edge district 2 simultaneously.
It is more than the concrete forming process of low-temperature polysilicon film transistor according to an embodiment of the invention.Below continue to be described the formation of low-temperature polysilicon film transistor array base palte according to an embodiment of the invention.
Continue, with reference to Fig. 4, on the 3rd insulation course 107 of viewing area 1, to form the flatness layer 110 covering source electrode 109a and drain electrode 109b; Wherein, flatness layer 110 is formed by organic material.Like this, flatness layer 110 is formed in viewing area 1 and edge district 2 simultaneously.
In the flatness layer 110 of viewing area 1, form the first groove 111a and by the bottom of the first groove 111a to the second groove 111b of lower recess; Wherein, the second groove 111b exposes the drain electrode 109b of low-temperature polysilicon film transistor.
The flatness layer 110 of viewing area 1 forms passivation layer 112.Wherein, in the first groove 111a and the second groove 111b, passivation layer 112 is not had.
Pixel electrode 113 is formed on the passivation layer 112 of viewing area 1; Wherein, pixel electrode 113 is formed in the first groove 111a and the second groove 111b, and contacts the drain electrode 109b of low-temperature polysilicon film transistor with the second groove 111b by the first groove 111a.In the present embodiment, pixel electrode 113 is formed by tin indium oxide ITO, but the present invention is not restricted to this.Should be understood that, when deposition forms the material of pixel electrode 113, also the flatness layer 112 in edge district 2 deposits the material forming pixel electrode 113, but when forming pixel electrode 113, need the material etch of the formation pixel electrode 113 of deposition on the flatness layer 112 in edge district 2 to remove.
Be more than whole manufacturing process of low-temperature polysilicon film transistor array base palte according to an embodiment of the invention.Be specifically described to the first groove 111a of flatness layer 110 and the forming process of the second groove 111b that are arranged in viewing area 1 below.
Fig. 5 is the schematic diagram forming the first groove and the second groove according to an embodiment of the invention in flatness layer in the display area.
With reference to Fig. 5, form the flatness layer 110 covering source electrode 109a and drain electrode 109b on the 3rd insulation course 107 of viewing area 1 after, exposure light shield 200 pairs of flatness layers 110 are utilized to expose, to determine the first exposure area A in flatness layer 110.
Moving exposure light shield 200; Wherein, the displacement of exposure light shield 200 is less than the width of the first exposure area A.In the present embodiment, towards left moving exposure light shield 200, but the present invention is not restricted to this, such as also can towards right moving exposure light shield 200.
After exposure light shield 200 moves, exposure light shield 200 is utilized again to expose the flatness layer 110 of viewing area 1, to determine the second exposure area B in the flatness layer 110 of viewing area 1; Wherein, the first exposure area A overlaps with the second exposure area part B, that is, the intersection of the first exposure area A and the second exposure area B is double exposed.
The flatness layer 110 of the viewing area 1 after exposure is developed, removes with the flatness layer 110 of the viewing area 1 by the first exposure area A and the second exposure area B.Like this, because the intersection of the first exposure area A and the second exposure area B is double exposed, it is more that the flatness layer 110 of the viewing area 1 than other regions is removed by the flatness layer 110 being therefore in the viewing area 1 of this overlapping region, thus the recessed formation second in the bottom groove 111b of the first groove 111a.
Further, the second groove 111b is recessed to form downwards in the centre position of the bottom of the first groove 111a.
That is, in flatness layer 110, the first groove 111a with step and the second groove 111b is formed therebetween; Wherein, the degree of depth (or claiming height) of the first groove 111a is not less than 1:1 with the ratio of the degree of depth (or claiming height) of the second groove 111b and is not more than 5:1.Preferably, in the present embodiment, the degree of depth (or claiming height) of the first groove 111a is 4:1 with the ratio of the degree of depth (or claiming height) of the second groove 111b.Here, the degree of depth of the first groove 111a (or claiming height) refers to the distance between the upper surface of flatness layer 110 and described step, and the distance between the bottom that the degree of depth of the second groove 111b (or claiming height) refers to described step and the second groove 111b.
Like this, owing to having bench height difference between the first groove 111a and the second groove 111b, the pixel electrode 113 therefore in the first groove 111a and the second groove 111b not easily produces broken string, thus improves the yield of product.
According to embodiments of the invention, by once moving and the double exposure of mobile front and back to flatness layer exposure light shield, form two grooves with bench height difference at the flatness layer being arranged in viewing area and edge district simultaneously, it is compared with the single groove formed in the flatness layer of prior art, significantly reduce the height of trench wall, avoiding the material forming pixel electrode in edge district remains in groove, can prevent the pixel electrode in viewing area from trench wall, occurring situation about breaking simultaneously.
Although illustrate and describe the present invention with reference to specific embodiment, but it should be appreciated by those skilled in the art that: when not departing from the spirit and scope of the present invention by claim and equivalents thereof, the various changes in form and details can be carried out at this.
Claims (10)
1. the array base palte for liquid crystal panel, comprise: viewing area (1) and the edge district (2) around described viewing area (1), in described viewing area (1) and described edge district (2), all there is flatness layer (110), it is characterized in that, there is the first groove (111a) and by recessed the second groove (111b) in the bottom of described first groove (111a) in described flatness layer (110), wherein, between described first groove (111a) and described second groove (111b), there is step difference.
2. array base palte according to claim 1, is characterized in that, described second groove (111b) is positioned at the centre position of the bottom of described first groove (111a).
3. array base palte according to claim 1 and 2, is characterized in that, the ratio of the degree of depth of described first groove (111a) and the degree of depth of described second groove (111b) is 4:1.
4. for a method for making for the array base palte of liquid crystal panel, described array base palte comprises: viewing area (1) and the edge district (2) around described viewing area (1), and it is characterized in that, described method for making comprises:
One substrate (101) is provided;
On the substrate (101) of described viewing area (1), form low-temperature polysilicon film transistor, and on the substrate in described edge district (2), form the second insulation course (105), gate electrode (106), the 3rd insulation course (107) and the second metal level (109) successively;
Form the flatness layer (110) covering described low-temperature polysilicon film transistor and described second metal level (109);
Form the first groove (111a) in the described flatness layer (110) and by recessed the second groove (111b) in the bottom of described first groove (111a); Wherein, expose the drain electrode (109b) of described low-temperature polysilicon film transistor at second groove (111b) of described viewing area (1), expose described second metal level (109) at second groove (111b) in described edge district (2);
Passivation layer (112) is formed on described flatness layer (110);
Formation pixel electrode (113) in upper and described first groove (111a) of passivation layer (112) in described viewing area (1) and described second groove (111b); Wherein, described pixel electrode (113) contacts the drain electrode (109b) of described low-temperature polysilicon film transistor by described first groove (111a) and described second groove (111b).
5. method for making according to claim 4, is characterized in that, described second groove (111b) is positioned at the centre position of the bottom of described first groove (111a).
6. method for making according to claim 5, is characterized in that, the ratio of the degree of depth of described first groove (111a) and the degree of depth of described second groove (111b) is 4:1.
7. the method for making according to any one of claim 4 to 6, is characterized in that, the concrete grammar forming described first groove (111a) and described second groove (111b) in described flatness layer (110) comprises:
Exposure light shield (200) is utilized to expose described flatness layer (110), to determine the first exposure area (A) in described flatness layer (110);
Mobile described exposure light shield (200); Wherein, the displacement of described exposure light shield (200) is less than the width of described first exposure area (A);
Described exposure light shield (200) is utilized again to expose described flatness layer (110), to determine the second exposure area (B) in described flatness layer (110); Wherein, described first exposure area (A) and described second exposure area (B) partially overlap;
Described flatness layer (110) after exposure is developed, remove with the flatness layer (110) that will be in described first exposure area (A) and described second exposure area (B), thus form described first groove (111a) and described second groove (111b).
8. method for making according to claim 4, it is characterized in that, described method for making also comprises: between the substrate (101) and described low-temperature polysilicon film transistor of described viewing area (1), form light shield layer (102); Wherein, described light shield layer (102) and described low-temperature polysilicon film transistor are just oppositely arranged.
9. method for making according to claim 8, it is characterized in that, described method for making also comprises: between described light shield layer (102) and described low-temperature polysilicon film transistor and between the substrate (101) and described second insulation course (105) in described edge district (2), form the first insulation course (103); Wherein, the first insulation course (103) between described light shield layer (102) and described low-temperature polysilicon film transistor covers described light shield layer (102).
10. method for making according to claim 9, is characterized in that, the method for making of described low-temperature polysilicon film transistor specifically comprises:
Polysilicon layer (104) is formed on described first insulation course (103);
The second insulation course (105) covering described polysilicon layer (104) is formed on described first insulation course (103);
Gate electrode (106) is formed on described second insulation course (105);
The 3rd insulation course (107) covering described gate electrode (106) is formed on described second insulation course (105);
The first through hole (108a) and the second through hole (108b) is formed in described 3rd insulation course (107) and described second insulation course (105); Wherein, described first through hole (108a) and described second through hole (108b) expose the surface of described polysilicon layer (104);
Source electrode (109a) and drain electrode (109b) is formed on described 3rd insulation course (107); Wherein, described source electrode (109a) is filled described first through hole (108a) and is contacted the surface of described polysilicon layer (104), and described drain electrode (109b) is filled described second through hole (108b) and contacted the surface of described polysilicon layer (104).
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN201510824948.3A CN105259723B (en) | 2015-11-24 | 2015-11-24 | Array base palte for liquid crystal panel and preparation method thereof |
| PCT/CN2015/097735 WO2017088219A1 (en) | 2015-11-24 | 2015-12-17 | Array substrate for liquid crystal panel and manufacturing method therefor |
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| CN201510824948.3A CN105259723B (en) | 2015-11-24 | 2015-11-24 | Array base palte for liquid crystal panel and preparation method thereof |
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| CN105259723B CN105259723B (en) | 2017-04-05 |
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| CN (1) | CN105259723B (en) |
| WO (1) | WO2017088219A1 (en) |
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| CN106646968A (en) * | 2016-11-15 | 2017-05-10 | 上海中航光电子有限公司 | Display base board and production method, LED panel and LED device |
| WO2017136967A1 (en) * | 2016-02-14 | 2017-08-17 | 武汉华星光电技术有限公司 | Method for manufacturing array substrate and array substrate |
| WO2018161444A1 (en) * | 2017-03-10 | 2018-09-13 | 华为技术有限公司 | Liquid crystal display panel and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113471143B (en) * | 2020-03-31 | 2023-06-23 | 群创光电股份有限公司 | Method for manufacturing electronic device |
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Also Published As
| Publication number | Publication date |
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| CN105259723B (en) | 2017-04-05 |
| WO2017088219A1 (en) | 2017-06-01 |
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