CN105206510A - Small-line-width ultrahigh ion implantation barrier layer technique - Google Patents
Small-line-width ultrahigh ion implantation barrier layer technique Download PDFInfo
- Publication number
- CN105206510A CN105206510A CN201510662264.8A CN201510662264A CN105206510A CN 105206510 A CN105206510 A CN 105206510A CN 201510662264 A CN201510662264 A CN 201510662264A CN 105206510 A CN105206510 A CN 105206510A
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- CN
- China
- Prior art keywords
- barrier layer
- ion implantation
- implantation barrier
- live width
- superelevation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- 238000005468 ion implantation Methods 0.000 title claims abstract description 65
- 230000004888 barrier function Effects 0.000 title claims abstract description 63
- 238000000034 method Methods 0.000 title claims abstract description 32
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 28
- 238000001259 photo etching Methods 0.000 claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 8
- 239000010703 silicon Substances 0.000 claims abstract description 8
- 239000003795 chemical substances by application Substances 0.000 claims description 9
- 238000001900 extreme ultraviolet lithography Methods 0.000 claims description 3
- 238000007654 immersion Methods 0.000 claims description 3
- 238000001459 lithography Methods 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 abstract 11
- 239000011248 coating agent Substances 0.000 abstract 3
- 238000000576 coating method Methods 0.000 abstract 3
- 238000007687 exposure technique Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 56
- 230000000903 blocking effect Effects 0.000 description 3
- 239000007943 implant Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a small-line-width ultrahigh ion implantation barrier layer technique. The technique comprises the steps of coating a silicon wafer with an ion implantation barrier layer; coating the ion implantation barrier layer with an etching barrier layer; coating the etching barrier layer with a layer of photoresist; forming photoresist patterns with a predetermined line width on the photoresist by means of the exposure technique on a photoetching machine; etching etching barrier layer patterns corresponding to the photoresist patterns in the etching barrier layer by means of the photoresist patterns with the etching technique, and then removing the photoresist; etching ion implantation barrier layer patterns corresponding to the etching barrier layer patterns in the ion implantation barrier layer by means of the etching barrier layer patterns with the etching technique, and then removing the etching barrier layer; conducting ion implantation on the silicon wafer by means of the ion implantation barrier layer where the ion implantation barrier layer patterns are formed.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, the present invention relates to a kind of little live width superelevation ion implantation barrier layer process.
Background technology
In semiconductor fabrication process, some ion implanted layer has high ion implantation amount, this just needs extremely thick ion implantation barrier layer (the highest thickness can reach more than 3 microns), and current technology is that photoetching uses one deck photoresist, forms ion implantation live width after development.But when photoresist reaches certain thickness, the live width of ion implantation will be restricted, and can not reach less live width, as less than 0.2 micron, the thickness of photoresist and the ratio of live width will reach 1:15, as shown in Figure 1.
Summary of the invention
Technical problem to be solved by this invention is for there is above-mentioned defect in prior art, provides a kind of little live width superelevation ion implantation barrier layer process that can solve the problem of high ion implantation barrier layer and less ion implantation live width.
In order to realize above-mentioned technical purpose, according to the present invention, providing a kind of little live width superelevation ion implantation barrier layer process, comprising:
First, silicon chip is coated with one deck ion implantation barrier layer;
Subsequently, then ion implantation barrier layer is coated with one deck etch stop layer;
Subsequently, etch stop layer is coated with one deck photoresist;
Subsequently, by exposure technology on mask aligner equipment, form the photoetching agent pattern with predetermined live width on a photoresist;
Subsequently, by etch process, utilize photoetching agent pattern in etch stop layer, carve the etch stop layer pattern corresponding to photoetching agent pattern, remove photoresist subsequently;
Subsequently, by etch process, utilize etch stop layer pattern in ion implantation barrier layer, carve the ion implantation barrier layer pattern corresponding to etch stop layer pattern, remove etch stop layer subsequently;
Finally, the ion implantation barrier layer being formed with ion implantation barrier layer pattern is utilized to perform ion implantation to silicon chip.
Preferably, the thickness on ion implantation barrier layer is more than 3 microns.
Preferably, the thickness of etch stop layer is more than 100 nanometers.
Preferably, the thickness of photoresist is 100 nanometers.
Preferably, the thickness on ion implantation barrier layer is not less than 1:10 with the ratio of predetermined live width.
Preferably, predetermined live width is less than 0.2 micron.
Preferably, mask aligner equipment is I Lithography machine.
Preferably, mask aligner equipment is KrF mask aligner.
Preferably, mask aligner equipment is ArF mask aligner.
Preferably, mask aligner equipment is ArF immersion type photolithography machine or extreme ultra violet lithography.
For the situation requiring the photoresist thickness of superelevation, the ion implanted layer of little live width, only rely on single-layer lithography glue can not resolve little feature sizes, super thick implant blocking layer is used by the present invention, etch stop layer, photoresist three layer photoetching technique, minimum feature sizes can be resolved, have enough thick implant blocking layer blocks ions to inject.
Accompanying drawing explanation
By reference to the accompanying drawings, and by reference to detailed description below, will more easily there is more complete understanding to the present invention and more easily understand its adjoint advantage and feature, wherein:
Fig. 1 schematically shows the ion implantation barrier layer technique according to prior art.
Fig. 2 to Fig. 8 schematically shows each step of little according to the preferred embodiment of the invention live width superelevation ion implantation barrier layer process.
It should be noted that, accompanying drawing is for illustration of the present invention, and unrestricted the present invention.Note, represent that the accompanying drawing of structure may not be draw in proportion.Further, in accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention clearly with understandable, below in conjunction with specific embodiments and the drawings, content of the present invention is described in detail.
The present invention uses three layer photoetching technique (ion implantation barrier layers, etch stop layer, photoresist), make ion implantation barrier layer can reach more than 3 microns, the live width of ion implantation is determined by photoresist, if need little live width, photoresist thickness can reduce as required thus meet the requirement of less live width.Wherein, the mask aligner equipment that exposure uses can be I line (i-line) mask aligner, KrF mask aligner, ArF mask aligner, ArF immersion type photolithography machine, extreme ultra violet lithography according to live width size.
Concrete preferred embodiment of the present invention is described below with reference to the accompanying drawings.
Fig. 2 to Fig. 8 schematically shows each step of little according to the preferred embodiment of the invention live width superelevation ion implantation barrier layer process.
As shown in Fig. 2 to Fig. 8, little according to the preferred embodiment of the invention live width superelevation ion implantation barrier layer process comprises:
First, silicon chip 10 is coated with one deck ion implantation barrier layer 20; Preferably, the thickness on ion implantation barrier layer is more than 3 microns, as shown in Figure 2.
Subsequently, then ion implantation barrier layer 20 is coated with one deck etch stop layer 30; Preferably, consider the thickness on ion implantation barrier layer, the thickness of etch stop layer is more than 100 nanometers, as shown in Figure 3.
Subsequently, etch stop layer 30 is coated with one deck photoresist 40, as shown in Figure 4.Preferably, consider the thickness of etch stop layer, the thickness of photoresist is 100 nanometers, and the thickness of photoresist can be more than 100 nanometers.
Subsequently, by exposure technology on mask aligner equipment, photoresist 40 forms the photoetching agent pattern 41 with predetermined live width (namely required live width), as shown in Figure 5.Predetermined live width can be less live width, as less than 0.2 micron.
Subsequently, by etch process, utilize photoetching agent pattern 41 in etch stop layer, carve the etch stop layer pattern 31 corresponding to photoetching agent pattern 41, remove photoresist 40 subsequently, as shown in Figure 6.
Subsequently, by etch process, utilize etch stop layer pattern 31 in ion implantation barrier layer 20, carve the ion implantation barrier layer pattern 21 corresponding to etch stop layer pattern 31, remove etch stop layer 30 subsequently, as shown in Figure 7.
Finally, the ion implantation barrier layer being formed with ion implantation barrier layer pattern 21 is utilized to perform ion implantation to silicon chip 10, as shown in Figure 8.
The present invention reaches less live width by less photoresist thickness, and logical overetched ion implantation barrier layer can reach high stop thickness.The present invention can realize super thick implant blocking layer and live width compares at more than 1:10 (that is, the thickness on ion implantation barrier layer is not less than 1:10 with the ratio of predetermined live width).
In addition, it should be noted that, unless stated otherwise or point out, otherwise the term " first " in specification, " second ", " the 3rd " etc. describe only for distinguishing each assembly, element, step etc. in specification, instead of for representing logical relation between each assembly, element, step or ordinal relation etc.
Be understandable that, although the present invention with preferred embodiment disclose as above, but above-described embodiment and be not used to limit the present invention.For any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the technology contents of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (10)
1. a little live width superelevation ion implantation barrier layer process, is characterized in that comprising:
First, silicon chip is coated with one deck ion implantation barrier layer;
Subsequently, then ion implantation barrier layer is coated with one deck etch stop layer;
Subsequently, etch stop layer is coated with one deck photoresist;
Subsequently, by exposure technology on mask aligner equipment, form the photoetching agent pattern with predetermined live width on a photoresist;
Subsequently, by etch process, utilize photoetching agent pattern in etch stop layer, carve the etch stop layer pattern corresponding to photoetching agent pattern, remove photoresist subsequently;
Subsequently, by etch process, utilize etch stop layer pattern in ion implantation barrier layer, carve the ion implantation barrier layer pattern corresponding to etch stop layer pattern, remove etch stop layer subsequently;
Finally, the ion implantation barrier layer being formed with ion implantation barrier layer pattern is utilized to perform ion implantation to silicon chip.
2. little live width superelevation ion implantation barrier layer according to claim 1 process, it is characterized in that, the thickness on ion implantation barrier layer is more than 3 microns.
3. little live width superelevation ion implantation barrier layer according to claim 1 and 2 process, it is characterized in that, the thickness of etch stop layer is more than 100 nanometers.
4. little live width superelevation ion implantation barrier layer according to claim 1 and 2 process, it is characterized in that, the thickness of photoresist is 100 nanometers.
5. little live width superelevation ion implantation barrier layer according to claim 1 and 2 process, it is characterized in that, the thickness on ion implantation barrier layer is not less than 1:10 with the ratio of predetermined live width.
6. little live width superelevation ion implantation barrier layer according to claim 1 and 2 process, it is characterized in that, predetermined live width is less than 0.2 micron.
7. little live width superelevation ion implantation barrier layer according to claim 1 and 2 process, it is characterized in that, mask aligner equipment is I Lithography machine.
8. little live width superelevation ion implantation barrier layer according to claim 1 and 2 process, it is characterized in that, mask aligner equipment is KrF mask aligner.
9. little live width superelevation ion implantation barrier layer according to claim 1 and 2 process, it is characterized in that, mask aligner equipment is ArF mask aligner.
10. little live width superelevation ion implantation barrier layer according to claim 1 and 2 process, it is characterized in that, mask aligner equipment is ArF immersion type photolithography machine or extreme ultra violet lithography.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510662264.8A CN105206510A (en) | 2015-10-14 | 2015-10-14 | Small-line-width ultrahigh ion implantation barrier layer technique |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510662264.8A CN105206510A (en) | 2015-10-14 | 2015-10-14 | Small-line-width ultrahigh ion implantation barrier layer technique |
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| Publication Number | Publication Date |
|---|---|
| CN105206510A true CN105206510A (en) | 2015-12-30 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510662264.8A Pending CN105206510A (en) | 2015-10-14 | 2015-10-14 | Small-line-width ultrahigh ion implantation barrier layer technique |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020144543A1 (en) * | 2019-01-08 | 2020-07-16 | Parcan Nanotech Co., Ltd | Substrate for controlled implantation of ions and method of preparing substrate for controlled implantation of ions |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102315100A (en) * | 2011-09-28 | 2012-01-11 | 上海宏力半导体制造有限公司 | Method for graphical film |
| CN103560078A (en) * | 2013-11-13 | 2014-02-05 | 中国科学院微电子研究所 | Method for accurately controlling steepness when silicon carbide high-temperature ions are injected into mask |
| CN103578942A (en) * | 2013-11-12 | 2014-02-12 | 中国科学院微电子研究所 | Method for manufacturing silicon carbide high-temperature ion implantation mask with selectivity cut-off layer |
| CN104882369A (en) * | 2014-02-28 | 2015-09-02 | 株洲南车时代电气股份有限公司 | Silicon carbide ion implantation doped mask structure and preparation method thereof |
-
2015
- 2015-10-14 CN CN201510662264.8A patent/CN105206510A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102315100A (en) * | 2011-09-28 | 2012-01-11 | 上海宏力半导体制造有限公司 | Method for graphical film |
| CN103578942A (en) * | 2013-11-12 | 2014-02-12 | 中国科学院微电子研究所 | Method for manufacturing silicon carbide high-temperature ion implantation mask with selectivity cut-off layer |
| CN103560078A (en) * | 2013-11-13 | 2014-02-05 | 中国科学院微电子研究所 | Method for accurately controlling steepness when silicon carbide high-temperature ions are injected into mask |
| CN104882369A (en) * | 2014-02-28 | 2015-09-02 | 株洲南车时代电气股份有限公司 | Silicon carbide ion implantation doped mask structure and preparation method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020144543A1 (en) * | 2019-01-08 | 2020-07-16 | Parcan Nanotech Co., Ltd | Substrate for controlled implantation of ions and method of preparing substrate for controlled implantation of ions |
| US11798987B2 (en) | 2019-01-08 | 2023-10-24 | Parcan Nanotech Co., Ltd. | Substrate for a controlled implantation of ions and method of preparing a substrate for a controlled implantation of ions |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20151230 |
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| RJ01 | Rejection of invention patent application after publication |