KR20090067997A

KR20090067997A - Method for forming resist pattern of semiconductor device

Info

Publication number: KR20090067997A
Application number: KR1020070135847A
Authority: KR
Inventors: 김태환
Original assignee: 주식회사 하이닉스반도체
Priority date: 2007-12-21
Filing date: 2007-12-21
Publication date: 2009-06-25

Abstract

A method for forming a resist pattern of a semiconductor device is provided to obtain a resist shrinking pattern by performing an exposing process and a developing process on a resist shrinking material layer. A photoresist pattern(210) is formed on a semiconductor substrate(200). A primary thermal process is performed on the photoresist pattern. Resist shrinking material is coated on a resultant surface. A secondary thermal process is performed on the semiconductor substrate. Then, a process for patterning the resist shrinking material is performed. The resist shrinking material uses RELACS. The primary thermal process is performed at a temperature of 80 to 120 degree. The secondary thermal process is performed at a temperature of 100 to 160 degree.

Description

Method for forming resist pattern of semiconductor device

The present invention relates to a method of forming a pattern of a semiconductor device, and more particularly to a method of forming a resist pattern formed on a semiconductor substrate.

Since the invention of transistors, the design rules of semiconductor memory devices have been gradually reduced over the last 20 years, and thus, there is a demand for a high level of semiconductor technology capable of implementing a large number of memory devices in a limited area.

Among the semiconductor technologies, the lithography process has been recognized as the technology that directly affects the miniaturization of semiconductor devices. The miniaturization of devices is due to the nature of the semiconductor process, which is processed on a wafer basis, and how many devices can be processed simultaneously on a single wafer is a technology that is directly related to productivity, that is, price competitiveness of each device. Lithography technology is therefore committed to research and development with advances.

Currently, various technologies are being developed to reduce patterns in the lithography process of semiconductors, and the fields may be classified into lithography equipment, masks, and photoresists. Recently, RELACS (Resist Enhancement Lithography Assisted by Chemical Shrink) has been spotlighted as a material to be formed on a photoresist in a lithography process for forming a reduction pattern on a semiconductor substrate. The reason is that pattern reduction using RELACS material is more effective because it has a reduction volume without difference between patterns in device isolation region and high pattern density region.

1 to 2 are views showing a conventional resist pattern forming method.

Referring to FIG. 1, after the photoresist is coated on the semiconductor substrate 100, the photoresist pattern 110 is formed by performing exposure and development. Subsequently, a photoresist pattern and a RELACS material are cured by coating a resist reduction material on the entire surface of the semiconductor substrate on which the photoresist pattern 110 is formed, for example, by applying a predetermined thermal process (not shown). At this time, the photoresist pattern 110 is reduced while cross linking occurs between the photoresist and the RELACS material.

Then, after selectively exposing using a photomask, a development process using ultrapure water is performed to form the RELACS pattern 120.

However, since the water-soluble RELACS material is coated on the highly hydrophobic photoresist, the bonding force between the two materials is significantly reduced. Therefore, the RELACS material that is not bonded in the heat treatment process falls off during the development process using super water, resulting in coating defects as shown in the photograph of FIG. 2.

The present invention comprises the steps of forming a photoresist pattern on a semiconductor substrate; Performing a first heat treatment on the photoresist pattern; Coating a resist shrink material onto the entire surface of the resultant; Performing a second heat treatment on the semiconductor substrate coated with the resist reduction material; And patterning the resist shrink material.

The resist shrink material may use RELACS.

The first heat treatment may be performed at 80 ℃ to 120 ℃.

The secondary heat treatment may be performed at 100 ℃ to 160 ℃.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

3 to 5 are diagrams for explaining a method of forming a pattern of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 3, after the photoresist is coated on the semiconductor substrate 200, the photoresist pattern 210 is formed by performing exposure and development. Next, the photoresist pattern 210 is first heat treated at a temperature of 80 ° C. to 120 ° C. to cure the photoresist pattern 210.

The first heat treatment after the photoresist pattern formation helps the acid contained in the photoresist to come to the surface. As a result, the photoresist pattern 210 has a firm bonding force with a resist shrink material used in a subsequent process. Therefore, when developing the resist shrink material pattern with ultrapure water in a subsequent step, the resist shrink material does not fall off by the ultrapure water.

Referring to FIG. 4, for example, a resist enhancement lithography assisted by chemical shrink (RELACS) material is coated on the entire surface of the cured photoresist pattern 210 without using a cooling process. Next, in order to smoothly crosslink the photoresist pattern and the RELACS material, a second heat treatment is performed at a temperature of 100 ° C. to 160 ° C. to cure the photoresist pattern and the resist shrink material 220.

Then, a shrinkage phenomenon occurs between the surface of the photoresist pattern 210 from which the acid is removed by the first heat treatment and the coated resist shrinking material 220, thereby forming a tight bond and further improving contactability.

Referring to FIG. 5, a resist reduction pattern 220 is formed by performing an exposure and development process using a photomask on the coated resist reduction material layer. Then, the resist that is not bonded to the surface of the photoresist pattern 210 and the resist shrinking material The shrink material is removed by ultrapure water to form a resist shrink pattern 220.

As such, after the photoresist pattern is formed and the resist shrinkage material is coated, a heat treatment process may be performed to increase the bonding strength between the resist shrinkage material and the photoresist pattern.

The effect of the present invention is to standardize the process using a resist shrinking material in the technique of shrinking contact holes or lines and space patterns. The use of the material can increase the contact and secure the reduction technology.

As described above, the present invention has been described using, for example, a process of forming a pattern during an exposure process of a semiconductor device. However, the present invention can be usefully applied to a process of forming a contact hole and forming a line and a space pattern.

1 is a view illustrating a problem occurring in the resist pattern forming method of the semiconductor device of the prior art.

2 to 5 are views for explaining a method of forming a resist pattern of a semiconductor device according to the present invention.

Claims

Forming a photoresist pattern on the semiconductor substrate;

Performing a first heat treatment on the photoresist pattern;

Coating a resist shrink material onto the entire surface of the resultant;

Performing a second heat treatment on the semiconductor substrate coated with the resist reduction material; And

And patterning the resist shrink material.

The method of claim 1,

The resist reduction material is a resist pattern forming method of a semiconductor device using RELACS.

The method of claim 1,

The first heat treatment is a method of forming a resist pattern of a semiconductor device performed at 80 ℃ to 120 ℃.

The method of claim 1,

The second heat treatment is a method of forming a resist pattern of a semiconductor device performed at 100 ℃ to 160 ℃.