CN105204251A - Display base plate and manufacturing method thereof as well as display device - Google Patents
Display base plate and manufacturing method thereof as well as display device Download PDFInfo
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- CN105204251A CN105204251A CN201510540512.1A CN201510540512A CN105204251A CN 105204251 A CN105204251 A CN 105204251A CN 201510540512 A CN201510540512 A CN 201510540512A CN 105204251 A CN105204251 A CN 105204251A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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Abstract
The invention provides a display base plate and a manufacturing method thereof as well as a display device. The display base plate is used for solving the problem in the prior art that the display effect is influenced by the ultra-high leaping voltage of the pixel electrode caused by the application of COA (Certificate of Authenticity) technique. The display base plate comprises a substrate base plate, a grid line, a data line and pixel units, wherein the grid line and the data line are arranged on the substrate base plate in a crossing form; the pixel units in matrix arrangement are divided by the grid line and the data line; a thin film transistor, a pixel electrode, a colorful film layer and a public electrode line are arranged in each pixel unit; at least one of the pixel units further comprises a metal wire which is insulated from the public electrode line; along the orthographic projection direction, the metal wire is locally overlapped with the public electrode line.
Description
Technical field
The present invention relates to display technique field, particularly relate to a kind of display base plate and preparation method thereof and display device.
Background technology
Thin Film Transistor-LCD (ThinFilmTransistorLiquidCrystalDisplay, TFT-LCD) there is the features such as volume is little, low in energy consumption, radiationless, obtain in recent years and develop by leaps and bounds, in current flat panel display market, occupy leading position.TFT-LCD is widely used on various big-and-middle undersized product, almost cover the primary electron product of current information society, as LCD TV, high definition digital television, computer, mobile phone, car-mounted display, Projection Display, video camera, digital camera, accutron, counter, electronic instrument and meter, public display and illusory display etc.
TFT-LCD is made up of display panels, driving circuit and backlight module, and display panels is the pith of TFT-LCD.In order to improve aperture opening ratio and reduce box processing procedure difficulty, COA (ColorFilteronArray) technology is generally adopted to be prepared in by color layer to form the COA substrate comprising thin film transistor (TFT) and chromatic filter layer on array base palte at present, as shown in Figure 1.Fig. 1 is the structural representation of the COA substrate of prior art, as shown in Figure 1, existing COA substrate comprises underlay substrate 101, grid line 102, data line 103, thin film transistor (TFT) 104, color rete 105, passivation layer 106 (see Fig. 2) and transparency conducting layer 107 (see Fig. 2).
For twisted nematic (TwistNematic, TN) display panel of liquid crystal display mode, as shown in Figure 2, after the making completing color rete, in order to ensure display effect, color rete and black matrix can overlap, overlapping widths is about 7.5 μm, and due to public electrode wire 108 and black matrix almost edging, therefore color rete meeting cover part public electrode wire, makes the distance between transparency conducting layer and public electrode wire increase.According to the definition of electric capacity, when the distance between transparency conducting layer and public electrode wire increases, the coupling capacitance C between transparency conducting layer and public electrode wire
streduce, and then cause the saltus step amount Δ V of leaping voltage of pixel electrode
pincrease, affect display effect.
Summary of the invention
Embodiments provide a kind of display base plate and preparation method thereof and display device, in order to solve the problem affecting display effect in prior art because the leaping voltage of the pixel electrode adopting COA technology to cause is excessive.
Embodiments provide a kind of display base plate, described display base plate comprises underlay substrate, the grid line of arranged crosswise, data line and the pixel cell arranged in matrix that marked off by described grid line and described data line on described underlay substrate, is provided with thin film transistor (TFT), pixel electrode, color rete and public electrode wire in pixel cell described in each;
Pixel cell described at least one also comprises the metal wire arranged that to insulate with described public electrode wire, described metal wire on orthogonal projection direction at least partly with described public electrode line overlap.
In the display base plate that the embodiment of the present invention provides, comprise underlay substrate, the grid line of arranged crosswise, data line and the pixel cell arranged in matrix that marked off by described grid line and described data line on described underlay substrate, be provided with thin film transistor (TFT), pixel electrode, color rete and public electrode wire in pixel cell described in each; Pixel cell described at least one also comprises the metal wire arranged that to insulate with described public electrode wire, described metal wire is at least part of and described public electrode line overlap on orthogonal projection direction, to make described metal wire and described public electrode wire form building-out capacitor, for compensating the coupling capacitance C between transparency conducting layer and public electrode wire
st, solve existing because of the coupling capacitance C between transparency conducting layer and public electrode wire
streduce and the saltus step amount Δ V of the leaping voltage of pixel electrode that causes
pthe problem increased, improves the display effect of display panel.
Preferably, every two adjacent pixel cells form a pixel cell group, and an a pixel cell only corresponding pixel cell group; Wherein being respectively arranged with one above and below every a line pixel cell group for this pixel cell group provides the grid line of signal;
In each pixel cell group, a pixel cell is driven by the grid line be positioned at above this pixel cell group, and one other pixel unit is driven by the grid line be positioned at below this pixel groups.
Preferably, described metal wire is positioned at the top of described public electrode wire.
When described metal wire is positioned at the top of described public electrode wire, the right opposite that can increase between described metal wire and described public electrode wire amasss, and the building-out capacitor between metal wire and public electrode wire is increased.And, when described metal wire is positioned at the top of described public electrode wire, be convenient to described metal wire be electrically connected with thin film transistor (TFT) or pixel electrode, described metal wire and pixel electrode is made to have identical current potential, formed and be used for make described metal wire and described public electrode wire form building-out capacitor, for compensating, the coupling capacitance C between transparency conducting layer and public electrode wire
st.
Preferably, described thin film transistor (TFT) comprises: be positioned at the grid on described underlay substrate, be positioned at gate insulation layer above described grid, be positioned at the active layer above described insulation course, be positioned at the source electrode above described active layer and drain electrode, described public electrode wire and described grid are arranged with layer, and described metal wire and described source electrode and draining is arranged with layer.
In the process making display base plate, described public electrode wire and described grid are arranged with layer, described metal wire and described source electrode and draining is arranged with layer, described public electrode wire and described grid can be formed by one-time process, and form described metal wire and described source electrode and drain electrode by one-time process, be not only conducive to simplifying preparation technology, can also fabrication cycle be shortened, enhance productivity, reduce production cost.
Preferably, described metal wire is electrically connected with described drain electrode.
When described metal wire with described drain be electrically connected time, make described metal wire can obtain the current potential identical with pixel electrode, jointly form building-out capacitor with public electrode wire, eliminate COA technology to the impact of the leaping voltage of pixel electrode.
Preferably, in pixel cell group described in each, the wire insulation of two adjacent pixel cells is arranged.
In pixel cell group described in each, the wire insulation of two adjacent pixel cells is arranged, and makes the building-out capacitor of each pixel cell only relevant with the driving voltage of pixel electrode in this pixel cell, is conducive to improving the degree of accuracy compensated, improves display quality.
Based on same inventive concept, the embodiment of the present invention additionally provides a kind of display device, and described display device comprises display base plate as above.
Based on same inventive concept, the embodiment of the present invention additionally provides a kind of method for making of display base plate, described method is included in the step that underlay substrate formed data line, sweep trace, color rete, pixel electrode and public electrode wire and forms the step of thin film transistor (TFT), and described color rete, pixel electrode, public electrode wire and thin film transistor (TFT) are all formed in multiple pixel cells that described sweep trace and data line surround; Described method also comprises the step forming the metal wire insulated with described public electrode wire, and described metal wire is at least part of and described public electrode line overlap on orthogonal projection direction.
The display base plate that the method for making of the display base plate provided by the embodiment of the present invention is formed, comprise underlay substrate, the grid line of arranged crosswise, data line and the pixel cell arranged in matrix that marked off by described grid line and described data line on described underlay substrate, be provided with thin film transistor (TFT), pixel electrode, color rete and public electrode wire in pixel cell described in each; Described pixel cell also comprises the metal wire arranged that to insulate with described public electrode wire, described metal wire is at least part of and described public electrode line overlap on orthogonal projection direction, building-out capacitor is formed to make described metal wire and described public electrode wire, for compensating, the coupling capacitance C between transparency conducting layer and public electrode wire
st, solve existing because of the coupling capacitance C between transparency conducting layer and public electrode wire
streduce and the saltus step amount Δ V of the leaping voltage of pixel electrode that causes
pthe problem increased, improves the display effect of display panel.
Preferably, every two adjacent pixel cells form a pixel cell group, and an a pixel cell only corresponding pixel cell group; Wherein being respectively arranged with one above and below every a line pixel cell group for this pixel cell group provides the grid line of signal;
In each pixel cell group, a pixel cell is driven by the grid line be positioned at above this pixel cell group, and one other pixel unit is driven by the grid line be positioned at below this pixel groups.
For the display base plate of double-gate structure, region in the middle of each pixel cell group does not have setting data line, therefore described metal wire can be arranged on the area part between two pixel cells, this metal wire can be made with described source electrode and described drain electrode simultaneously, and then shortening fabrication cycle, reduce production cost.
Preferably, the step of described formation thin film transistor (TFT) comprises:
Described underlay substrate is formed the figure comprising grid;
The described substrate comprising the figure of grid forms gate insulation layer;
The substrate comprising described gate insulation layer is formed the figure including active layer;
The described substrate including the figure of active layer is formed the figure comprising source electrode and drain electrode.
In the method for above-mentioned formation thin film transistor (TFT), described public electrode wire and described grid line are arranged with layer, described metal wire and described source electrode and draining is arranged with layer, be conducive to simplifying preparation technology, also shorten fabrication cycle, enhance productivity, reduce production cost.
Preferably, described method specifically comprises:
Described underlay substrate is formed the figure comprising grid and public electrode wire;
The described substrate comprising the figure of grid and public electrode wire forms gate insulation layer;
The substrate comprising described gate insulation layer is formed the figure including active layer;
The described substrate including the figure of active layer comprises described in being formed the figure of source electrode, drain electrode and metal wire;
Described comprise source electrode, drain electrode and metal wire figure substrate on form the figure comprising color rete;
The described substrate comprising the figure of color rete is formed the figure comprising pixel electrode.
Preferably, before formation comprises the figure of pixel electrode, described method also comprises:
The described substrate comprising the figure of color rete forms passivation layer.
By forming passivation layer on the described substrate comprising the figure of color rete, color rete and thin film transistor (TFT) can be protected to avoid being damaged in follow-up preparation process, being conducive to improving display effect.
Accompanying drawing explanation
Fig. 1 is the top plan view of display base plate in prior art;
Fig. 2 is the sectional structure chart along A-A ' direction in Fig. 1;
The top plan view of the display base plate that Fig. 3 provides for the embodiment of the present invention one;
Fig. 4 is the sectional structure chart along D-D ' direction in Fig. 3;
The schematic flow sheet of the making display base plate that Fig. 5-Fig. 9 provides for the embodiment of the present invention two.
Embodiment
Embodiments provide a kind of display base plate and preparation method thereof and display device, in order to solve the problem affecting display effect in prior art because the leaping voltage of the pixel electrode adopting COA technology to cause is excessive.
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described.Obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
The embodiment of the present invention one provides a kind of display base plate, see Fig. 3 and 4; Composition graphs 3 and Fig. 4 can find out, described display base plate comprises underlay substrate 31, the grid line 32 of arranged crosswise, data line 33 and the pixel cell arranged in matrix that marked off by described grid line 32 and described data line 33 on described underlay substrate 31, is provided with thin film transistor (TFT) 34, pixel electrode 35 (see Fig. 4), color rete 36 and public electrode wire 37 in pixel cell described in each;
Pixel cell described at least one also comprises the metal wire 38 arranged that to insulate with described public electrode wire 37, and described metal wire 38 is overlapping with described public electrode wire 37 at least partly on orthogonal projection direction.
In the display base plate that the embodiment of the present invention provides, comprise underlay substrate, the grid line of arranged crosswise, data line and the pixel cell arranged in matrix that marked off by described grid line and described data line on described underlay substrate, be provided with thin film transistor (TFT), pixel electrode, color rete and public electrode wire in pixel cell described in each; Pixel cell described at least one also comprises the metal wire arranged that to insulate with described public electrode wire, described metal wire is at least part of and described public electrode line overlap on orthogonal projection direction, to make described metal wire and described public electrode wire form building-out capacitor, for compensating the coupling capacitance C between transparency conducting layer and public electrode wire
st, solve existing because of the coupling capacitance C between transparency conducting layer and public electrode wire
streduce and the saltus step amount Δ V of the leaping voltage of pixel electrode that causes
pthe problem increased, improves the display effect of display panel.
It can also be seen that from Fig. 3, the display base plate that the embodiment of the present invention one provides is the display base plate of double-gate structure, and wherein, every two adjacent pixel cells form a pixel cell group, and an a pixel cell only corresponding pixel cell group; Wherein being respectively arranged with one above and below every a line pixel cell group for this pixel cell group provides the grid line of signal;
In each pixel cell group, a pixel cell is driven by the grid line be positioned at above this pixel cell group, and one other pixel unit is driven by the grid line be positioned at below this pixel groups.
For the display base plate of double-gate structure, region in the middle of each pixel cell group does not have setting data line, therefore described metal wire 38 can be arranged on the area part between two pixel cells, this metal wire can be made with described source electrode and described drain electrode simultaneously, and then shortening fabrication cycle, reduce production cost.
Further, described metal wire 38 is positioned at the top of described public electrode wire 37.
When described metal wire is positioned at the top of described public electrode wire, the right opposite that can increase between described metal wire and described public electrode wire amasss, and the building-out capacitor between metal wire and public electrode wire is increased.And, when described metal wire is positioned at the top of described public electrode wire, be convenient to described metal wire be electrically connected with thin film transistor (TFT) or pixel electrode, described metal wire and pixel electrode is made to have identical current potential, formed and be used for make described metal wire and described public electrode wire form building-out capacitor, for compensating, the coupling capacitance C between transparency conducting layer and public electrode wire
st.
In the embodiment of the present invention, described thin film transistor (TFT) 34 comprises: be positioned at the grid (not shown) on described underlay substrate, be positioned at gate insulation layer 42 above described grid, be positioned at the active layer (not shown) above described gate insulation layer 42, be positioned at the source electrode (not shown) above described active layer and drain electrode (not shown); Wherein, described public electrode wire 37 and described grid are arranged with layer, and described metal wire and described source electrode to be arranged with layer with draining.
Therefore, in the process making display base plate, described public electrode wire and described grid are arranged with layer, described metal wire and described source electrode and draining is arranged with layer, described public electrode wire and described grid can be formed by one-time process, and form described metal wire and described source electrode and drain electrode by one-time process, not only be conducive to simplifying preparation technology, can also fabrication cycle be shortened, enhance productivity, reduce production cost.And, described public electrode wire and described grid are arranged with layer, described metal wire and described source electrode and draining be when arranging with layer, exist owing to only having gate insulation layer between metal wire and described public electrode wire, spacing is less, so can obtain larger electric capacity during the less overlapping area of both existence.Therefore, public electrode wire in the embodiment of the present invention can adopt graph thinning to design, and because this display base plate employing COA technology is without the need to considering box offset problem, black matrix can narrow along with the refinement of public electrode wire, therefore under the prerequisite not affecting display effect, can also improve aperture opening ratio further.
Further, described metal wire 38 adopts identical making material with described source electrode with draining, and the existing material generally selected in process is non-transparent metals and the alloys thereof such as Cr, W, Ti, Ta, Mo, Al, Cu.
Further, described metal wire 38 is electrically connected with described drain electrode.
When described metal wire 38 with described drain be electrically connected time, make described metal wire 38 can obtain the current potential identical with pixel electrode 35, jointly form building-out capacitor with public electrode wire 37, eliminate COA technology to the impact of the leaping voltage of pixel electrode.
Further, in pixel cell group described in each, the metal wire 38 of two adjacent pixel cells insulate and arranges.
By arranging the wire insulation of two pixel cells adjacent in pixel cell group described in each, make the building-out capacitor of each pixel cell only relevant with the driving voltage of pixel electrode in this pixel cell, be conducive to improving the degree of accuracy compensated, improve display quality.
Further, in order to protect color rete to avoid being damaged in follow-up preparation process, improve the display effect of display base plate, described display base plate also comprise be arranged on above described color rete, for the protection of it from the passivation layer 39 destroyed.And, in order to make by thin film transistor (TFT) as described pixel electrode 35 provides drive singal, at pixel electrode 35, the described corresponding position that drains is provided with via hole (not shown) in described passivation layer 39, described pixel electrode 35 is electrically connected with the drain electrode of described thin film transistor (TFT); In addition, all right protective film transistor of described passivation layer 39 is from destruction.
Based on same inventive concept, the embodiment of the present invention two additionally provides a kind of method for making of display base plate, and described method comprises:
Underlay substrate is formed the step of data line, sweep trace, pixel electrode and public electrode wire and forms the step of thin film transistor (TFT), described pixel electrode, public electrode wire and thin film transistor (TFT) are all formed in multiple pixel cells that described sweep trace and data line surround; Described method also comprises the step forming the metal wire insulated with described public electrode wire, and described metal wire is at least part of and described public electrode line overlap on orthogonal projection direction.
Further, every two adjacent pixel cells form a pixel cell group, and an a pixel cell only corresponding pixel cell group; Wherein being respectively arranged with one above and below every a line pixel cell group for this pixel cell group provides the grid line of signal;
In each pixel cell group, a pixel cell is driven by the grid line be positioned at above this pixel cell group, and one other pixel unit is driven by the grid line be positioned at below this pixel groups.
For the display base plate of double-gate structure, region in the middle of each pixel cell group does not have setting data line, therefore described metal wire can be arranged on the area part between two pixel cells, this metal wire can be made with described source electrode and described drain electrode simultaneously, and then shortening fabrication cycle, reduce production cost.
Wherein, the step of described formation thin film transistor (TFT) specifically comprises:
Described underlay substrate is formed the figure comprising grid;
The described substrate comprising the figure of grid forms gate insulation layer;
The substrate comprising described gate insulation layer is formed the figure including active layer;
The described substrate including the figure of active layer is formed the figure comprising source electrode and drain electrode.
In the method for above-mentioned formation thin film transistor (TFT), described public electrode wire and described grid line are arranged with layer, described metal wire and described source electrode and draining is arranged with layer, be conducive to simplifying preparation technology, also shorten fabrication cycle, enhance productivity, reduce production cost.And, described public electrode wire and described grid are arranged with layer, described metal wire and described source electrode and draining be when arranging with layer, exist owing to only having gate insulation layer between metal wire and described public electrode wire, spacing is less, so can obtain larger electric capacity during the less overlapping area of both existence.Therefore, public electrode wire in the embodiment of the present invention can adopt graph thinning to design, and because this display base plate employing COA technology is without the need to considering box offset problem, black matrix can narrow along with the refinement of public electrode wire, therefore under the prerequisite not affecting display effect, can also improve aperture opening ratio further.
Further, before formation comprises the figure of pixel electrode, described method also comprises:
The described substrate comprising the figure of color rete forms passivation layer.
By forming passivation layer on the described substrate comprising the figure of color rete, color rete can be protected to avoid being damaged in follow-up preparation process, being conducive to improving display effect.
For the display base plate provided in the embodiment of the present invention one, the method utilizing method provided by the present invention to make described display base plate specifically comprises:
The first step, see Fig. 5, forms the figure comprising grid (not showing in Fig. 5), grid line (not showing in Fig. 5) and public electrode wire 37 at described underlay substrate 31; This step specifically comprises:
Underlay substrate 31 is formed the metallic film of (as sputtering or coating etc.) one deck for the formation of grid, grid line and public electrode wire 37; Then, metallic film applies one deck photoresist; Then, with the mask plate being provided with the figure comprising grid, grid line and public electrode wire, photoresist is exposed; The figure comprising grid, grid line and public electrode wire is formed finally by after development, etching.In the method for making of the present embodiment display base plate, the manufacture craft relating to the rete formed by patterning processes is identical therewith, is after this no longer described in detail.
In the present invention, patterning processes, can only include photoetching process, or, comprise photoetching process and etch step, other techniques for the formation of predetermined pattern such as printing, ink-jet can also be comprised simultaneously; Photoetching process, refers to that utilize photoresist, mask plate, the exposure machine etc. that comprise the technological processs such as film forming, exposure, development form the technique of figure.Can according to the structure choice formed in the present invention corresponding patterning processes.
Second step, see Fig. 6, deposited silicon nitride (SiN on the described substrate comprising the figure of grid and public electrode wire 37
x) or monox (SiO
x) layer, form gate insulation layer 42.
3rd step, the substrate comprising described gate insulation layer 42 is formed the figure including active layer; This step specifically comprises:
By plasma enhanced chemical vapor deposition method or other similar approach, amorphous thin Film layers is formed above gate insulation layer 42, then by the technological process such as laser annealing technique or solid-phase crystallization technique, make recrystallized amorphous silicon, form layer polysilicon film, and formed the figure comprising low-temperature polysilicon silicon active layer by patterning processes process; The figure of described active layer is formed on described gate insulation layer 42.
4th step, see Fig. 7, the described substrate including the figure of active layer deposits a metal level, then by patterning processes process, forms the figure comprising source electrode, drain electrode and metal wire 38.
5th step, see Fig. 8, described comprise source electrode, drain electrode and metal wire 38 figure substrate on form the figure comprising color rete 36.
6th step, see Fig. 9, the described substrate comprising the figure of color rete 36 forms passivation layer 39, and forms via hole at described pixel electrode 35 with the described corresponding position that drains by patterning processes, described pixel electrode 35 is electrically connected with described drain electrode.
7th step, see Fig. 4, uses magnetron sputtering method on passivation layer 39, deposit indium oxide layer tin ITO transparent conductive film, and pass through patterning processes, namely through coating photoresist after exposure imaging, then after carrying out wet etching, peeling off, the figure comprising pixel electrode 35 is formed; Be filled with the conductive material for the formation of described pixel electrode in described via hole, described pixel electrode 35 is electrically connected with drain electrode by described via hole.
Based on above-mentioned same inventive concept, the embodiment of the present invention additionally provides a kind of display device, and described display device comprises above-mentioned display base plate.
In sum, embodiments provide a kind of display base plate and display device, described display base plate comprises underlay substrate, the grid line of arranged crosswise, data line and the pixel cell arranged in matrix that marked off by described grid line and described data line on described underlay substrate, is provided with thin film transistor (TFT), pixel electrode, color rete and public electrode wire in pixel cell described in each; Described pixel cell also comprises the metal wire arranged that to insulate with described public electrode wire, described metal wire is at least part of and described public electrode line overlap on orthogonal projection direction, building-out capacitor is formed to make described metal wire and described public electrode wire, for compensating, the coupling capacitance C between transparency conducting layer and public electrode wire
st, solve existing because of the coupling capacitance C between transparency conducting layer and public electrode wire
streduce and the saltus step amount Δ V of the leaping voltage of pixel electrode that causes
pthe problem increased, improves the display effect of display panel.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (12)
1. a display base plate, described display base plate comprises underlay substrate, the grid line of arranged crosswise, data line and the pixel cell arranged in matrix that marked off by described grid line and described data line on described underlay substrate, it is characterized in that, described pixel cell is provided with thin film transistor (TFT), pixel electrode, color rete and public electrode wire;
Pixel cell described at least one also comprises the metal wire arranged that to insulate with described public electrode wire, described metal wire on orthogonal projection direction at least partly with described public electrode line overlap.
2. display base plate as claimed in claim 1, is characterized in that, every two adjacent pixel cells form a pixel cell group, and an a pixel cell only corresponding pixel cell group; Wherein being respectively arranged with one above and below every a line pixel cell group for this pixel cell group provides the grid line of signal;
In each pixel cell group, a pixel cell is driven by the grid line be positioned at above this pixel cell group, and one other pixel unit is driven by the grid line be positioned at below this pixel groups.
3. display base plate as claimed in claim 2, it is characterized in that, described metal wire is positioned at the top of described public electrode wire.
4. display base plate as claimed in claim 2, described thin film transistor (TFT) comprises: be positioned at the grid on described underlay substrate, is positioned at gate insulation layer above described grid, be positioned at the active layer above described insulation course, be positioned at the source electrode above described active layer and drain electrode, it is characterized in that
Described public electrode wire and described grid are arranged with layer, and described metal wire and described source electrode and draining is arranged with layer.
5. display base plate as claimed in claim 4, it is characterized in that, described metal wire is electrically connected with described drain electrode.
6. display base plate as claimed in claim 1, is characterized in that, in pixel cell group described in each, the wire insulation of two adjacent pixel cells is arranged.
7. a display device, is characterized in that, described display device comprises the display base plate as described in claim as arbitrary in claim 1 ~ 6.
8. the method for making of a display base plate, it is characterized in that, described method is included in the step that underlay substrate formed data line, sweep trace, color rete, pixel electrode and public electrode wire and forms the step of thin film transistor (TFT), and described color rete, pixel electrode, public electrode wire and thin film transistor (TFT) are all formed in multiple pixel cells that described sweep trace and data line surround;
Described method also comprises the step forming the metal wire insulated with described public electrode wire, and described metal wire is at least part of and described public electrode line overlap on orthogonal projection direction.
9. method as claimed in claim 8, is characterized in that, every two adjacent pixel cells form a pixel cell group, and an a pixel cell only corresponding pixel cell group; Wherein be respectively arranged with one above and below every a line pixel cell group and provide the grid line of signal with this pixel cell group;
In each pixel cell group, a pixel cell is driven by the grid line be positioned at above this pixel cell group, and one other pixel unit is driven by the grid line be positioned at below this pixel groups.
10. method as claimed in claim 9, it is characterized in that, the step of described formation thin film transistor (TFT) comprises:
Described underlay substrate is formed the figure comprising grid;
The described substrate comprising the figure of grid forms gate insulation layer;
The substrate comprising described gate insulation layer is formed the figure including active layer;
The described substrate including the figure of active layer is formed the figure comprising source electrode and drain electrode.
11. methods as claimed in claim 10, it is characterized in that, described method specifically comprises:
Described underlay substrate is formed the figure comprising grid and public electrode wire;
The described substrate comprising the figure of grid and public electrode wire forms gate insulation layer;
The substrate comprising described gate insulation layer is formed the figure including active layer;
The described substrate including the figure of active layer comprises described in being formed the figure of source electrode, drain electrode and metal wire;
Described comprise source electrode, drain electrode and metal wire figure substrate on form the figure comprising color rete;
The described substrate comprising the figure of color rete is formed the figure comprising pixel electrode.
12. methods as claimed in claim 11, is characterized in that, before formation comprises the figure of pixel electrode, described method also comprises:
The described substrate comprising the figure of color rete forms passivation layer.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108922467A (en) * | 2018-06-26 | 2018-11-30 | 惠科股份有限公司 | Pixel circuit and display panel |
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| CN102937767A (en) * | 2012-10-29 | 2013-02-20 | 北京京东方光电科技有限公司 | Array substrate, display device and manufacturing method of array substrate |
| CN102981333A (en) * | 2012-11-21 | 2013-03-20 | 京东方科技集团股份有限公司 | Array substrate, and manufacturing method and display device thereof |
| CN103178082A (en) * | 2011-12-21 | 2013-06-26 | 乐金显示有限公司 | Display device and method for manufacturing the same |
| CN104714345A (en) * | 2015-04-08 | 2015-06-17 | 京东方科技集团股份有限公司 | Thin film transistor array substrate, liquid crystal display panel and display device |
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| CN103178082A (en) * | 2011-12-21 | 2013-06-26 | 乐金显示有限公司 | Display device and method for manufacturing the same |
| CN102937767A (en) * | 2012-10-29 | 2013-02-20 | 北京京东方光电科技有限公司 | Array substrate, display device and manufacturing method of array substrate |
| CN102981333A (en) * | 2012-11-21 | 2013-03-20 | 京东方科技集团股份有限公司 | Array substrate, and manufacturing method and display device thereof |
| CN104714345A (en) * | 2015-04-08 | 2015-06-17 | 京东方科技集团股份有限公司 | Thin film transistor array substrate, liquid crystal display panel and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108922467A (en) * | 2018-06-26 | 2018-11-30 | 惠科股份有限公司 | Pixel circuit and display panel |
| CN108922467B (en) * | 2018-06-26 | 2019-12-31 | 惠科股份有限公司 | Pixel circuit and display panel |
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