CN105186902A - ANPC type three-level inverter, modulation method and electrical equipment - Google Patents
ANPC type three-level inverter, modulation method and electrical equipment Download PDFInfo
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- CN105186902A CN105186902A CN201510574157.XA CN201510574157A CN105186902A CN 105186902 A CN105186902 A CN 105186902A CN 201510574157 A CN201510574157 A CN 201510574157A CN 105186902 A CN105186902 A CN 105186902A
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Abstract
The invention discloses an ANPC type three-level inverter, a modulation method and electrical equipment. The modulation method comprises steps that, a leg voltage instruction stands t1, t2 and t3 switch state change moments during transition from a positive half cycle to a negative half cycle, from the t1 moment, a T3 and a T6 are turned on, and a T2 and a T5 are maintained to turn on; from the t2 moment, the T2 and the T5 are turned off; from the t3 moment, the T3 is turned off, and the T4 is turned on; the Vo sequentially stands t11, t12 and t13 moments during transition from a negative half cycle to a positive half cycle, from the t11 moment, the T2 and the T5 are turned on, the T3 and the T6 are maintained to turn on; from the t12 moment, the T3 and the T6 are turned off; from t13 moment, the T2 is turned off, and the T1 is turned on; except two time segments of t1-t3 and t11-t13, a traditional ANPC type three-level inverter modulation method is followed in other time, so generation of a relatively long commutation loop during turning off a switch tube near a zero crossing point of the leg voltage instruction can be avoided.
Description
Technical field
The present invention relates to electric and electronic technical field, more particularly, relate to a kind of ANPC type three-level inverter, modulator approach and electric equipment.
Background technology
ANPC (ActiveNeutral-point-clamped, active neutral-point-clamped) type three-level inverter main circuit topology as shown in Figure 1, comprise 6 switch transistor T 1 ~ T6, 6 diode D1 ~ D6 and 2 Support Capacitor C1 ~ C2, wherein: the output termination T2 of T1, the input of T5, the input termination T3 of T4, the output of T6, the input of the output termination T6 of T5, the input termination direct current positive bus DC+ of T1, the output termination direct current negative busbar DC-of T4, the output of T2, the input of T3 all meets DC bus mid point O, the output of T5 is as ac output end AC, C1 is connected between DC+ and O, and C2 is connected between DC-and O, T1 anti-paralleled diode D1, T2 anti-paralleled diode D2, the like, T6 anti-paralleled diode D6.
Traditional ANPC type three-level inverter modulator approach is: when bridge arm voltage instruction Vo >=0, and keep T5 open-minded, keep T3, T4 and T6 to turn off, T1 and T2 complementation is open-minded simultaneously; As Vo < 0, keep T6 open-minded, keep T1, T2 and T5 to turn off, T3 and T4 complementation is open-minded simultaneously.
But, at bridge arm voltage instruction Vo near zero-crossing point, switching tube there will be longer commutation circuit when turning off, commutation circuit is longer, in loop, the inductance value of stray inductance is larger, the peak voltage born when so switching tube turns off is higher, if peak voltage exceedes the withstand voltage of switching tube, switching tube will be caused to demolish.
Summary of the invention
In view of this, the invention provides a kind of ANPC type three-level inverter, modulator approach and electric equipment, to avoid occurring longer commutation circuit when bridge arm voltage instruction near zero-crossing point on-off switching tube.
A kind of modulator approach of ANPC type three-level inverter, described ANPC type three-level inverter comprises switch transistor T 1 ~ T6 and 2 Support Capacitor C1 ~ C2 of 6 band anti-paralleled diodes, wherein: the output termination T2 of T1, the input of T5, the input termination T3 of T4, the output of T6, the input of the output termination T6 of T5, the input termination direct current positive bus of T1, the output termination direct current negative busbar of T4, the output of T2, the input of T3 all connects DC bus mid point, the output of T5 is as ac output end, C1 is connected between described direct current positive bus and described DC bus mid point, C2 is connected between described direct current negative busbar and described DC bus mid point, described modulator approach comprises:
Bridge arm voltage instruction changes the moment through t1, t2, t3 tri-on off states successively by during just half circumferential negative half period transition, wherein: the t1 moment rises, and T3, T6 are open-minded, maintains T2, T5 open-minded simultaneously; The t2 moment rises, and T2, T5 turn off; The t3 moment rises, and T3 turns off, and T4 is open-minded;
Bridge arm voltage instruction changes the moment through t11, t12, t13 tri-on off states by negative half period successively to during positive half cycle transition, wherein: the t11 moment rises, and T2, T5 are open-minded, maintains T3, T6 open-minded simultaneously; The t12 moment rises, and T3, T6 turn off; The t13 moment rises, and T2 turns off, and T1 is open-minded;
Except t1 ~ t3, two periods of t11 ~ t13, in all the other times, still follow traditional ANPC type three-level inverter modulator approach;
Wherein, the t1 moment is bridge arm voltage instruction positive half cycle finish time; Choosing of t2 moment should be enough to ensure that T3, T6 are open-minded; When described traditional ANPC type three-level inverter modulator approach is the anti-phase layered manner of carrier wave, choosing of t3 moment should not change the duty ratio size of-1 level at negative half period, when described traditional ANPC type three-level inverter modulator approach is carrier wave homophase layered manner, choosing of t3 moment should ensure that T2, T5 turn off completely; The t11 moment is bridge arm voltage instruction negative half period finish time; Choosing of t12 moment should be enough to ensure that T2, T5 are open-minded; When described traditional ANPC type three-level inverter modulator approach is the anti-phase layered manner of carrier wave, choosing of t13 moment should not change the duty ratio size of+1 level at positive half cycle, when described traditional ANPC type three-level inverter modulator approach is carrier wave homophase layered manner, choosing of t13 moment should ensure that T3, T6 turn off completely.
Wherein, t2 ~ t3, two periods of t12 ~ t13 are all set to equal Dead Time.
A kind of ANPC type three-level inverter, comprise main circuit and control unit, described main circuit comprises switch transistor T 1 ~ T6 and 2 Support Capacitor C1 ~ C2 of 6 band anti-paralleled diodes, wherein: the output termination T2 of T1, the input of T5, the input termination T3 of T4, the output of T6, the input of the output termination T6 of T5, the input termination direct current positive bus of T1, the output termination direct current negative busbar of T4, the output of T2, the input of T3 all connects DC bus mid point, the output of T5 is as ac output end, C1 is connected between described direct current positive bus and described DC bus mid point, C2 is connected between described direct current negative busbar and described DC bus mid point, described control unit is used for modulating according to the output voltage of preset rules to described main circuit, and described preset rules comprises:
Bridge arm voltage instruction changes the moment through t1, t2, t3 tri-on off states successively by during just half circumferential negative half period transition, wherein: the t1 moment rises, and T3, T6 are open-minded, maintains T2, T5 open-minded simultaneously; The t2 moment rises, and T2, T5 turn off; The t3 moment rises, and T3 turns off, and T4 is open-minded;
Bridge arm voltage instruction changes the moment through t11, t12, t13 tri-on off states by negative half period successively to during positive half cycle transition, wherein: the t11 moment rises, and T2, T5 are open-minded, maintains T3, T6 open-minded simultaneously; The t12 moment rises, and T3, T6 turn off; The t13 moment rises, and T2 turns off, and T1 is open-minded;
Except t1 ~ t3, two periods of t11 ~ t13, in all the other times, still follow traditional ANPC type three-level inverter modulator approach;
Wherein, the t1 moment is bridge arm voltage instruction positive half cycle finish time; Choosing of t2 moment should be enough to ensure that T3, T6 are open-minded; When described traditional ANPC type three-level inverter modulator approach is the anti-phase layered manner of carrier wave, choosing of t3 moment should not change the duty ratio size of-1 level at negative half period, when described traditional ANPC type three-level inverter modulator approach is carrier wave homophase layered manner, choosing of t3 moment should ensure that T2, T5 turn off completely; The t11 moment is bridge arm voltage instruction negative half period finish time; Choosing of t12 moment should be enough to ensure that T2, T5 are open-minded; When described traditional ANPC type three-level inverter modulator approach is the anti-phase layered manner of carrier wave, choosing of t13 moment should not change the duty ratio size of+1 level at positive half cycle, when described traditional ANPC type three-level inverter modulator approach is carrier wave homophase layered manner, choosing of t13 moment should ensure that T3, T6 turn off completely.
Wherein, t2 ~ t3, two periods of t12 ~ t13 are all set to equal Dead Time.
Wherein, T1 ~ T6 is IGBT or is MOSFET.
Wherein, described main circuit adopts 2 Support Capacitor C1 ~ C2 and 3, two level block to build;
Described 3 two level block comprise: two level block be made up of T1, T2, D1 and D2, two level block be made up of T3, T4, D3 and D4, and two level block be made up of T5, T6, D5 and D6.
A kind of electric equipment, comprises above-mentioned any one ANPC type three-level inverter disclosed.
Wherein, described electric equipment is photovoltaic DC-to-AC converter, wind electric converter or universal frequency converter.
As can be seen from above-mentioned technical scheme, under the anti-phase layered manner of carrier wave: when bridge arm voltage instruction Vo is by just half circumferential negative half period transition, + 0 level that the present invention controls should to turn off in the t11 moment exports finger delays and turns off to the t12 moment, it is open-minded that-0 level output branch road simultaneously should opened in dead band finish time is advanced to the t11 moment, thus avoid the appearance of long commutation circuit; Bridge arm voltage instruction Vo by negative half period to modulation strategy during positive half cycle transition in like manner;
Under carrier wave homophase layered manner: when bridge arm voltage instruction Vo is by just half circumferential negative half period transition, the present invention is before bridge arm current I exports the branch road change of current to-1 level output branch road by+0 level, insert-0 level and export branch road, carry out the change of current between-0 to-1 after completing the change of current between+0 to-0 again, thus avoid the appearance of long commutation circuit; Bridge arm voltage instruction Vo by negative half period to modulation strategy during positive half cycle transition in like manner.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is a kind of ANPC type three-level inverter main circuit topological structure schematic diagram disclosed in prior art;
Fig. 2 disclosed in prior art the anti-phase layered manner of a kind of carrier wave by positive half wave to work wave schematic diagram during negative half-wave transition;
Fig. 3 a-3b for follow the anti-phase layered manner of described carrier wave and bridge arm current I > 0 time, bridge arm voltage instruction is by commutation circuit path profile during just half circumferential negative half period transition;
Fig. 3 c is when bridge arm current I > 0, exports the commutation circuit path profile of the direct change of current of branch road to-0 level output branch road by+0 level;
Fig. 4 a-4b for follow the anti-phase layered manner of described carrier wave and bridge arm current I < 0 time, bridge arm voltage instruction is by commutation circuit path profile during just half circumferential negative half period transition;
Fig. 4 c is when bridge arm current I < 0, exports the commutation circuit path profile of the direct change of current of branch road to-0 level output branch road by+0 level;
Fig. 4 d disclosed in the embodiment of the present invention a kind of bridge arm voltage based on the anti-phase layered manner of carrier wave by the work wave schematic diagram of just half circumferential negative half period transition;
The work wave schematic diagram of Fig. 5 when a kind of carrier wave homophase layered manner is transitioned into negative half-wave by positive half wave disclosed in prior art;
Fig. 6 for follow described carrier wave homophase layered manner and bridge arm current I < 0 time, bridge arm voltage instruction is by the long commutation circuit path profile occurred during just half circumferential negative half period transition;
Fig. 7 disclosed in the embodiment of the present invention a kind of bridge arm voltage based on carrier wave homophase layered manner by the work wave schematic diagram of just half circumferential negative half period transition;
Fig. 8 is a kind of ANPC type three-level inverter structure structural representation disclosed in the embodiment of the present invention;
Fig. 9 is a kind of ANPC type three-level inverter main circuit topological structure schematic diagram disclosed in the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
The embodiment of the invention discloses a kind of modulator approach being applied to the type of ANPC shown in Fig. 1 three-level inverter, to avoid occurring longer commutation circuit when bridge arm voltage instruction near zero-crossing point on-off switching tube, comprising:
Bridge arm voltage instruction Vo changes the moment through t1, t2, t3 tri-on off states successively by during just half circumferential negative half period transition, wherein: the t1 moment rises, and T3, T6 are open-minded, maintains T2, T5 open-minded simultaneously; The t2 moment rises, and T2, T5 turn off; The t3 moment rises, and T3 turns off, and T4 is open-minded;
Bridge arm voltage instruction Vo changes the moment through t11, t12, t13 tri-on off states by negative half period successively to during positive half cycle transition, wherein: the t11 moment rises, and T2, T5 are open-minded, maintains T3, T6 open-minded simultaneously; The t12 moment rises, and T3, T6 turn off; The t13 moment rises, and T2 turns off, and T1 is open-minded;
Except t1 ~ t3, two periods of t11 ~ t13, in all the other times, still follow traditional ANPC type three-level inverter modulator approach;
Wherein, the t1 moment is bridge arm voltage instruction positive half cycle finish time; Choosing of t2 moment should be enough to ensure that T3, T6 are open-minded; When described traditional ANPC type three-level inverter modulator approach is the anti-phase layered manner of carrier wave, choosing of t3 moment should not change the duty ratio size of-1 level at negative half period, when described traditional ANPC type three-level inverter modulator approach is carrier wave homophase layered manner, choosing of t3 moment should ensure that T2, T5 turn off completely; The t11 moment is bridge arm voltage instruction negative half period finish time; Choosing of t12 moment should be enough to ensure that T2, T5 are open-minded; When described traditional ANPC type three-level inverter modulator approach is the anti-phase layered manner of carrier wave, choosing of t13 moment should not change the duty ratio size of+1 level at positive half cycle, when described traditional ANPC type three-level inverter modulator approach is carrier wave homophase layered manner, choosing of t13 moment should ensure that T3, T6 turn off completely.
The present embodiment carries out improving obtaining on the basis of traditional ANPC type three-level inverter modulator approach, in order to the technical scheme described in clearer description the present embodiment, start with from the operation principle of analysis conventional ANPC type three-level inverter modulator approach and Problems existing below, the operation principle of the present embodiment and beneficial effect are derived.
Known traditional ANPC type three-level inverter modulator approach is divided into the anti-phase layered manner of carrier wave and carrier wave homophase layered manner two kinds of forms.Under the anti-phase layered manner of carrier wave, the positive half cycle output waveform of bridge arm voltage instruction Vo is (+0)-(+1)-(+0), and negative half-cycle output waveform is (-0)-(-1)-(-0); Under carrier wave homophase layered manner, the positive half cycle output waveform of Vo is (+0)-(+1)-(+0), and negative half-cycle output waveform is (-1)-(-0)-(-1).The change of bridge arm voltage instruction Vo output level utilizes the switching state of switch transistor T 1 ~ T6 to control in real time, is specially: when keeping T1, T5 to open, bridge arm voltage instruction Vo exports+1 level; When keeping T2, T5 to open, bridge arm voltage instruction Vo exports+0 level; When keeping T3, T6 to open, bridge arm voltage instruction Vo exports-0 level; When keeping T4, T6 to open, bridge arm voltage instruction Vo exports-1 level; T1 ~ T6 all turn off and bridge arm current I > 0 time, bridge arm voltage instruction Vo exports-1 level; T1 ~ T6 all turn off and bridge arm current I < 0 time, bridge arm voltage instruction Vo exports+1 level.
For topology shown in Fig. 1, work wave corresponding to the anti-phase layered manner of carrier wave as shown in Figure 2.Below, when bridge arm voltage instruction Vo is by just half circumferential negative half period transition, respectively under bridge arm current I > 0 and bridge arm current I < 0 two kinds of operating modes, solution disclosed in the operation principle of the anti-phase layered manner of carrier wave, Problems existing and the present embodiment correspondence is analyzed.
1, under the operating mode of bridge arm current I > 0, when bridge arm voltage instruction Vo is by just half circumferential negative half period transition, exist:
1) the positive half cycle of Vo terminates eve output+0 level, and now T2, T5 are open-minded, and bridge arm current I is as I in Fig. 3 a
2shown in, I
2ac output end AC is flowed into through D2, T5 by DC bus mid point O;
2) Vo positive half cycle finish time T2, T5 turn off, and first Vo will export-0 level after entering negative half period, and namely T3, T6 are open-minded; But due to the existence of dead band (the Dead Time t1 ~ td namely marked out in Fig. 2), Vo entered in t1 ~ td time of negative half period, and T1 ~ T6 all turns off, because diode D4, D6 afterflow exports-1 level, the change of current terminates rear brachium pontis electric current I as I in Fig. 3 a
1shown in, I
1ac output end AC is flowed into through D4, D6 by direct current negative busbar DC-; By I
2to I
1commutation circuit be equivalent circulation I in Fig. 3 a
3the loop surrounded, also known as commutation circuit I
3;
3) in the td moment, T3, T6 are open-minded, and bridge arm current I is as I in Fig. 3 b
4shown in, I
4ac output end AC is flowed into by DC bus mid point O successively T3, D6; By I
1to I
4commutation circuit be equivalent circulation I in Fig. 3 b
5the loop surrounded, also known as commutation circuit I
5.
Known commutation circuit is longer, and the inductance value of the stray inductance existed in this commutation circuit is larger, and so switching tube peak voltage that will bear when turning off is higher, switching tube just may be caused to demolish when this peak voltage exceeds the voltage stress that it can bear.Commutation circuit I under above-mentioned operating mode
5shorter, the peak voltage that switching tube bears when turning off is lower, and commutation circuit I
3than commutation circuit I
5grow, the peak voltage that switching tube bears when turning off is higher, likely exceedes the voltage stress that it can bear, and there is switching tube demolition risk.For ease of describe, below will with commutation circuit I
3isometric commutation circuit classifies as long commutation circuit, will with commutation circuit I
5isometric commutation circuit classifies as short commutation circuit.
Under the operating mode that content 1 sets, switching tube switching state should be opened by T2, T5 that to be directly switch to T3, T6 open-minded in theory, and namely bridge arm current I should export the direct change of current of branch road from+0 level and export branch road to-0 level in theory, and commutation circuit is by I
2the change of current is to I
4short commutation circuit I
6, as shown in Figure 3 c.But due to the existence in dead band, bridge arm current I the first change of current can export branch road to corresponding-1 level of Dead Time before exporting the branch road change of current from+0 level and exporting branch road to-0 level, form the commutation course that output waveform is (+0)-(-1)-(-0), this just result in long commutation circuit I in Fig. 3 a
3appearance.
2, under the operating mode of bridge arm current I < 0, when bridge arm voltage instruction Vo is by just half circumferential negative half period transition, exist:
1) the positive half cycle of Vo terminates eve output+0 level, and now T2, T5 are open-minded, and bridge arm current I is as I in Fig. 4 a
2shown in, I
2dC bus mid point O is flowed into through D5, T2 by ac output end AC;
2) Vo positive half cycle finish time T2, T5 turn off, and first Vo will export-0 level after entering negative half period, and namely T3, T6 are open-minded; But equally due to the existence of dead band (the time period t 1 ~ td namely marked out in Fig. 2), Vo enters in t1 ~ td time of negative half period, T1 ~ T6 all turns off, and Vo is due to diode D5, D1 afterflow output+1 level, and the change of current terminates rear brachium pontis electric current I as I in Fig. 4 a
1shown in, I
1direct current positive bus DC+ is flowed into through D5, D1 by ac output end AC; By I
2to I
1commutation circuit be short commutation circuit I in Fig. 4 a
3;
3) in the td moment, T3, T6 are open-minded, and the change of current terminates rear brachium pontis electric current I as I in Fig. 4 b
4shown in, I
4dC bus mid point O is flowed into through T6, D3 by ac output end AC; By I
1to I
4commutation circuit be long commutation circuit I in Fig. 4 b
5.
Under the operating mode that content 2 sets, bridge arm current I should export the direct change of current of branch road from+0 level and export branch road to-0 level in theory, and commutation circuit is by I
2the change of current is to I
4short commutation circuit I
6, as illustrated in fig. 4 c.But due to the existence in dead band, bridge arm current I the first change of current can export branch road to corresponding+1 level of Dead Time before exporting the branch road change of current from+0 level and exporting branch road to-0 level, form the commutation course that output waveform is (+0)-(+1)-(-0), this just result in long commutation circuit I in Fig. 4 b
5appearance.
Roundup content 1 ~ 2 is known, under the anti-phase layered manner of carrier wave, when bridge arm voltage instruction Vo is from just half circumferential negative half period transition, due to the existence in dead band, exported branch road by+0 level and to export to-0 level in the commutation course of branch road insert Dead Time corresponding ± 1 level exports branch road, thus result in the appearance of long commutation circuit.For solving this problem, the present embodiment is not when changing inverter output waveforms, + 0 level that should turn off in the t1 moment exports finger delays and turns off to the t2 moment, it is open-minded that-0 level output branch road simultaneously should opened in the td moment is advanced to the t1 moment, avoid in Dead Time because diode continuousing flow exports ± 1 level, to ensure that+0 level exports branch road and can export branch road in the direct change of current of t2 moment to-0 level, thus when avoiding completing when causing peak voltage too high because there is long commutation circuit the transition of Vo by just half circumferential negative half period, see Fig. 4 d, make a concrete analysis of as follows:
1) the t1 moment rises, and T3, T6 are open-minded, maintains T2, T5 open-minded simultaneously, and now bridge arm current exports branch road and the output of-0 level output branch circuit parallel connection by+0 level; Because the t1 moment does not have switching tube to turn off action, therefore there will not be peak voltage;
2) the t2 moment rises, T2, T5 turn off, that commutation course is corresponding is Fig. 3 c (during I>0) and 4c (during I<0), now only there is+0 level and export branch road the exports branch road change of current to-0 level, due to be short commutation circuit and before and after the change of current output level constant, the problem that the peak voltage born when therefore commutation course does not exist on-off switching tube is too high; The t2 moment completes the transition of Vo by just half circumferential negative half period;
3) the t3 moment rises, and T3 turns off, and T4 is open-minded, and now bridge arm voltage instruction Vo exports-1 level; Because the present embodiment is when Vo is by just half circumferential negative half period transition, negative half period modulation strategy is improved, therefore want to guarantee that inverter output waveforms is constant, will ensure that-1 level is constant in the duty ratio of negative half period, shown in obvious Fig. 4 d, scheme does not change-1 level duty ratio, and thus brachium pontis output voltage is identical with bridge arm voltage instruction.
Under the anti-phase layered manner of carrier wave, bridge arm voltage instruction Vo by negative half period to occurring during positive half cycle transition that the analytic process of long commutation circuit in like manner can obtain.Bridge arm current I should export the direct change of current of branch road from-0 level and export branch road to+0 level in theory, and proving by the same methods is short commutation circuit.But due to the existence in dead band, bridge arm current I before exporting the branch road change of current from-0 level and exporting branch road to+0 level can the first change of current to Dead Time corresponding ± 1 level exports branch road, form the commutation course of (+0)-(± 1)-(-0), this just result in the appearance of long commutation circuit.Solution is: when not changing inverter output waveforms, + 0 level that should turn off in the t11 moment exports finger delays and turns off to the t12 moment, it is open-minded that-0 level output branch road simultaneously should opened in the td moment is advanced to the t11 moment, can in the direct change of current of t12 moment to+0 level output branch road to ensure that-0 level exports branch road, thus when avoiding completing Vo by the transition of negative half period to positive half cycle when causing peak voltage too high because there is long commutation circuit.
Work wave corresponding to carrier wave homophase layered manner as shown in Figure 5.Below, when bridge arm voltage instruction Vo is by just half circumferential negative half period transition, respectively under bridge arm current I > 0 and bridge arm current I < 0 two kinds of operating modes, solution disclosed in the operation principle of carrier wave homophase layered manner, Problems existing and the present embodiment correspondence is analyzed.
1, under the operating mode of bridge arm current I > 0, when bridge arm voltage instruction Vo is by just half circumferential negative half period transition, exist:
1) Vo positive half period terminates front output+0 level, and now T2, T5 are open-minded, I in bridge arm current I and Fig. 3 a
2unanimously, I
2ac output end AC is flowed into through D2, T5 by DC bus mid point O;
2) Vo positive half cycle finish time T2, T5 turn off, and first Vo will export-1 level after entering negative half period, and namely T4, T6 are open-minded; But due to the existence of dead band (the Dead Time t1 ~ td namely marked out in Fig. 5), so Vo enters in t1 ~ td time of negative half period, T1 ~ T6 all turns off, and Vo is due to diode D4, D6 afterflow reason output-1 level, and the change of current terminates I in rear brachium pontis electric current I and Fig. 3 a
1unanimously, I
1ac output end AC is flowed into through D4, D6 successively by direct current negative busbar DC-; By I
1to I
2commutation circuit and Fig. 3 a in long commutation circuit I
3unanimously;
3) in the td moment, T4, T6 are open-minded, and bridge arm current I maintains I
1state; Without commutation course.
2, under the operating mode of bridge arm current I < 0, when bridge arm voltage instruction Vo is by just half circumferential negative half period transition, exist:
1) Vo positive half period terminates front output+0 level, and now T2, T5 are open-minded, I in bridge arm current I and Fig. 4 a
2unanimously, I
2dC bus mid point O is flowed into through D5, T2 by ac output end AC;
2) Vo positive half cycle finish time T2, T5 turn off, and first Vo will export-1 level after entering negative half period, and namely T4, T6 are open-minded; But due to the existence of dead band (the Dead Time t1 ~ td namely marked out in Fig. 5), Vo enters in t1 ~ td time of negative half period, T1 ~ T6 all turns off, and Vo is due to diode D5, D1 afterflow reason output+1 level, and the change of current terminates I in rear brachium pontis electric current I and Fig. 4 a
1unanimously, I
1direct current positive bus DC+ is flowed into through D5, D1 successively by ac output end AC; By I
1to I
2commutation circuit and Fig. 4 a in short commutation circuit I
3unanimously;
3) in the td moment, T4, T6 are open-minded, and bridge arm current I is as I in Fig. 6
4shown in, I
4direct current negative busbar DC-is flowed into through D6, T4 by ac output end AC; By I
1to I
4commutation circuit be long commutation circuit I in Fig. 6
5.
Roundup content 1 ~ 2 is known, when bridge arm voltage instruction Vo is from just half circumferential negative half period transition, there is the commutation course of (+0)-(± 1)-(-1), known bridge arm current I by+0 level export the first change of current of branch road to Dead Time corresponding ± 1 level output branch road, continue the change of current again and export branch road (if no special instructions to-1 level, "+1 level exports branch road " that occur in literary composition all refers to that corresponding+1 level of non-Dead Time exports branch road, "-1 level export branch road " that occurs in literary composition all refers to that corresponding-1 level of non-Dead Time exports branch road) process in there will be long commutation circuit, overvoltage problem is there is when causing switching tube to turn off.Therefore the present embodiment is before bridge arm current I exports the branch road change of current to-1 level output branch road by+0 level, insert-0 level and export branch road, form the commutation course of (+0)-(-0)-(-1), to avoid occurring overvoltage problem in bridge arm voltage instruction by on-off switching tube during just half circumferential negative half period transition, see Fig. 7, concrete:
1) the t1 moment rises, and T3, T6 are open-minded, maintains T2, T5 open-minded simultaneously, and now bridge arm current exports branch road and the output of-0 level output branch circuit parallel connection by+0 level; Because the t1 moment does not have switching tube to turn off action, therefore there will not be peak voltage;
2) the t2 moment rises, T2, T5 turn off, now only there is+0 level and export branch road the exports branch road change of current to-0 level, that commutation course is corresponding is Fig. 3 c (during I>0) and Fig. 4 c (during I<0), the problem that peak voltage when this commutation course does not exist on-off switching tube is too high;
3) the t3 moment rises, and T3 turns off, and T4 is open-minded, and commutation course is served as reasons and-0 exported the branch road change of current to-1 level output branch road, is short commutation circuit, and the t3 moment completes the transition of Vo by just half circumferential negative half period;
About choosing of t3 moment, should ensure that+0 level exports branch road and turns off completely, namely should retain time enough and guarantee that the change of current that+0 level output branch road and-0 level export between branch road completes after t2, such as, arranging t2 ~ t3 time period equals Dead Time, certainly, also can arrange t2 ~ t3 time period is greater than Dead Time.Wherein, compensate to duty ratio the duty ratio that D=D0+ (t3-t1)/Tchop, D0 is-1 level under former modulator approach, D is-1 level duty ratio after compensating, and Tchop is PWM cycle corresponding to PWM frequency.
Under carrier wave homophase layered manner, bridge arm voltage instruction Vo by negative half period to occurring during positive half cycle transition that the analytic process of long commutation circuit in like manner can obtain.For avoid bridge arm current I by-1 level export the first change of current of branch road to Dead Time corresponding ± 1 level output branch road, continue the change of current again and occur long commutation circuit in the process of+0 level output branch road, the present embodiment is before bridge arm current I exports the branch road change of current to+0 level output branch road by-1 level, insert-0 level and export branch road, form the commutation course of (-1)-(-0)-(+0), to avoid occurring overvoltage problem by negative half period to on-off switching tube during positive half cycle transition in bridge arm voltage instruction.
Comprehensive foregoing description can be found out, under the anti-phase layered manner of carrier wave: when bridge arm voltage instruction Vo is by just half circumferential negative half period transition, + 0 level that the present embodiment controls should to turn off in the t11 moment exports finger delays and turns off to the t12 moment, it is open-minded that-0 level output branch road simultaneously should opened in the td moment is advanced to the t11 moment, complete the direct change of current between+0 level output branch road to-0 level output branch road, avoid bridge arm current first from+0 level export the branch road change of current to Dead Time corresponding ± 1 level exports branch road, continue the change of current exports branch road commutation course to-0 branch road again, thus avoid the appearance of long commutation circuit, bridge arm voltage instruction Vo by negative half period to modulation strategy during positive half cycle transition in like manner.Under carrier wave homophase layered manner: when bridge arm voltage instruction Vo is by just half circumferential negative half period transition, the present embodiment is before bridge arm current I exports the branch road change of current to-1 level output branch road by+0 level, insert-0 level and export branch road, achieve and first export the branch road change of current to-0 level output branch road from+0 level, export branch road from-0 level again and change the commutation course being left to-1 level output branch road, thus avoid the appearance of long commutation circuit; Bridge arm voltage instruction Vo by negative half period to modulation strategy during positive half cycle transition in like manner.
In addition, see Fig. 8, the embodiment of the invention also discloses this kind of ANPC type three-level inverter, to avoid occurring longer commutation circuit when bridge arm voltage instruction near zero-crossing point on-off switching tube, comprise main circuit 100 and control unit 200;
Wherein, main circuit 100 comprises switch transistor T 1 ~ T6 and 2 Support Capacitor C1 ~ C2 of 6 band anti-paralleled diodes, wherein: the output termination T2 of T1, the input of T5, the input termination T3 of T4, the output of T6, the input of the output termination T6 of T5, the input termination direct current positive bus of T1, the output termination direct current negative busbar of T4, the output of T2, the input of T3 all connects DC bus mid point, the output of T5 is as ac output end, C1 is connected between described direct current positive bus and described DC bus mid point, C2 is connected between described direct current negative busbar and described DC bus mid point,
Control unit 200 is for modulating according to the output voltage of preset rules to main circuit 100, and described preset rules comprises:
Bridge arm voltage instruction changes the moment through t1, t2, t3 tri-on off states successively by during just half circumferential negative half period transition, wherein: the t1 moment rises, and T3, T6 are open-minded, maintains T2, T5 open-minded simultaneously; The t2 moment rises, and T2, T5 turn off; The t3 moment rises, and T3 turns off, and T4 is open-minded;
Bridge arm voltage instruction changes the moment through t11, t12, t13 tri-on off states by negative half period successively to during positive half cycle transition, wherein: the t11 moment rises, and T2, T5 are open-minded, maintains T3, T6 open-minded simultaneously; The t12 moment rises, and T3, T6 turn off; The t13 moment rises, and T2 turns off, and T1 is open-minded;
Except t1 ~ t3, two periods of t11 ~ t13, in all the other times, still follow traditional ANPC type three-level inverter modulator approach;
Wherein, the t1 moment is bridge arm voltage instruction positive half cycle finish time; Choosing of t2 moment should be enough to ensure that T3, T6 are open-minded; When described traditional ANPC type three-level inverter modulator approach is the anti-phase layered manner of carrier wave, choosing of t3 moment should not change the duty ratio size of-1 level at negative half period, when described traditional ANPC type three-level inverter modulator approach is carrier wave homophase layered manner, choosing of t3 moment should ensure that T2, T5 turn off completely; The t11 moment is bridge arm voltage instruction negative half period finish time; Choosing of t12 moment should be enough to ensure that T2, T5 are open-minded; When described traditional ANPC type three-level inverter modulator approach is the anti-phase layered manner of carrier wave, choosing of t13 moment should not change the duty ratio size of+1 level at positive half cycle, when described traditional ANPC type three-level inverter modulator approach is carrier wave homophase layered manner, choosing of t13 moment should ensure that T3, T6 turn off completely.
Wherein, t2 ~ t3, two periods of t12 ~ t13 are all set to equal Dead Time.
Wherein, T1 ~ T6 can be IGBT (InsulatedGateBipolarTransistor, igbt), also can be MOSFET (MetalOxideSemiconductorFET, mos field effect transistor).Accompanying drawing disclosed in the present application is only IGBT exemplarily with T1 ~ T6.This three end of control end, input and output is comprised for T1, T1; When T1 is IGBT, the control end of T1 is the grid of IGBT, and the input of T1 is the collector electrode of IGBT, and the output of T1 is the emitter of IGBT; When T1 is MOSFET, the control end of T1 is the grid of MOSFET, and the input of T1 is the drain electrode of MOSFET, and the output of T1 is the source electrode of MOSFET.
Alternatively, consider that the power grade of existing integrated ANPC type three-level inverter main circuit topology is limited, therefore under high-power applications occasion, the present embodiment adopts powerful resolution element to build its main circuit topology, and the mode of building is: adopt 2 Support Capacitor C1 ~ C2 and 3 two level block to build main circuit.See Fig. 9, described 3 two level block comprise: the two level block #1 be made up of T1, T2, D1 and D2, the two level block #2 be made up of T3, T4, D3 and D4, and the two level block #3 be made up of T5, T6, D5 and D6.
In addition, the embodiment of the invention also discloses a kind of electric equipment, its internal applications has above-mentioned any one ANPC type three-level inverter disclosed.Described can be photovoltaic DC-to-AC converter, wind electric converter, universal frequency converter etc.
In sum, under the anti-phase layered manner of carrier wave: when bridge arm voltage instruction Vo is by just half circumferential negative half period transition, + 0 level that the present invention controls should to turn off in the t11 moment exports finger delays and turns off to the t12 moment, it is open-minded that-0 level output branch road simultaneously should opened in dead band finish time is advanced to the t11 moment, thus avoid the appearance of long commutation circuit; Bridge arm voltage instruction Vo by negative half period to modulation strategy during positive half cycle transition in like manner.Under carrier wave homophase layered manner: when bridge arm voltage instruction Vo is by just half circumferential negative half period transition, the present invention is before bridge arm current I exports the branch road change of current to-1 level output branch road by+0 level, insert-0 level and export branch road, carry out the change of current between-0 to-1 after completing the change of current between+0 to-0 again, thus avoid the appearance of long commutation circuit; Bridge arm voltage instruction Vo by negative half period to modulation strategy during positive half cycle transition in like manner.
Especially under large-power occasions; power model volume is larger; therefore commutation circuit can be longer; the peak voltage born when bridge arm voltage instruction near zero-crossing point switching tube turns off also can be higher; so switching tube demolition risk is also just larger, and when therefore this programme is applicable to large-power occasions, the protected effect of switch tube is particularly evident.
In this specification, each embodiment adopts the mode of going forward one by one to describe, and what each embodiment stressed is the difference with other embodiments, between each embodiment identical similar portion mutually see.For ANPC type three-level inverter disclosed in embodiment, because it is corresponding with embodiment of the method disclosed in embodiment, so description is fairly simple, relevant part illustrates see method part.
To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the present invention.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein when not departing from the spirit or scope of the embodiment of the present invention, can realize in other embodiments.Therefore, the embodiment of the present invention can not be restricted to these embodiments shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (8)
1. the modulator approach of an ANPC type three-level inverter, described ANPC type three-level inverter comprises switch transistor T 1 ~ T6 and 2 Support Capacitor C1 ~ C2 of 6 band anti-paralleled diodes, wherein: the output termination T2 of T1, the input of T5, the input termination T3 of T4, the output of T6, the input of the output termination T6 of T5, the input termination direct current positive bus of T1, the output termination direct current negative busbar of T4, the output of T2, the input of T3 all connects DC bus mid point, the output of T5 is as ac output end, C1 is connected between described direct current positive bus and described DC bus mid point, C2 is connected between described direct current negative busbar and described DC bus mid point, it is characterized in that, described modulator approach comprises:
Bridge arm voltage instruction changes the moment through t1, t2, t3 tri-on off states successively by during just half circumferential negative half period transition, wherein: the t1 moment rises, and T3, T6 are open-minded, maintains T2, T5 open-minded simultaneously; The t2 moment rises, and T2, T5 turn off; The t3 moment rises, and T3 turns off, and T4 is open-minded;
Bridge arm voltage instruction changes the moment through t11, t12, t13 tri-on off states by negative half period successively to during positive half cycle transition, wherein: the t11 moment rises, and T2, T5 are open-minded, maintains T3, T6 open-minded simultaneously; The t12 moment rises, and T3, T6 turn off; The t13 moment rises, and T2 turns off, and T1 is open-minded;
Except t1 ~ t3, two periods of t11 ~ t13, in all the other times, still follow traditional ANPC type three-level inverter modulator approach;
Wherein, the t1 moment is bridge arm voltage instruction positive half cycle finish time; Choosing of t2 moment should be enough to ensure that T3, T6 are open-minded; When described traditional ANPC type three-level inverter modulator approach is the anti-phase layered manner of carrier wave, choosing of t3 moment should not change the duty ratio size of-1 level at negative half period, when described traditional ANPC type three-level inverter modulator approach is carrier wave homophase layered manner, choosing of t3 moment should ensure that T2, T5 turn off completely; The t11 moment is bridge arm voltage instruction negative half period finish time; Choosing of t12 moment should be enough to ensure that T2, T5 are open-minded; When described traditional ANPC type three-level inverter modulator approach is the anti-phase layered manner of carrier wave, choosing of t13 moment should not change the duty ratio size of+1 level at positive half cycle, when described traditional ANPC type three-level inverter modulator approach is carrier wave homophase layered manner, choosing of t13 moment should ensure that T3, T6 turn off completely.
2. modulator approach according to claim 1, is characterized in that, t2 ~ t3, two periods of t12 ~ t13 are all set to equal Dead Time.
3. an ANPC type three-level inverter, comprise main circuit and control unit, described main circuit comprises switch transistor T 1 ~ T6 and 2 Support Capacitor C1 ~ C2 of 6 band anti-paralleled diodes, wherein: the output termination T2 of T1, the input of T5, the input termination T3 of T4, the output of T6, the input of the output termination T6 of T5, the input termination direct current positive bus of T1, the output termination direct current negative busbar of T4, the output of T2, the input of T3 all connects DC bus mid point, the output of T5 is as ac output end, C1 is connected between described direct current positive bus and described DC bus mid point, C2 is connected between described direct current negative busbar and described DC bus mid point, it is characterized in that, described control unit is used for modulating according to the output voltage of preset rules to described main circuit, described preset rules comprises:
Bridge arm voltage instruction changes the moment through t1, t2, t3 tri-on off states successively by during just half circumferential negative half period transition, wherein: the t1 moment rises, and T3, T6 are open-minded, maintains T2, T5 open-minded simultaneously; The t2 moment rises, and T2, T5 turn off; The t3 moment rises, and T3 turns off, and T4 is open-minded;
Bridge arm voltage instruction changes the moment through t11, t12, t13 tri-on off states by negative half period successively to during positive half cycle transition, wherein: the t11 moment rises, and T2, T5 are open-minded, maintains T3, T6 open-minded simultaneously; The t12 moment rises, and T3, T6 turn off; The t13 moment rises, and T2 turns off, and T1 is open-minded;
Except t1 ~ t3, two periods of t11 ~ t13, in all the other times, still follow traditional ANPC type three-level inverter modulator approach;
Wherein, the t1 moment is bridge arm voltage instruction positive half cycle finish time; Choosing of t2 moment should be enough to ensure that T3, T6 are open-minded; When described traditional ANPC type three-level inverter modulator approach is the anti-phase layered manner of carrier wave, choosing of t3 moment should not change the duty ratio size of-1 level at negative half period, when described traditional ANPC type three-level inverter modulator approach is carrier wave homophase layered manner, choosing of t3 moment should ensure that T2, T5 turn off completely; The t11 moment is bridge arm voltage instruction negative half period finish time; Choosing of t12 moment should be enough to ensure that T2, T5 are open-minded; When described traditional ANPC type three-level inverter modulator approach is the anti-phase layered manner of carrier wave, choosing of t13 moment should not change the duty ratio size of+1 level at positive half cycle, when described traditional ANPC type three-level inverter modulator approach is carrier wave homophase layered manner, choosing of t13 moment should ensure that T3, T6 turn off completely.
4. ANPC type three-level inverter according to claim 3, is characterized in that, t2 ~ t3, two periods of t12 ~ t13 are all set to equal Dead Time.
5. the ANPC type three-level inverter according to claim 3 or 4, it is characterized in that, T1 ~ T6 is IGBT or is MOSFET.
6. the ANPC type three-level inverter according to claim 3 or 4, is characterized in that, described main circuit adopts 2 Support Capacitor C1 ~ C2 and 3, two level block to build;
Wherein, described 3 two level block comprise: two level block be made up of T1, T2, D1 and D2, two level block be made up of T3, T4, D3 and D4, and two level block be made up of T5, T6, D5 and D6.
7. an electric equipment, is characterized in that, comprises the ANPC type three-level inverter according to any one of claim 3-6.
8. electric equipment according to claim 7, is characterized in that, described electric equipment is photovoltaic DC-to-AC converter, wind electric converter or universal frequency converter.
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