CN111697860B - Switch control method of multi-level inverter - Google Patents

Switch control method of multi-level inverter Download PDF

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CN111697860B
CN111697860B CN202010494360.7A CN202010494360A CN111697860B CN 111697860 B CN111697860 B CN 111697860B CN 202010494360 A CN202010494360 A CN 202010494360A CN 111697860 B CN111697860 B CN 111697860B
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bipolar transistor
insulated gate
gate bipolar
diode
bridge arm
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CN111697860A (en
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陈丹江
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Shenzhen Tiandepu Energy Storage Technology Co ltd
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Zhejiang Wanli University
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • H02M7/53875—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with analogue control of three-phase output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0051—Diode reverse recovery losses
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention discloses a switch control method of a multi-level inverter, which is characterized in that a second insulated gate bipolar transistor is controlled to be conducted in advance, so that direct switching between a P switch state and an N switch state can not occur in a transient state process of switching a switch state from P to Z when a phase current is greater than 0; by controlling the second insulated gate bipolar transistor to carry out delayed judgment, when the phase current is greater than 0, the direct switching between the switch states of P and N does not occur in the transient process of switching the switch state from Z to P; by controlling the delay judgment of the third insulated gate bipolar transistor, the direct switching between the switch states of P and N can not occur in the transient process of switching the switch state from Z to N when the phase current is less than 0; by controlling the third insulated gate bipolar transistor to be conducted in advance, when the phase current is less than 0, the direct switching between the switch states of P and N does not occur in the transient process of switching the switch state from N to Z; thereby reducing circuit losses.

Description

Switch control method of multi-level inverter
Technical Field
The invention relates to a switching control strategy of an inverter, in particular to a switching control method of a multi-level inverter.
Background
Compared with the traditional two-level inverter, the multi-level inverter has lower dv/dt value and total harmonic distortion, and becomes a feasible solution for medium-voltage and high-power application. A diode Neutral Point Clamped (NPC) inverter is a popular topology structure, and is widely applied to renewable energy systems, medium-voltage motor drives, pumped storage power stations, and other occasions. In recent years, multi-level inverters are gradually applied to low-voltage occasions, such as photovoltaic inverters, power factor correctors, electric vehicle systems and the like. On the basis of diode neutral point clamped inverters, three-level T-type inverters have been proposed by researchers, wherein the main circuit combines the advantages of the conventional two-level inverter and the advantages of a multi-level inverter, and is shown in FIG. 1, and the device S in FIG. 1a1Device Sa2Device Sa3Device Sa4Device Sb1Device Sb2Device Sb3Device Sb4Device Sc1Device Sc2Device Sc3Device Sc4Are all Insulated Gate Bipolar Transistors (IGBTs).
In practical applications, the modulation strategy of the inverter is an important consideration, because the modulation mode of the inverter has a great influence on the main performance of the inverter, such as efficiency, distortion, harmonic content, and the like. There are therefore a number of documents that have developed relevant research, such as carrier-based pulse width modulation, space vector modulation, etc. The modulation strategy of the inverter is essentially to control the on and off combination of the switches of each phase and to obtain the desired level output or other index.
At present, there are two main switch control strategies for the common three-level T-type inverter.
The first switching control strategy is referred to herein as M1, and the specific switching states, switching commands, and corresponding output leg voltages are shown in table 1. There are a number of documents that use such switching control strategies, such as: "Design and implementation of a high efficiency, three-level T-type converter Design and application for low-voltage applications" ("a high efficiency, three-level T-type converter Design and application suitable for low-voltage applications") (2013,28(2): 899-; also, for example, Ronak V.Nemade, Jay K.pandit, Mohan V.Aware et al, "Reconfiguration of T-type inverter for direct torque controlled inverter drive unit open-switch faults" ("Reconfiguration of T-type inverter in direct torque controlled industrial motor drive in open-circuit fault") published in IEEE Transactions on Industrial Applications (IEEE articles of Industrial application) (2017,53(3): 2936-.
TABLE 1M 1 switch states, switch commands, and output leg voltages
Figure BDA0002522222270000021
The second switching control strategy, referred to herein as M2, is shown in table 2 for specific switching states, switching commands, and corresponding output leg voltages. There are also documents that use such switching control strategies, such as: mokhtar Aly, Emad M.Ahmed, Masahito Shoyama et al, "development new life extension SVM algorithm for multiple level inverters with thermally aged Power devices" ("develop new life extension SVM algorithm for multilevel inverters with thermally aged Power devices") (2017,10(15): 2248-.
TABLE 2M 2 switch states, switch commands, and output leg voltages
Figure BDA0002522222270000022
The two switching control strategies described above each have disadvantages, and are described by taking phase a in the main circuit shown in fig. 1 as an example.
1) Disadvantage of the switching control strategy M1:
when the main circuit shown in fig. 1 adopts the switching control strategy M1 and enters into steady state operation, the current path in the "P" switching state is shown in fig. 2a, the current path in the "Z" switching state is shown in fig. 2b, and the current path in the "N" switching state is shown in fig. 2 c. In fig. 2a, 2b and 2c, the device names are given rectangular symbols indicating that the corresponding devices are provided with driving signals. In FIG. 2a, phase current i in the "P" switch statea>At 0 (with solid line current as reference), current flows through the device Sa1Flowing to a load; phase current ia<At 0, current flows through diode Da1From the load to the dc power supply. In FIG. 2b, phase current i in the "Z" switch statea>At 0, current passes through the device Sa2And a diode Da3Flowing to a load; phase current ia<At 0, current passes through the device Sa3And a diode Da2To the dc voltage midpoint. In FIG. 2c, phase current i in the "N" switch statea>At 0, current flows through diode Da4Flowing to a load; phase current ia<At 0, current passes through the device Sa4To the dc power supply. It can be seen that the device S in fig. 2aa2And device S in FIG. 2ca3Although the driving signals are all given, the driving signals do not pass through the two devices regardless of the phase current direction, that is, the switching control strategy is adopted under the condition that the three-level T-type inverter operates in a steady stateThere are two redundant drive signals in M1, including S in the "P" switch statea2And S in the "N" switch statea3The switching control strategy M1 increases the losses generated by the driver circuit.
2) Disadvantage of the switching control strategy M2:
phase current i using a switching control strategy M2a>When the switching state is 0, the switching of the switching state between the P switching state and the Z switching state is called a transient process; phase current ia<At 0, the switching of the switch state between the "Z" switch state and the "N" switch state is referred to as a transient process.
FIG. 3a shows phase current ia>Device S with switching state from "P" to "Z" at 0a1Device Sa2And a device Sa3High level in fig. 3a indicates that the corresponding device is on, low level indicates that the corresponding device is off, device S is switched between the "P" and "Z" switching states due to the switching statea4Is always in the off-state, so that device S is not shown in fig. 3aa4The gate of the transistor is switched on. FIG. 3b shows phase current ia>Device S with switching state from "Z" to "P" at 0a1Device Sa2And a device Sa3High level in fig. 3b indicates that the corresponding device is on and low level indicates that the corresponding device is off, since device S is switched between the "P" and "Z" switching states due to the switching statea4Is always in the off-state, so that device S is not shown in fig. 3ba4The gate of the transistor is switched on. Δ T1 in FIGS. 3a and 3b is the PWM dead time, typically on the order of microseconds. FIG. 3c shows phase current ia>Current path in the "P" switching state during switching of the "P" switching state to "Z" at 0, and phase current i is given in fig. 3da>The current path in the "N" switching state during the switching of the "P" to "Z" switching state at 0, and phase current i is given in FIG. 3ea>Current paths in the "Z" switching state during switching of the "P" to "Z" switching state at 0, and phase current i is given in fig. 3fa>Current paths in the "Z" switching state during switching of the "Z" switching state to "P" at 0, and phase current i is given in fig. 3ga>Current paths in the "N" switching state during switching of the "Z" switching state to "P" at 0, and phase current i is given in fig. 3ha>Current path in the "P" switch state during switching of switch state "Z" to "P" at 0. In fig. 3c, 3e, 3f and 3h, the device names are given rectangular symbols indicating that the corresponding devices are provided with driving signals. In FIG. 3c, the device S is useda1Drive signal, i.e. switching state "P", at which time phase current iaVia device Sa1. In FIG. 3d, when the device S is removeda1At the time of the drive signal of (1), phase current iaThrough diode Da4Freewheeling and the switch state changes to "N". In FIG. 3e, the device S is useda2And a device Sa3Drive signal, phase current iaPass device Sa2And a diode Da3And entering the steady-state working condition of the switch state Z. In FIG. 3f, the devices S are simultaneously feda2And a device Sa3Drive signal, i.e. switching state "Z", at which time phase current iaVia device Sa2And a diode Da3. In FIG. 3g, device S is removeda2And a device Sa3Phase current i of the driving signalaThrough diode Da4Freewheeling and the switch state changes to "N". In FIG. 3h, device Sa1Drive signal, phase current iaVia device Sa1And entering the steady-state working condition of the switch state P. As can be seen from fig. 3c and 3d, the switch state switches directly from "P" to "N"; as can be seen from FIGS. 3g and 3h, the switching state is switched directly from "N" to "P", i.e. in phase current ia>During the transient at 0, there is a direct switching between the "P" and "N" switching states, in which case the diode Da2And a diode Da3The voltage born by the two ends can be directly at plus Vdc2 'and' -V dc2 betweenSwitching, which causes a current to flow through the diode Da2And a diode Da3The reverse recovery current increases, causing additional circuit losses.
Also, at phase current ia<The "N" switch state and the "P" switch state are directly switched during the transient state at 0, which also causes extra circuit loss. FIG. 3i shows phase current ia<Device S with switching state from "Z" to "N" at 0a2Device Sa3Device Sa4High level in fig. 3i indicates that the corresponding device is on, low level indicates that the corresponding device is off, device S is switched between the "Z" switching state and the "N" switching state due to the switching statea1Is always in the off-state, so that device S is not shown in fig. 3ia1The gate of the transistor is switched on. FIG. 3j shows phase current ia<Device S with 0 switching state from "N" to "Z" switching statea2Device Sa3Device Sa4High level in fig. 3j indicates that the corresponding device is on and low level indicates that the corresponding device is off, since device S is switched between the "Z" and "N" switching states due to the switching statea1Is always in the off-state, so that device S is not shown in fig. 3ja1The gate of the transistor is switched on. Δ T1 in FIGS. 3i and 3j is the PWM dead time, typically on the order of microseconds. In FIG. 3i, first, device Sa2Device Sa3Is turned on and the device Sa4Off, the switch state is "Z"; the middle delta T1 interval is a dead zone; then device Sa2Device Sa3Is turned off, and the device Sa4On, the switch state is "N".
Disclosure of Invention
The technical problem to be solved by the invention is to provide a switch control method of a multi-level inverter, which enables a main circuit of a three-level T-shaped inverter to adopt the same mode as the existing switch control strategy when the main circuit works in a steady state so as to reduce the loss of a driving circuit when the main circuit works in the steady state; when the transient state work with the phase current larger than 0, the switching state is prevented from being directly switched between the switching state P and the switching state N by adjusting the on-off time of the second insulated gate bipolar transistor; and when the transient state work with the phase current less than 0, the switching state is prevented from being directly switched between the switching states 'N' and 'P' by adjusting the on-off time of the third insulated gate bipolar transistor.
The technical scheme adopted by the invention for solving the technical problems is as follows: a switching control method of a multilevel inverter is characterized by comprising the following steps:
step 1: building a three-level T-type inverter, wherein the three-level T-type inverter comprises a three-phase bridge arm circuit and two direct-current voltage sources, each phase of the bridge arm circuit consists of a first insulated gate bipolar transistor, a second insulated gate bipolar transistor, a third insulated gate bipolar transistor, a fourth insulated gate bipolar transistor, a first diode, a second diode, a third diode, a fourth diode, a resistor and an inductor, a collector electrode of the first insulated gate bipolar transistor is respectively connected with a positive electrode of a first direct-current voltage source and a negative electrode of the first diode, an emitter electrode of the first insulated gate bipolar transistor is respectively connected with a positive electrode of the first diode, a collector electrode of the third insulated gate bipolar transistor, a negative electrode of the third diode, a collector electrode of the fourth insulated gate bipolar transistor, a first diode, a second diode, a third diode, a fourth diode, a third diode and a fourth diode, The negative electrode of the fourth diode is connected with one end of the resistor, the collector of the second insulated gate bipolar transistor is respectively connected with the negative end of the first direct-current voltage source, the positive end of the second direct-current voltage source and the negative electrode of the second diode, the emitter of the second insulated gate bipolar transistor is respectively connected with the positive electrode of the second diode, the emitter of the third insulated gate bipolar transistor and the positive electrode of the third diode, the emitter of the fourth insulated gate bipolar transistor is respectively connected with the negative end of the second direct-current voltage source and the positive electrode of the fourth diode, the other end of the resistor is connected with one end of the first inductor, the other ends of the inductors in the three-phase bridge arm circuits are connected together, the first insulated gate bipolar transistor, the second diode, the third diode and the fourth diode are connected together, and the three-phase bridge arm circuits are connected with the other ends of the inductors in series and parallel The gate electrodes of the second insulated gate bipolar transistor, the third insulated gate bipolar transistor and the fourth insulated gate bipolar transistor are used for accessing a driving signal;
step 2: meanwhile, loading high level or low level to a first insulated gate bipolar transistor, a second insulated gate bipolar transistor, a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in a three-phase bridge arm circuit so as to realize that the switching state is switched from 'P' to 'Z' when the phase current of the three-level T-type inverter is greater than 0, wherein the specific process is as follows: loading a high level to a first insulated gate bipolar transistor in a three-phase bridge arm circuit, and loading a low level to a second insulated gate bipolar transistor, a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, so that the switching state of the three-level T-type inverter is P, and at the moment, the phase current is greater than 0 and passes through the first insulated gate bipolar transistor; then loading high level to a first insulated gate bipolar transistor and a second insulated gate bipolar transistor in the three-phase bridge arm circuit, loading low level to a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, wherein the duration time is delta T2, so that the switching state of the three-level T-type inverter is still P, and at the moment, the phase current is greater than 0 and passes through the first insulated gate bipolar transistor; loading a high level to a second insulated gate bipolar transistor in the three-phase bridge arm circuit, loading a low level to a first insulated gate bipolar transistor, a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, wherein the duration time is delta T1, switching the switching state of the three-level T-type inverter to Z, and enabling the phase current to be greater than 0 and to pass through the second insulated gate bipolar transistor and a third diode; loading high level to a second insulated gate bipolar transistor and a third insulated gate bipolar transistor in the three-phase bridge arm circuit, loading low level to a first insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit, enabling the switching state of the three-level T-type inverter to be still Z, and enabling the phase current to be larger than 0 and to pass through the second insulated gate bipolar transistor and a third diode at the moment;
and step 3: meanwhile, loading high level or low level to a first insulated gate bipolar transistor, a second insulated gate bipolar transistor, a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in a three-phase bridge arm circuit so as to realize that the switching state is switched from 'Z' to 'P' when the phase current of the three-level T-type inverter is greater than 0, wherein the specific process is as follows: loading high level to a second insulated gate bipolar transistor and a third insulated gate bipolar transistor in a three-phase bridge arm circuit, loading low level to a first insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit, enabling the switching state of the three-level T-type inverter to be Z, and enabling the phase current to be greater than 0 and to pass through the second insulated gate bipolar transistor and a third diode; then loading a high level to a second insulated gate bipolar transistor in the three-phase bridge arm circuit, loading a low level to a first insulated gate bipolar transistor, a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, wherein the duration time is delta T1, so that the switching state of the three-level T-type inverter is still Z, and at the moment, the phase current is greater than 0 and passes through the second insulated gate bipolar transistor and a third diode; loading high level to a first insulated gate bipolar transistor and a second insulated gate bipolar transistor in the three-phase bridge arm circuit, loading low level to a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, wherein the duration time is delta T2, switching the switching state of the three-level T-type inverter to be P, and enabling the phase current to be larger than 0 and to pass through the first insulated gate bipolar transistor; loading a high level to a first insulated gate bipolar transistor in the three-phase bridge arm circuit, and loading a low level to a second insulated gate bipolar transistor, a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, so that the switching state of the three-level T-type inverter is still P, and at the moment, the phase current is greater than 0 and passes through the first insulated gate bipolar transistor;
and 4, step 4: meanwhile, loading high level or low level to a first insulated gate bipolar transistor, a second insulated gate bipolar transistor, a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in a three-phase bridge arm circuit so as to realize that the switching state is switched from 'Z' to 'N' when the phase current of the three-level T-type inverter is less than 0, wherein the specific process is as follows: loading high level to a second insulated gate bipolar transistor and a third insulated gate bipolar transistor in a three-phase bridge arm circuit, loading low level to a first insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit, enabling the switching state of the three-level T-type inverter to be Z, and enabling the phase current to be less than 0 and to pass through the third insulated gate bipolar transistor and a second diode; then loading a high level to a third insulated gate bipolar transistor in the three-phase bridge arm circuit, loading a low level to a first insulated gate bipolar transistor, a second insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, wherein the duration time is delta T1, so that the switching state of the three-level T-type inverter is still Z, and at the moment, the phase current is less than 0 and passes through the third insulated gate bipolar transistor and a second diode; loading a high level to a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit, loading a low level to a first insulated gate bipolar transistor and a second insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, wherein the duration time is delta T2, switching the switching state of the three-level T-type inverter to 'N', and at the moment, the phase current is less than 0 and passes through the fourth insulated gate bipolar transistor; loading a high level to a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit, and loading a low level to a first insulated gate bipolar transistor, a second insulated gate bipolar transistor and a third insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, so that the switching state of the three-level T-type inverter is still N, and at the moment, the phase current is less than 0 and passes through the fourth insulated gate bipolar transistor;
and 5: meanwhile, loading high level or low level to a first insulated gate bipolar transistor, a second insulated gate bipolar transistor, a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in a three-phase bridge arm circuit so as to realize that the switching state is switched from 'N' to 'Z' when the phase current of the three-level T-type inverter is less than 0, and the specific process is as follows: loading a high level to a fourth insulated gate bipolar transistor in a three-phase bridge arm circuit, and loading a low level to a first insulated gate bipolar transistor, a second insulated gate bipolar transistor and a third insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, so that the switching state of the three-level T-type inverter is N, and at the moment, the phase current is less than 0 and passes through the fourth insulated gate bipolar transistor; then loading high level to a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit, loading low level to a first insulated gate bipolar transistor and a second insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, wherein the duration time is delta T2, so that the switching state of the three-level T-type inverter is still N, and at the moment, the phase current is less than 0 and passes through the fourth insulated gate bipolar transistor; loading a high level to a third insulated gate bipolar transistor in the three-phase bridge arm circuit, loading a low level to a first insulated gate bipolar transistor, a second insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, wherein the duration time is delta T1, switching the switching state of the three-level T-type inverter to Z, and enabling the phase current to be less than 0 and to pass through the third insulated gate bipolar transistor and a second diode; and loading high level to a second insulated gate bipolar transistor and a third insulated gate bipolar transistor in the three-phase bridge arm circuit, loading low level to a first insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit, so that the switching state of the three-level T-type inverter is still Z, and at the moment, the phase current is less than 0 and passes through the third insulated gate bipolar transistor and a second diode.
Δ T1 is the PWM dead time, Δ T1 ═ 5 μ s, and Δ T2 ═ 5 μ s.
Compared with the prior art, the invention has the advantages that:
1) compared with the traditional switch control strategy M1, the method removes redundant switch driving signals when the circuit works in a steady state, thereby reducing the loss of the driving circuit.
2) Compared with the traditional switch control strategy M2, the method solves the problem that the switch state is directly switched between 'P' and 'N' by adjusting the driving signal time sequence of a specific switch (an insulated gate bipolar transistor) in the transient working process of the circuit, thereby reducing the reverse recovery current of the diode in the main circuit of the three-level T-type inverter and reducing the loss of the diode.
Drawings
Fig. 1 is a circuit diagram of a main circuit of a conventional three-level T-type inverter;
FIG. 2a is a current path diagram for the "P" switch state of FIG. 1 under steady state operating conditions based on the switch control strategy M1;
FIG. 2b is a current path diagram for the "Z" switch state of FIG. 1 under steady state operating conditions based on the switch control strategy M1;
FIG. 2c is a current path diagram for the "N" switch state of FIG. 1 under steady state operating conditions based on the switch control strategy M1;
FIG. 3a shows phase current i of phase a in the transient operating state of FIG. 1, based on a switching control strategy M2a>Device S with switching state from "P" to "Z" at 0a1Device Sa2And a device Sa3The timing diagram of the drive signal of the gate access;
FIG. 3b shows phase current i of phase a in the transient operating state of FIG. 1, based on a switching control strategy M2a>Device S with switching state from "Z" to "P" at 0a1Device Sa2And a device Sa3The timing diagram of the drive signal of the gate access;
FIG. 3c shows phase current i of phase a in the transient operating state of FIG. 1, based on a switching control strategy M2a>A current path diagram in the switching state of 'P' in the process of switching the switching state 'P' to 'Z' at 0;
FIG. 3d shows phase current i of phase a in the transient operating state of FIG. 1, based on a switching control strategy M2a>A current path diagram in the process of switching the switching state "P" to "Z" at 0 time under the switching state "N";
FIG. 3e shows phase current i of phase a in the transient operating state of FIG. 1, based on a switching control strategy M2a>A current path diagram in the switching state of "Z" in the process of switching the switching state "P" to "Z" at 0;
FIG. 3f shows phase current i of phase a in the transient operating state of FIG. 1, based on a switching control strategy M2a>A current path diagram in the switching state of the 'Z' in the process of switching the switching state of the 'Z' to the 'P' at 0 time;
FIG. 3g shows phase current i of phase a in the transient operating state of FIG. 1, based on a switching control strategy M2a>A current path diagram in the process of switching the switching state Z to P at 0 under the switching state N;
FIG. 3h shows phase current i of phase a in the transient operating state of FIG. 1, based on a switching control strategy M2a>A current path diagram in the switching state of 'P' in the process of switching the switching state 'Z' to 'P' at 0;
FIG. 3i shows phase current i of phase a in the transient operating state of FIG. 1, based on a switching control strategy M2a<Device S with switching state from "Z" to "N" at 0a2Device Sa3Device Sa4The timing diagram of the drive signal of the gate access;
FIG. 3j shows phase current i of phase a in the transient operating state of FIG. 1 based on a switching control strategy M2a<Device S with 0 switching state from "N" to "Z" switching statea2Device Sa3Device Sa4The timing diagram of the drive signal of the gate access;
FIG. 4a shows phase current i of phase a in the transient operating state of FIG. 1, based on the method according to the inventiona>First IGBT S of a-phase with switching state at 0 time switched from 'P' switching state to 'Z' switching statea1A second insulated gate bipolar transistor S of phase aa2A third insulated gate bipolar transistor S of a phasea3The timing diagram of the drive signal of the gate access;
FIG. 4b shows phase current i of phase a in the transient operating state of FIG. 1, according to the method of the inventiona>A current path diagram in the switching state of 'P' in the process of switching the switching state 'P' to 'Z' at 0;
FIG. 4c shows phase current i of phase a in the transient operating state of FIG. 1, according to the method of the inventiona>Maintaining a current path diagram in the switching state of the P during the process that the switching state of the P is switched to the Z when the voltage is 0;
FIG. 4d shows phase current i of phase a in the transient operating state of FIG. 1, according to the method of the inventiona>A current path diagram in the switching state of "Z" in the process of switching the switching state "P" to "Z" at 0;
FIG. 4e shows phase current i of phase a in the transient operating condition of FIG. 1, according to the method of the present inventiona>Maintaining a current path diagram in a Z switching state in the process of switching the switching state P to Z when the voltage is 0;
FIG. 4f shows phase current i of phase a in the transient operating state of FIG. 1, according to the method of the inventiona>First IGBT S of a-phase with switching state at 0 time switched from "Z" to "P" switching statea1A second insulated gate bipolar transistor S of phase aa2A third insulated gate bipolar transistor S of a phasea3The timing diagram of the drive signal of the gate access;
FIG. 4g shows phase current i of phase a in the transient operating state of FIG. 1, according to the method of the inventiona>A current path diagram in the switching state of the 'Z' in the process of switching the switching state of the 'Z' to the 'P' at 0 time;
FIG. 4h shows phase current i of phase a in the transient operating state of FIG. 1, based on the method according to the inventiona>Maintaining a current path diagram in the Z switching state in the process of switching the switching state Z to P when the voltage is 0;
FIG. 4i shows phase current i of phase a in the transient operating condition of FIG. 1, based on the method of the present inventiona>A current path diagram in the switching state of 'P' in the process of switching the switching state 'Z' to 'P' at 0;
FIG. 4j shows phase current i of phase a in the transient operating condition of FIG. 1, according to the method of the present inventiona>Maintaining a current path diagram in a P switch state in the process of switching the switch state Z to P when the voltage is 0;
FIG. 5a shows phase current i of phase a in the transient operating state of FIG. 1, based on the method according to the inventiona<Second insulated gate bipolar transistor S of a phase under the condition that the switching state at 0 is switched from the 'Z' switching state to the 'N' switching statea2A third insulated gate bipolar transistor S of a phasea3And a phase fourth insulated gate bipolar transistor Sa4The timing diagram of the drive signal of the gate access;
FIG. 5b shows phase current i of phase a in the transient operating state of FIG. 1, according to the method of the inventiona<Second insulated gate bipolar transistor S of a phase under the condition that the switch state at 0 is switched from the 'N' switch state to the 'Z' switch statea2A third insulated gate bipolar transistor S of a phasea3And a phase fourth insulated gate bipolar transistor Sa4The timing diagram of the drive signal of the gate access;
FIG. 6a shows the DC voltage V of the DC voltage source in the main circuit of the three-level T-inverter of FIG. 1dcSetting 600V, and obtaining a simulation result when the phase current of the a phase is greater than 0 by adopting a switch control strategy M1 when each phase of load is a resistor with 8 ohms and is connected with an inductor with 20mH in series;
FIG. 6b is a partial enlarged view between 25ms and 26ms of the simulation results of FIG. 6 a;
FIG. 7a shows the DC voltage V of the DC voltage source in the main circuit of the three-level T-inverter of FIG. 1dcSetting 600V, and obtaining a simulation result when the phase current of the a phase is greater than 0 by adopting a switch control strategy M2 when each phase of load is a resistor with 8 ohms and is connected with an inductor with 20mH in series;
FIG. 7b is a partial enlarged view between 25ms and 26ms of the simulation result of FIG. 7 a;
FIG. 8a is a schematic diagram of the three-level T-inverter shown in FIG. 1DC voltage V of DC voltage source in main circuitdcSetting the voltage as 600V, and when each phase load is a resistor with 8 ohms and is connected with an inductor with 20mH in series, obtaining a simulation result when the phase current of the phase a is greater than 0 by adopting the method of the invention;
fig. 8b is a partial enlarged view between 25.5ms and 26ms of the simulation result of fig. 8 a.
Detailed Description
The invention is described in further detail below with reference to the accompanying examples.
The invention provides a switch control method of a multi-level inverter, which comprises the following steps:
step 1: a three-level T-type inverter is built by adopting PSIM simulation software, as shown in fig. 1, the three-level T-type inverter includes a three-phase bridge arm circuit and two dc voltage sources, each phase of bridge arm circuit is composed of a first insulated gate bipolar transistor, a second insulated gate bipolar transistor, a third insulated gate bipolar transistor, a fourth insulated gate bipolar transistor, a first diode, a second diode, a third diode, a fourth diode, a resistor and an inductor, a collector of the first insulated gate bipolar transistor is connected with a positive terminal of the first dc voltage source and a negative terminal of the first diode, an emitter of the first insulated gate bipolar transistor is connected with a positive terminal of the first diode, a collector of the third insulated gate bipolar transistor, a negative terminal of the third diode, a collector of the fourth insulated gate bipolar transistor, a negative terminal of the fourth diode, One end of a resistor is connected, the collector electrode of a second insulated gate bipolar transistor is respectively connected with the negative end of a first direct-current voltage source, the positive end of a second direct-current voltage source and the negative electrode of a second diode, the emitter electrode of the second insulated gate bipolar transistor is respectively connected with the positive electrode of a second diode, the emitter electrode of a third insulated gate bipolar transistor and the positive electrode of a third diode, the emitter electrode of a fourth insulated gate bipolar transistor is respectively connected with the negative end of the second direct-current voltage source and the positive electrode of a fourth diode, the other end of the resistor is connected with one end of a first inductor, the other ends of the inductors in the three-phase bridge arm circuits are connected together, and the gates of the first insulated gate bipolar transistor, the second insulated gate bipolar transistor, the third insulated gate bipolar transistor and the fourth insulated gate bipolar transistor are used for accessing the driving signal.
In FIG. 1, Sa1、Sa2、Sa3、Sa4Corresponding to a first insulated gate bipolar transistor, a second insulated gate bipolar transistor, a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the a-phase bridge arm circuit, Da1、Da2、Da3、Da4Corresponding to a first diode, a second diode, a third diode and a fourth diode in the a-phase bridge arm circuit, Ra、LaThe resistance and the inductance in the a-phase bridge arm circuit are correspondingly arranged; sb1、Sb2、Sb3、Sb4Corresponding to a first insulated gate bipolar transistor, a second insulated gate bipolar transistor, a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the b-phase bridge arm circuit, Db1、Db2、Db3、Db4Corresponding to a first diode, a second diode, a third diode and a fourth diode in the b-phase bridge arm circuit, Rb、LbThe resistance and the inductance in the b-phase bridge arm circuit are correspondingly arranged; sc1、Sc2、Sc3、Sc4Corresponding to a first insulated gate bipolar transistor, a second insulated gate bipolar transistor, a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the c-phase bridge arm circuit, Dc1、Dc2、Dc3、Dc4Corresponding to a first diode, a second diode, a third diode and a fourth diode in the c-phase bridge arm circuit, Rc、LcThe resistance and the inductance in the c-phase bridge arm circuit are correspondingly adopted.
Step 2: meanwhile, a high level or a low level is loaded on a first insulated gate bipolar transistor, a second insulated gate bipolar transistor, a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in a three-phase bridge arm circuit, so that the switching state is switched from "P" to "Z" when the phase current of the three-level T-type inverter is greater than 0, as shown in fig. 4a (taking a phase as an example in the drawing), the specific process is as follows: firstly, loading a high level to a first insulated gate bipolar transistor in a three-phase bridge arm circuit, and loading a low level to a second insulated gate bipolar transistor, a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, so that the switching state of the three-level T-type inverter is 'P', and at the moment, the phase current is greater than 0 and passes through the first insulated gate bipolar transistor, as shown in fig. 4b (taking a phase as an example in the drawing); then loading a high level to a first insulated gate bipolar transistor and a second insulated gate bipolar transistor in the three-phase bridge arm circuit, loading a low level to a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, wherein the duration is delta T2, so that the switching state of the three-level T-type inverter is still 'P', and at the moment, the phase current is greater than 0 and passes through the first insulated gate bipolar transistor, as shown in fig. 4c (taking phase a as an example); then loading a high level to a second insulated gate bipolar transistor in the three-phase bridge arm circuit, loading a low level to a first insulated gate bipolar transistor, a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, wherein the duration time is delta T1, switching the switching state of the three-level T-type inverter to be Z, and at the moment, the phase current is greater than 0 and passes through the second insulated gate bipolar transistor and a third diode, as shown in fig. 4d (taking a phase as an example); loading a high level to a second insulated gate bipolar transistor and a third insulated gate bipolar transistor in the three-phase bridge arm circuit, and loading a low level to a first insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, so that the switching state of the three-level T-type inverter is still Z, and at the moment, the phase current is greater than 0 and passes through the second insulated gate bipolar transistor and a third diode, as shown in fig. 4e (taking a phase as an example); as described above, Δ T1+ Δ T2 is the time for controlling the second igbt to turn on earlier. As can be seen from fig. 4b to 4e, no direct switching between the "P" switch state and the "N" switch state occurs during this transient. The timing of the drive signal for the fourth igbt is omitted in fig. 4a, since the fourth igbt is always in the off-state when the switching state is switched between the "P" switching state and the "Z" switching state when the phase current is greater than 0.
The b-phase and c-phase operate in the same manner as phase a, except that the drive signals for phase a and phase b differ in phase by 120 degrees and the drive signals for phase b and phase c differ in phase by 120 degrees.
And step 3: meanwhile, a high level or a low level is loaded on a first insulated gate bipolar transistor, a second insulated gate bipolar transistor, a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in a three-phase bridge arm circuit, so that the switching state is switched from "Z" to "P" when the phase current of the three-level T-type inverter is greater than 0, as shown in fig. 4f (taking a phase as an example in the drawing), the specific process is as follows: firstly, loading a high level to a second insulated gate bipolar transistor and a third insulated gate bipolar transistor in a three-phase bridge arm circuit, and loading a low level to a first insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, so that the switching state of the three-level T-type inverter is 'Z', and at the moment, the phase current is greater than 0 and passes through the second insulated gate bipolar transistor and a third diode, as shown in fig. 4g (taking a phase as an example); then loading a high level to a second insulated gate bipolar transistor in the three-phase bridge arm circuit, loading a low level to a first insulated gate bipolar transistor, a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, wherein the duration time is delta T1, so that the switching state of the three-level T-type inverter is still Z, and at the moment, the phase current is greater than 0 and passes through the second insulated gate bipolar transistor and a third diode, as shown in fig. 4h (taking a phase as an example); then loading a high level to a first insulated gate bipolar transistor and a second insulated gate bipolar transistor in the three-phase bridge arm circuit, loading a low level to a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, wherein the duration is delta T2, switching the switching state of the three-level T-type inverter to be 'P', and at the moment, the phase current is greater than 0 and passes through the first insulated gate bipolar transistor, as shown in fig. 4i (taking a phase as an example in the drawing); loading a high level to a first insulated gate bipolar transistor in the three-phase bridge arm circuit, and loading a low level to a second insulated gate bipolar transistor, a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, so that the switching state of the three-level T-type inverter is still 'P', and at the moment, the phase current is greater than 0 and passes through the first insulated gate bipolar transistor, as shown in fig. 4j (taking a phase as an example in the drawing); as described above, Δ T1+ Δ T2 is the time for controlling the delayed turn-off of the second igbt. As can be seen from fig. 4g to 4j, no direct switching between the "P" switch state and the "N" switch state occurs during this transient. The timing of the drive signal for the fourth igbt is omitted in fig. 4f, since the fourth igbt is always in the off-state when the switching state is switched between the "P" switching state and the "Z" switching state when the phase current is greater than 0.
The b-phase and c-phase operate in the same manner as phase a, except that the drive signals for phase a and phase b differ in phase by 120 degrees and the drive signals for phase b and phase c differ in phase by 120 degrees.
And 4, step 4: meanwhile, a high level or a low level is loaded on a first insulated gate bipolar transistor, a second insulated gate bipolar transistor, a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in a three-phase bridge arm circuit, so that the switching state is switched from "Z" to "N" when the phase current of the three-level T-type inverter is less than 0, as shown in fig. 5a (taking a phase as an example in the drawing), the specific process is as follows: loading high level to a second insulated gate bipolar transistor and a third insulated gate bipolar transistor in a three-phase bridge arm circuit, loading low level to a first insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit, enabling the switching state of the three-level T-type inverter to be Z, and enabling the phase current to be less than 0 and to pass through the third insulated gate bipolar transistor and a second diode; then loading a high level to a third insulated gate bipolar transistor in the three-phase bridge arm circuit, loading a low level to a first insulated gate bipolar transistor, a second insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, wherein the duration time is delta T1, so that the switching state of the three-level T-type inverter is still Z, and at the moment, the phase current is less than 0 and passes through the third insulated gate bipolar transistor and a second diode; loading a high level to a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit, loading a low level to a first insulated gate bipolar transistor and a second insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, wherein the duration time is delta T2, switching the switching state of the three-level T-type inverter to 'N', and at the moment, the phase current is less than 0 and passes through the fourth insulated gate bipolar transistor; loading a high level to a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit, and loading a low level to a first insulated gate bipolar transistor, a second insulated gate bipolar transistor and a third insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, so that the switching state of the three-level T-type inverter is still N, and at the moment, the phase current is less than 0 and passes through the fourth insulated gate bipolar transistor; in the above description, Δ T1+ Δ T2 is the time for controlling the delayed turn-off of the third igbt. It can be seen from the above that no direct switching between the "N" switch state and the "P" switch state occurs during this transient. The timing of the drive signal for the first igbt is omitted in fig. 5a, since the first igbt is always in the off-state when the switch state is switched between the "Z" switch state and the "N" switch state when the phase current is less than 0.
The b-phase and c-phase operate in the same manner as phase a, except that the drive signals for phase a and phase b differ in phase by 120 degrees and the drive signals for phase b and phase c differ in phase by 120 degrees.
And 5: meanwhile, a high level or a low level is loaded on a first insulated gate bipolar transistor, a second insulated gate bipolar transistor, a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in a three-phase bridge arm circuit, so that the switching state is switched from "N" to "Z" when the phase current of the three-level T-type inverter is less than 0, as shown in fig. 5b (taking a phase as an example in the drawing), the specific process is as follows: loading a high level to a fourth insulated gate bipolar transistor in a three-phase bridge arm circuit, and loading a low level to a first insulated gate bipolar transistor, a second insulated gate bipolar transistor and a third insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, so that the switching state of the three-level T-type inverter is N, and at the moment, the phase current is less than 0 and passes through the fourth insulated gate bipolar transistor; then loading high level to a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit, loading low level to a first insulated gate bipolar transistor and a second insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, wherein the duration time is delta T2, so that the switching state of the three-level T-type inverter is still N, and at the moment, the phase current is less than 0 and passes through the fourth insulated gate bipolar transistor; loading a high level to a third insulated gate bipolar transistor in the three-phase bridge arm circuit, loading a low level to a first insulated gate bipolar transistor, a second insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, wherein the duration time is delta T1, switching the switching state of the three-level T-type inverter to Z, and enabling the phase current to be less than 0 and to pass through the third insulated gate bipolar transistor and a second diode; and loading high level to a second insulated gate bipolar transistor and a third insulated gate bipolar transistor in the three-phase bridge arm circuit, loading low level to a first insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit, so that the switching state of the three-level T-type inverter is still Z, and at the moment, the phase current is less than 0 and passes through the third insulated gate bipolar transistor and a second diode. As described above, Δ T1+ Δ T2 is the time for controlling the third igbt to turn on earlier. It can be seen from the above that no direct switching between the "N" switch state and the "P" switch state occurs during this transient. The timing of the drive signal for the first igbt is omitted in fig. 5b, since the first igbt is always in the off-state when the switch state is switched between the "Z" switch state and the "N" switch state when the phase current is less than 0.
The b-phase and c-phase operate in the same manner as phase a, except that the drive signals for phase a and phase b differ in phase by 120 degrees and the drive signals for phase b and phase c differ in phase by 120 degrees.
The Δ T1 is the PWM dead time, and Δ T1 is 5 μ s and Δ T2 is 5 μ s.
In the above, FIG. 4a to FIG. 5b, Sa1First insulated gate bipolar transistor of a phase, Sa2Second insulated gate bipolar transistor of a phase, Sa3Third insulated gate bipolar transistor of a phase, Sa4And the fourth insulated gate bipolar transistor is a phase a.
In order to verify the feasibility and the effectiveness of the switch control method, the method is subjected to simulation verification.
Adopting PSIM software to simulate the direct-current voltage V of the direct-current voltage source in the main circuit of the three-level T-type inverter shown in the figure 1dcA resistor with a load of 8 ohms per phase is connected in series with an inductor of 20mH, set at 600V.
Take phase a as an example, and the phase current is greater than 0.
When the switching control strategy M1 is adopted, the simulation result is shown in fig. 6a, and the partial enlarged view between 25ms and 26ms is shown in fig. 6 b. In fig. 6a and 6b, the abscissa represents time in milliseconds, the ordinate represents voltage in volts, and the driving signals of 4 Insulated Gate Bipolar Transistors (IGBTs) of phase a and the bridge arm voltage v of phase a are respectively from top to bottomao. As can be seen from fig. 6b, when the device S is a semiconductor devicea1And a device Sa2When the bridge arms are conducted at the same time, the voltage v of the a-phase bridge armaoIs high, i.e. the switch state is "P"; when the device Sa2And a device Sa3When the bridge arms are conducted at the same time, the voltage v of the a-phase bridge armaoAt zero level, i.e., the switch state is "Z".
When the switching control strategy M2 is adopted, the simulation result is shown in FIG. 7a, and the partial enlarged view between 25ms and 26ms is shown in FIG. 7 b. In fig. 7a and 7b, the abscissa represents time in milliseconds, the ordinate represents voltage in volts, and the driving signals of 4 Insulated Gate Bipolar Transistors (IGBTs) of the a-phase and the a-phase arm voltage v are respectively the a-phase from top to bottomao. As can be seen from fig. 7b, when the device S is presenta1When conducting, the a-phase bridge arm voltage vaoAt a high level, i.e.The switch state is "P"; when the device Sa2And a device Sa3When the bridge arms are conducted at the same time, the voltage v of the a-phase bridge armaoAt zero level, i.e., the switch state is "Z". Furthermore, it can be seen that during the transient state of the switching between the "P" switch state and the "Z" switch state, an "N" switch state occurs.
When the method of the present invention is adopted, the simulation result is shown in fig. 8a, and the partial enlarged view between 25.5ms and 26ms is shown in fig. 8 b. In fig. 8a and 8b, the abscissa represents time in milliseconds, the ordinate represents voltage in volts, and the driving signals of 4 Insulated Gate Bipolar Transistors (IGBTs) of phase a and the bridge arm voltage v of phase a are respectively from top to bottomao. As can be seen from fig. 8b, during steady state, when the first igbt S for phase aa1When conducting, the a-phase bridge arm voltage vaoIs high, i.e. the switch state is "P"; second IGBT S of phase aa2And a-phase third insulated gate bipolar transistor Sa3When the bridge arms are conducted at the same time, the voltage v of the a-phase bridge armaoIs at zero level, i.e. the switch state is "Z"; during the transient state, the second insulated gate bipolar transistor S of the a phasea2Third insulated gate bipolar transistor S of phase aa3The switch is switched on in advance and the judgment is delayed, so that the 'N' switch state can not occur in the transient process of switching between the 'P' switch state and the 'Z' switch state, and the problem of the switch control strategy M2 is solved.

Claims (2)

1. A switch control method of a three-level T-type inverter is characterized by comprising the following steps:
step 1: building a three-level T-type inverter, wherein the three-level T-type inverter comprises a three-phase bridge arm circuit and two direct-current voltage sources, each phase of the bridge arm circuit consists of a first insulated gate bipolar transistor, a second insulated gate bipolar transistor, a third insulated gate bipolar transistor, a fourth insulated gate bipolar transistor, a first diode, a second diode, a third diode, a fourth diode, a resistor and an inductor, a collector electrode of the first insulated gate bipolar transistor is respectively connected with a positive electrode of a first direct-current voltage source and a negative electrode of the first diode, an emitter electrode of the first insulated gate bipolar transistor is respectively connected with a positive electrode of the first diode, a collector electrode of the third insulated gate bipolar transistor, a negative electrode of the third diode, a collector electrode of the fourth insulated gate bipolar transistor, a first diode, a second diode, a third diode, a fourth diode, a third diode and a fourth diode, The negative electrode of the fourth diode is connected with one end of the resistor, the collector of the second insulated gate bipolar transistor is respectively connected with the negative end of the first direct-current voltage source, the positive end of the second direct-current voltage source and the negative electrode of the second diode, the emitter of the second insulated gate bipolar transistor is respectively connected with the positive electrode of the second diode, the emitter of the third insulated gate bipolar transistor and the positive electrode of the third diode, the emitter of the fourth insulated gate bipolar transistor is respectively connected with the negative end of the second direct-current voltage source and the positive electrode of the fourth diode, the other end of the resistor is connected with one end of the inductor, the other ends of the inductors in the three-phase bridge arm circuits are connected together, the first insulated gate bipolar transistor, the second diode, the third diode and the fourth diode are connected together, the negative electrode of the first insulated gate bipolar transistor is connected with the negative electrode of the second direct-current voltage source, the emitter of the third diode is connected with the positive electrode of the third diode, the third diode is connected with the third diode, the third diode and the third diode are connected with the third diode, the third diode and the third diode are connected with the third diode, the third diode and the third diode, the third diode, The gate electrodes of the second insulated gate bipolar transistor, the third insulated gate bipolar transistor and the fourth insulated gate bipolar transistor are used for accessing a driving signal;
step 2: meanwhile, loading high level or low level to a first insulated gate bipolar transistor, a second insulated gate bipolar transistor, a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in a three-phase bridge arm circuit so as to realize that the switching state is switched from 'P' to 'Z' when the phase current of the three-level T-type inverter is greater than 0, wherein the specific process is as follows: loading a high level to a first insulated gate bipolar transistor in a three-phase bridge arm circuit, and loading a low level to a second insulated gate bipolar transistor, a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, so that the switching state of the three-level T-type inverter is P, and at the moment, the phase current is greater than 0 and passes through the first insulated gate bipolar transistor; then loading high level to a first insulated gate bipolar transistor and a second insulated gate bipolar transistor in the three-phase bridge arm circuit, loading low level to a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, wherein the duration time is delta T2, so that the switching state of the three-level T-type inverter is still P, and at the moment, the phase current is greater than 0 and passes through the first insulated gate bipolar transistor; loading a high level to a second insulated gate bipolar transistor in the three-phase bridge arm circuit, loading a low level to a first insulated gate bipolar transistor, a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, wherein the duration time is delta T1, switching the switching state of the three-level T-type inverter to Z, and enabling the phase current to be greater than 0 and to pass through the second insulated gate bipolar transistor and a third diode; loading high level to a second insulated gate bipolar transistor and a third insulated gate bipolar transistor in the three-phase bridge arm circuit, loading low level to a first insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit, enabling the switching state of the three-level T-type inverter to be still Z, and enabling the phase current to be larger than 0 and to pass through the second insulated gate bipolar transistor and a third diode at the moment;
and step 3: meanwhile, loading high level or low level to a first insulated gate bipolar transistor, a second insulated gate bipolar transistor, a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in a three-phase bridge arm circuit so as to realize that the switching state is switched from 'Z' to 'P' when the phase current of the three-level T-type inverter is greater than 0, wherein the specific process is as follows: loading high level to a second insulated gate bipolar transistor and a third insulated gate bipolar transistor in a three-phase bridge arm circuit, loading low level to a first insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit, enabling the switching state of the three-level T-type inverter to be Z, and enabling the phase current to be greater than 0 and to pass through the second insulated gate bipolar transistor and a third diode; then loading a high level to a second insulated gate bipolar transistor in the three-phase bridge arm circuit, loading a low level to a first insulated gate bipolar transistor, a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, wherein the duration time is delta T1, so that the switching state of the three-level T-type inverter is still Z, and at the moment, the phase current is greater than 0 and passes through the second insulated gate bipolar transistor and a third diode; loading high level to a first insulated gate bipolar transistor and a second insulated gate bipolar transistor in the three-phase bridge arm circuit, loading low level to a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, wherein the duration time is delta T2, switching the switching state of the three-level T-type inverter to be P, and enabling the phase current to be larger than 0 and to pass through the first insulated gate bipolar transistor; loading a high level to a first insulated gate bipolar transistor in the three-phase bridge arm circuit, and loading a low level to a second insulated gate bipolar transistor, a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, so that the switching state of the three-level T-type inverter is still P, and at the moment, the phase current is greater than 0 and passes through the first insulated gate bipolar transistor;
and 4, step 4: meanwhile, loading high level or low level to a first insulated gate bipolar transistor, a second insulated gate bipolar transistor, a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in a three-phase bridge arm circuit so as to realize that the switching state is switched from 'Z' to 'N' when the phase current of the three-level T-type inverter is less than 0, wherein the specific process is as follows: loading high level to a second insulated gate bipolar transistor and a third insulated gate bipolar transistor in a three-phase bridge arm circuit, loading low level to a first insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit, enabling the switching state of the three-level T-type inverter to be Z, and enabling the phase current to be less than 0 and to pass through the third insulated gate bipolar transistor and a second diode; then loading a high level to a third insulated gate bipolar transistor in the three-phase bridge arm circuit, loading a low level to a first insulated gate bipolar transistor, a second insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, wherein the duration time is delta T1, so that the switching state of the three-level T-type inverter is still Z, and at the moment, the phase current is less than 0 and passes through the third insulated gate bipolar transistor and a second diode; loading a high level to a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit, loading a low level to a first insulated gate bipolar transistor and a second insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, wherein the duration time is delta T2, switching the switching state of the three-level T-type inverter to 'N', and at the moment, the phase current is less than 0 and passes through the fourth insulated gate bipolar transistor; loading a high level to a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit, and loading a low level to a first insulated gate bipolar transistor, a second insulated gate bipolar transistor and a third insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, so that the switching state of the three-level T-type inverter is still N, and at the moment, the phase current is less than 0 and passes through the fourth insulated gate bipolar transistor;
and 5: meanwhile, loading high level or low level to a first insulated gate bipolar transistor, a second insulated gate bipolar transistor, a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in a three-phase bridge arm circuit so as to realize that the switching state is switched from 'N' to 'Z' when the phase current of the three-level T-type inverter is less than 0, and the specific process is as follows: loading a high level to a fourth insulated gate bipolar transistor in a three-phase bridge arm circuit, and loading a low level to a first insulated gate bipolar transistor, a second insulated gate bipolar transistor and a third insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, so that the switching state of the three-level T-type inverter is N, and at the moment, the phase current is less than 0 and passes through the fourth insulated gate bipolar transistor; then loading high level to a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit, loading low level to a first insulated gate bipolar transistor and a second insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, wherein the duration time is delta T2, so that the switching state of the three-level T-type inverter is still N, and at the moment, the phase current is less than 0 and passes through the fourth insulated gate bipolar transistor; loading a high level to a third insulated gate bipolar transistor in the three-phase bridge arm circuit, loading a low level to a first insulated gate bipolar transistor, a second insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit at the same time, wherein the duration time is delta T1, switching the switching state of the three-level T-type inverter to Z, and enabling the phase current to be less than 0 and to pass through the third insulated gate bipolar transistor and a second diode; and loading high level to a second insulated gate bipolar transistor and a third insulated gate bipolar transistor in the three-phase bridge arm circuit, loading low level to a first insulated gate bipolar transistor and a fourth insulated gate bipolar transistor in the three-phase bridge arm circuit, so that the switching state of the three-level T-type inverter is still Z, and at the moment, the phase current is less than 0 and passes through the third insulated gate bipolar transistor and a second diode.
2. The switching control method of the three-level T-type inverter as claimed in claim 1, wherein Δ T1 is PWM dead time, Δ T1 ═ 5 μ s, and Δ T2 ═ 5 μ s.
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