CN105185789A - Fabrication method of array substrate, array substrate and liquid crystal display device - Google Patents
Fabrication method of array substrate, array substrate and liquid crystal display device Download PDFInfo
- Publication number
- CN105185789A CN105185789A CN201510563586.7A CN201510563586A CN105185789A CN 105185789 A CN105185789 A CN 105185789A CN 201510563586 A CN201510563586 A CN 201510563586A CN 105185789 A CN105185789 A CN 105185789A
- Authority
- CN
- China
- Prior art keywords
- electrode layer
- common electrode
- layer
- array base
- base palte
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Liquid Crystal (AREA)
Abstract
The invention provides a fabrication method of an array substrate. The method comprises the following steps of: forming a grid metal layer on a substrate; forming an active layer on the grid metal layer; forming a source-drain metal layer on the active layer; forming a first insulation layer on the source-drain metal layer; forming a pixel electrode layer on the insulation layer; and forming a second insulation layer on the pixel electrode layer and forming a first partial common electrode layer and a second partial common electrode layer on the second insulation layer, wherein the first partial common electrode layer and the second partial common electrode layer arranged at positions corresponding to data lines and arranged above the data lines in a strip manner, and the material of the first partial common electrode layer is metal. The invention also provides the array substrate fabricated according to the above method and a liquid crystal display device containing the array substrate. The fabrication method of the array substrate, the array substrate and the liquid crystal display device, provided by the invention, have the advantages of high yield, high light transmittance and difficulty in light leakage.
Description
Technical field
The present invention relates to Display Technique field, particularly a kind of array base palte manufacture method, by the manufacture method manufacture of this array base palte array base palte and comprise the liquid crystal indicator of this array base palte.
Background technology
Liquid crystal indicator (LiquidCrystalDisplay, LCD) possesses the plurality of advantages such as frivolous, energy-conservation, radiationless, has therefore replaced traditional cathode ray tube (CRT) display gradually.Current liquid crystal display is widely used in the electronic equipments such as HD digital TV, desktop computer, personal digital assistant (PDA), notebook computer, mobile phone, digital camera.
Common liquid crystal indicator can be divided into the twisted nematic (TwistedNematic at narrow visual angle, TN) liquid crystal indicator, super-twist nematic (SuperTwistedNematic, STN) liquid crystal indicator, double-layer super-twist nematic (Double-layerSuperTwistedNematic, DSTN) the fringe field switching technology (FringeFieldSwitching of liquid crystal indicator and wide viewing angle, FFS) liquid crystal indicator, plane conversion (In-PlaneSwitching, IPS) liquid crystal indicator and vertical orientation technology (VerticalAlignment, VA) liquid crystal indicator.Wherein, IPS type liquid crystal indicator is widely used in display device due to various advantages such as its visible angle are large, real colour, picture are outstanding.
Along with the resolution of IPS type liquid crystal indicator is more and more higher, the pixel on the panel of IPS type liquid crystal indicator is more and more intensive, then red (Red.R) sub-pixel, green (Green, G) sub-pixel and blueness (Blue, the width of the black matrix" (BlackMatrix, BM) B) arranged between sub-pixel will reduce, and BM width reduces easily to cause liquid crystal indicator generation light leakage phenomena.In addition, in the process that array base palte and colored filter substrate group stand, if the side-play amount MA between array base palte and colored filter substrate is excessive, also can there is light leakage phenomena in liquid crystal indicator.
At present, in order to prevent the light leakage phenomena of liquid crystal indicator in prior art, widen the width of BM on the one hand, be on the other hand stand in process at array base palte and colored filter substrate group to set board running parameter, make side-play amount between array base palte and colored filter substrate in limited range.But the width widening BM declines by causing the light transmittance of liquid crystal indicator to, affect picture display, in addition, stand in process in the group of array base palte and colored filter substrate and set tool parameters, reliability is low, the bad product of easy generation, reduces the yield of product.
Therefore, be necessary to provide the technical scheme of improvement to overcome the above technical problem existed in prior art.
Summary of the invention
In view of above problem, the invention provides that a kind of yield is high, light transmittance is high and the array base palte of not easily light leak.
The invention provides a kind of manufacture method of array base palte, described method comprises step: in substrate, form gate metal layer; Described gate metal layer is formed with active layer; Described active layer is formed source-drain electrodes metal level; Described source-drain electrodes metal level forms the first insulating barrier; Described insulating barrier forms pixel electrode layer; Described pixel electrode layer is formed the second insulating barrier and form Part I common electrode layer and Part II common electrode layer on described second insulating barrier, wherein, described Part I common electrode layer is arranged corresponding to the position of data wire, and the top of data wire is positioned in strip, the material of described Part I common electrode layer is metal.
The present invention also provides a kind of array base palte manufactured by said method, and described array base palte comprises substrate, is arranged on described suprabasil gate metal layer, the active layer be arranged in described gate metal layer, the source-drain electrodes metal level arranged on described active layer, the first insulating barrier be arranged on described source-drain electrodes metal level, the pixel electrode layer be arranged on described first insulating barrier, be arranged on the second insulating barrier on described pixel electrode layer and the Part I common electrode layer be arranged on described second insulating barrier and Part II common electrode layer.Wherein, described Part I common electrode layer is arranged corresponding to the position of data wire, and is positioned at above data wire in strip, and the material of described Part I common electrode layer is metal.
The present invention also provides a kind of liquid crystal indicator comprising above-mentioned array base palte.
The manufacture method of array base palte of the present invention, public electrode on array base palte is divided into Part I common electrode layer and Part II common electrode layer by the array base palte manufactured by the method and the liquid crystal display comprising this array base palte, and Part I common electrode layer is positioned at the top of data wire, in addition, the material of Part I common electrode layer is metal molybdenum, due to the opaqueness of metal molybdenum, the Part I common electrode layer of side is equivalent to black matrix" on the data line, and then make array base palte not easily produce light leakage phenomena, and then improve the yield of product, in addition, corresponding to the black matrix" of linear position data can be suitable reduction width thus improve the light transmittance of product.
Accompanying drawing explanation
The steps flow chart schematic diagram of the manufacture method of the array base palte that Fig. 1 provides for one embodiment of the invention.
The planar structure schematic diagram of array base palte of Fig. 2 for inventing an embodiment and providing.
The cross-sectional view of the liquid crystal indicator that Fig. 3 provides for one embodiment of the invention.
Embodiment
For further setting forth the present invention for the technological means reaching predetermined goal of the invention and take and effect, below in conjunction with accompanying drawing and preferred embodiment, to the manufacture method of array base palte proposed according to the present invention, array base palte and its embodiment of liquid crystal indicator, method, step, structure, feature and effect, be described in detail as follows.
Aforementioned and other technology contents, feature and effect for the present invention, can clearly present in the detailed description of following cooperation with reference to graphic preferred embodiment.By the explanation of embodiment, when can to the present invention for the technological means reaching predetermined object and take and effect be able to more deeply and concrete understanding, however institute's accompanying drawings be only to provide with reference to and the use of explanation, be not used for being limited the present invention.
Please refer to Fig. 1, the steps flow chart schematic diagram of the manufacture method of the array base palte that Fig. 1 provides for one embodiment of the invention.As shown in Figure 1, the manufacture method of array base palte of the present invention comprises step:
S11: form gate metal layer in substrate;
In this step, first need first to clean substrate, the main purpose of cleaning removes the pollutants such as the organic substance of substrate surface, metallic particles and dust.The method that cleaning adopts is mainly dry clean method and wet-cleaned method, and dry clean method mainly contains ultraviolet cleaning, infrared ray cleaning and plasma cleaning etc., and what General Production Lines was conventional is ultraviolet cleaning method; Wet-cleaned method mainly contains the method for scrubbing, ultrasonic method, high-pressure spraying method, the cleaning of pure water/air two fluid and liquid ablution, generally integrated used in combination in production line cleaning machine.In addition, it should be noted that cleaning process needs to carry out drying process to substrate surface after completing.
Further, substrate after the drying adopts spatter film forming method form the first metal layer, wherein, main direct current and the radio-frequency alternating current of adopting drives magnetron sputtering.Four parameters are mainly contained on quality of forming film impact is larger: film-forming temperature, film forming gas pressure, reaction chamber vacuum degree and magnetic field intensity and distribution thereof in spatter film forming process.Film-forming temperature is higher, and the film quality of formation is finer and close, and resistance to chemical attack ability is stronger, and specific impedance is less; When film forming gas pressure is low, the dense micro-structure of sputtered film, defect is few, and during film forming gas pressure height, the film quality of sputtered film is loose, defect is many; In addition, if there is foreign gas to exist in reaction chamber, film quality and film forming speed can be had a strong impact on, and the uneven meeting of Distribution of Magnetic Field causes film forming uneven.It should be noted that, in the present embodiment, substrate is glass material.
Further, complete and after uniform the first metal layer, the gate metal layer with target pattern can be formed by mask processing procedure in substrate when forming one whole at substrate surface.Particularly, at the first metal layer surface coating photoresistance liquid, and then figuratum mask plate at quarter is placed on the top of substrate and is exposed substrate by mask plate, the process such as development are to be dissolved in developer solution by the photoresistance liquid be exposed under ultraviolet, then will through overexposure, substrate after development is put into metal etch liquid and is carried out being etched with the first metal layer of removal substrate surface through development treatment, finally stripping process is carried out to the substrate after etching, particularly to photoresistance liquid surface instillation organic solution, this organic solution and photoresistance liquid generation chemical reaction are to remove the photoresistance liquid on the first metal layer surface, and then formation gate metal layer.It should be noted that, the material of gate metal layer can be the one in the metals such as aluminium, molybdenum, chromium, nickel, in addition, it should be noted that, photoresistance liquid in the present embodiment is positivity photoresistance, but it will be appreciated by those skilled in the art that, the photoresistance liquid in the present embodiment also can be negativity photoresistance.
S12: be formed with active layer in gate metal layer;
In this step, complete uniform amorphous silicon (a-Si) film need be formed at substrate surface after forming gate metal layer in step S11.In the present embodiment, chemical vapour deposition technique (PlasmaEnhancedChemicalVaporDeposition can be strengthened by using plasma, PECVD), high-density plasma vapour deposition process (HighDensityChemicalVaporDeposition, HDPCVD), the method such as metal organic vapor phase epitaxy method (Metallo-organicChemicalVaporDeposition, MOCVD) deposition film forming.
After amorphous silicon membrane is formed, can adopt the mask processing procedure as described in step S11 in gate metal layer, form the active layer with target pattern, this active layer belongs to semiconductor medium, and it is for transmission electronic, and this active layer is positioned in gate metal layer.Mask processing procedure in this step is similar to the mask processing procedure in step S11, detailed process can associated description in refer step S11, so place repeats no more, it should be noted that, in the mask processing procedure in this step and step S11, mask processing procedure distinguishes the etching solution that part is to adopt in etching process is film etching liquid.
S13: form source-drain electrodes metal level on active layer;
In this step, after step S12 is formed with active layer, the method of spatter film forming can be adopted to form the second metal level at substrate surface, after form complete uniform second metal level at substrate surface, adopt mask processing procedure to form the source-drain electrodes metal level with target pattern.In this step, mask processing procedure is adopted to form the concrete mask processing procedure of source-drain electrodes metal level identical with the mask processing procedure in step S11, specifically can the associated description of refer step S11, so place repeats no more.
S14: form the first insulating barrier on source-drain electrodes metal level;
In this step, the methods such as chemical vapour deposition technique, high-density plasma vapour deposition process, metal organic vapor phase epitaxy method can be strengthened on source-drain electrodes metal level, deposit film forming to form the first insulating barrier by using plasma after step S13 forms source-drain electrodes metal level.
S15: form pixel electrode layer on the first insulating barrier;
In this step, the method such as chemical vapour deposition technique, high-density plasma vapour deposition process, metal organic vapor phase epitaxy method can be strengthened on the first insulating barrier, deposit film forming by using plasma after step S14 forms the first insulating barrier.Further, after formed uniform film on the first insulating barrier, need to adopt mask processing procedure to form the pixel electrode layer with target pattern, this pixel electrode layer is planar distribution, and pixel electrode material is tin indium oxide (Indiumtinoxide, ITO) film.Mask processing procedure in this step is similar to the mask processing procedure in step S11, detailed process can associated description in refer step S11, so place repeats no more, it should be noted that, in the mask processing procedure in this step and step S11, mask processing procedure distinguishes the etching solution that part is to adopt in etching process is film etching liquid.
S16: form the second insulating barrier on pixel electrode layer;
In this step, the methods such as chemical vapour deposition technique, high-density plasma vapour deposition process, metal organic vapor phase epitaxy method can be strengthened on pixel electrode layer, deposit film forming to form the second insulating barrier by using plasma when step S15 is formed after pixel electrode layer.
S17: form Part I common electrode layer and Part II common electrode layer over the second dielectric, wherein, Part I common electrode layer is arranged corresponding to the position of data wire, and is positioned at the top of data wire in strip, and the material of Part I common electrode layer is metal;
In this step, after forming the second insulating barrier in step s 16, spatter film forming method first can be adopted to form a complete uniform metal level at the second surface of insulating layer, and then adopt mask processing procedure to form the Part I common electrode layer with target pattern over the second dielectric.In the present embodiment, Part I common electrode layer is arranged corresponding to the position of data wire, and the top of data wire is positioned in strip, in addition, the width of Part I service message machine layer is greater than the width of data wire, that is, the every bar service message in Part I common electrode layer is cover data line extremely completely.It should be noted that, the concrete mask processing procedure that this step is formed by mask processing procedure formation Part I common electrode layer is identical with the mask processing procedure in step S11, specifically can the associated description of refer step S11, so place repeats no more, in addition, the material of Part I common electrode layer is metal molybdenum, certainly it will be understood by those skilled in the art that, the material of Part I common layer also can be other metals, such as aluminium, chromium, nickel etc.In the present embodiment, because the impedance of metal molybdenum is far smaller than ITO, therefore, when after the energising of Part I public electrode, material impedance is less on public electrode voltages Vcom impact, and then provides the consistency of common electric voltage Vcom.
When after formation Part I common electrode layer, the method such as chemical vapour deposition technique, high-density plasma vapour deposition process, metal organic vapor phase epitaxy method can be strengthened deposit complete uniform film over the second dielectric by using plasma, and adopt mask processing procedure to form the Part II common electrode layer with target pattern.In the present embodiment, Part II common electrode layer is positioned at pixel cell, and is that strip distributes over the second dielectric along the direction parallel with described data wire.
Please refer to Fig. 2, the planar structure schematic diagram of array base palte of Fig. 2 for inventing an embodiment and providing.As shown in Figure 2, it is (not shown that array base palte of the present invention comprises substrate 100, please refer to Fig. 3), be arranged on the gate metal layer 101 in substrate 100, be arranged on the active layer (not shown) in gate metal layer 101, be arranged on the source-drain electrodes metal level 102 on active layer, be arranged on the first insulating barrier (not shown) on source-drain electrodes metal level 102, be arranged on the pixel electrode layer 103 on the first insulating barrier, the second insulating barrier 107 be arranged on pixel electrode layer 103 is (not shown, please refer to Fig. 3) and be arranged on Part I common electrode layer on the second insulating barrier 107 104 and Part II common electrode layer 105.Wherein, Part I common electrode layer 104 is arranged corresponding to the position of data wire 106, and is positioned at above data wire 106 in strip, and the width of every bar Part I common electrode layer 104 is greater than the width of every bar data wire 106, in addition, the material of Part I common electrode layer 104 is metal.It should be noted that, in the present embodiment array base palte can be formed by the method manufacture described in embodiment one, specifically can the detailed description of reference example one, repeat no more herein.
In one embodiment of this invention, the material of Part I common electrode layer 104 is metal molybdenum.
In one embodiment of this invention, Part II common electrode layer 105 is that strip is distributed on pixel electrode layer 103 along the direction parallel with data wire 106.
In one embodiment of this invention, the first insulating barrier is provided with via, via is used for conducting source-drain electrodes metal level 102 and pixel electrode layer 103.
Please refer to Fig. 3, the cross-sectional view of the liquid crystal indicator that Fig. 3 provides for one embodiment of the invention.As shown in Figure 3, liquid crystal indicator of the present invention comprises array base palte 10, colored filter substrate 20 and the liquid crystal layer between array base palte 10 and colored filter substrate 20 30 as described in Figure 2.Wherein, colored filter substrate 20 comprises substrate 200, setting colored filter (not shown) on a substrate 200 and the public electrode 201 be arranged on colored filter.
Further, the pixel electrode 103 that array base palte 10 comprises substrate 100, arrange in substrate 100 with data wire 106, be arranged on data wire 106 and the second insulating barrier 107 on pixel electrode 103 and the Part I common electrode layer 104 be arranged on the second insulating barrier 107 and Part II common electrode layer 105, and Part I common electrode layer 104 is arranged corresponding to the position of this data wire 106, and the width of every bar Part I common electrode layer 104 is greater than the width of every bar data wire 106.It should be noted that, the array base palte in the liquid crystal indicator in the present embodiment is the array base palte described in embodiment two, specifically can the detailed description of reference example two, repeats no more herein.
The manufacture method of array base palte of the present invention, public electrode on array base palte 10 is divided into Part I public electrode 104 layers and Part II common electrode layer 105 by the array base palte manufactured by the method and the liquid crystal display comprising this array base palte, and Part I common electrode layer 104 is positioned at the top of data wire 106, in addition, the material of Part I common electrode layer 104 is metal molybdenum, due to the opaqueness of metal molybdenum, the Part I public electrode 104 of side is equivalent to black matrix" on the data line, and then make array base palte 10 not easily produce light leakage phenomena, and then improve the yield of product, in addition, corresponding to the black matrix" of data wire 106 position can be suitable reduction width thus improve the light transmittance of product.
The above, it is only preferred embodiment of the present invention, not any pro forma restriction is done to the present invention, although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, make a little change when the technology contents of above-mentioned announcement can be utilized or be modified to the Equivalent embodiments of equivalent variations, in every case be do not depart from technical solution of the present invention content, according to any simple modification that technical spirit of the present invention is done above embodiment, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (10)
1. a manufacture method for array base palte, is characterized in that, described method comprises step:
Substrate forms gate metal layer;
Described gate metal layer is formed with active layer;
Described active layer is formed source-drain electrodes metal level;
Described source-drain electrodes metal level forms the first insulating barrier;
Described first insulating barrier forms pixel electrode layer;
Described pixel electrode layer is formed the second insulating barrier; And
Described second insulating barrier is formed Part I common electrode layer and Part II common electrode layer, wherein, described Part I common electrode layer is arranged corresponding to the position of data wire, and is positioned at the top of data wire in strip, and the material of described Part I common electrode layer is metal.
2. the manufacture method of array base palte according to claim 1, is characterized in that, the material of described Part I common electrode layer is metal molybdenum.
3. the manufacture method of array base palte according to claim 1, is characterized in that, the width of described Part I common electrode layer is greater than the width of described data wire.
4. the manufacture method of array base palte according to claim 1, is characterized in that, described Part II common electrode layer is that strip is distributed on described pixel electrode layer along the direction parallel with described data wire.
5. the manufacture method of array base palte according to claim 1, is characterized in that, described first insulating barrier is provided with via, and described via is used for source-drain electrodes metal level and described pixel electrode layer described in conducting.
6. an array base palte, is characterized in that, described array base palte comprises:
Substrate;
Be arranged on described suprabasil gate metal layer;
Be arranged on the active layer in described gate metal layer;
Source-drain electrodes metal level on described active layer is set;
Be arranged on the first insulating barrier on described source-drain electrodes metal level;
Be arranged on the pixel electrode layer on described first insulating barrier;
Be arranged on the second insulating barrier on described pixel electrode layer; And
Be arranged on the Part I common electrode layer on described second insulating barrier and Part II common electrode layer;
Wherein, described Part I common electrode layer is arranged corresponding to the position of data wire, and is positioned at above data wire in strip, and the material of described Part I common electrode layer is metal.
7. array base palte according to claim 6, is characterized in that, the material of described Part I common electrode layer is metal molybdenum.
8. array base palte according to claim 6, is characterized in that, described Part II common electrode layer is that strip is distributed on described pixel electrode layer along the direction parallel with described data wire.
9. array base palte according to claim 6, is characterized in that, described first insulating barrier is provided with via, and described via is used for source-drain electrodes metal level and described pixel electrode layer described in conducting.
10. a liquid crystal indicator, is characterized in that, described liquid crystal indicator comprises the array base palte as described in any one of claim 6 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510563586.7A CN105185789A (en) | 2015-09-07 | 2015-09-07 | Fabrication method of array substrate, array substrate and liquid crystal display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510563586.7A CN105185789A (en) | 2015-09-07 | 2015-09-07 | Fabrication method of array substrate, array substrate and liquid crystal display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105185789A true CN105185789A (en) | 2015-12-23 |
Family
ID=54907772
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510563586.7A Pending CN105185789A (en) | 2015-09-07 | 2015-09-07 | Fabrication method of array substrate, array substrate and liquid crystal display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105185789A (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101097333A (en) * | 2006-06-30 | 2008-01-02 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and method for fabricating the same |
| CN101241278A (en) * | 2007-02-05 | 2008-08-13 | 京东方显示器科技公司 | Fringe field switching mode liquid crystal display device |
| CN101738792A (en) * | 2008-11-21 | 2010-06-16 | 索尼株式会社 | Display device, method for driving display device and electronic device |
| CN102116981A (en) * | 2009-12-30 | 2011-07-06 | 乐金显示有限公司 | Thin film transistor array substrate and method for fabricating the same |
| CN102645808A (en) * | 2012-04-20 | 2012-08-22 | 京东方科技集团股份有限公司 | Manufacture method of array substrate, array substrate and display device |
| CN103311253A (en) * | 2012-12-24 | 2013-09-18 | 上海中航光电子有限公司 | Thin film transistor array substrate and manufacturing method thereof and liquid crystal display device |
| CN203883006U (en) * | 2014-06-12 | 2014-10-15 | 京东方科技集团股份有限公司 | Array substrate and display device |
-
2015
- 2015-09-07 CN CN201510563586.7A patent/CN105185789A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101097333A (en) * | 2006-06-30 | 2008-01-02 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and method for fabricating the same |
| CN101241278A (en) * | 2007-02-05 | 2008-08-13 | 京东方显示器科技公司 | Fringe field switching mode liquid crystal display device |
| CN101738792A (en) * | 2008-11-21 | 2010-06-16 | 索尼株式会社 | Display device, method for driving display device and electronic device |
| CN102116981A (en) * | 2009-12-30 | 2011-07-06 | 乐金显示有限公司 | Thin film transistor array substrate and method for fabricating the same |
| CN102645808A (en) * | 2012-04-20 | 2012-08-22 | 京东方科技集团股份有限公司 | Manufacture method of array substrate, array substrate and display device |
| CN103311253A (en) * | 2012-12-24 | 2013-09-18 | 上海中航光电子有限公司 | Thin film transistor array substrate and manufacturing method thereof and liquid crystal display device |
| CN203883006U (en) * | 2014-06-12 | 2014-10-15 | 京东方科技集团股份有限公司 | Array substrate and display device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103676376B (en) | Array base palte and preparation method thereof and apply the display panels of this array base palte | |
| CN102881688B (en) | Array substrate, display panel and array substrate manufacturing method | |
| CN103117285B (en) | The manufacture method of a kind of array base palte, display unit and array base palte | |
| CN102736325B (en) | A kind of dot structure and manufacture method, display device | |
| CN106094366B (en) | The production method and IPS type array substrate of IPS type array substrate | |
| US20140168585A1 (en) | Color filter substrate, manfacturing method for the same, and display device | |
| CN103885221B (en) | Large board electrified circuit and manufacturing method of large board electrified circuit | |
| CN105093750A (en) | TFT array substrate structure and manufacturing method thereof | |
| CN105514032A (en) | Manufacturing method of IPS (In-Plane Switching) type TFT-LCD (Thin Film Transistor-Liquid Crystal Display) array substrate and IPS type TFT-LCD array substrate | |
| CN102723308B (en) | Array substrate, manufacturing method thereof and display device | |
| CN104898318A (en) | IPS-type In Cell touch display panel and manufacturing method | |
| CN102998856A (en) | Array substrate, as well as manufacture method and display device thereof | |
| US10403761B2 (en) | Array substrate and manufacturing method thereof, and display device | |
| CN104965324B (en) | The manufacturing method of liquid crystal display device | |
| CN105068340B (en) | Array substrate, display device and preparation method thereof | |
| CN103413782A (en) | Array substrate, method for manufacturing array substrate and display panel | |
| CN101666949B (en) | IPS type TFT-LCD array substrate and manufacturing method thereof | |
| US9778512B2 (en) | Array substrate having spacer, method for manufacturing the same, and display panel | |
| CN104020621A (en) | Array substrate and preparation method thereof and display device | |
| CN102707832A (en) | Method for manufacturing touch screen display, touch screen display and terminal | |
| CN102629587A (en) | Array substrate and manufacturing method thereof and display device | |
| CN103021943B (en) | Array substrate, manufacture method of array substrate and display device | |
| CN102945827A (en) | Array substrate and manufacturing method thereof | |
| CN102799038B (en) | Array substrate, display device and method for producing array substrate | |
| CN105185789A (en) | Fabrication method of array substrate, array substrate and liquid crystal display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20151223 |
|
| RJ01 | Rejection of invention patent application after publication |