CN105185761A - Porpezite IC packaging projection - Google Patents
Porpezite IC packaging projection Download PDFInfo
- Publication number
- CN105185761A CN105185761A CN201510537870.7A CN201510537870A CN105185761A CN 105185761 A CN105185761 A CN 105185761A CN 201510537870 A CN201510537870 A CN 201510537870A CN 105185761 A CN105185761 A CN 105185761A
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- Prior art keywords
- layer
- porpezite
- gold
- buffer block
- conductive layer
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a porpezite IC packaging projection, comprising a carrier, a conductive layer, an insulating layer, a titanium tungsten layer, a first gold layer, a palladium layer, and a second gold layer arranged from bottom to top in sequence. The insulating layer is provided with holes to expose part of the conductive layer. The surface of the part of the conductive layer is at least provided with a stress buffer block. The stress buffer block is a polyethylene product. The titanium tungsten layer is abutted against part of the conductive layer, the stress buffer block, and the surface of the insulating layer, and is in a wavy shape. The first gold layer, the palladium layer, and the gold layers are in wavy shape. The stress buffer block can absorb stress between the titanium tungsten layer and part of the conductive layer, and also makes each metal layer in a wavy shape. When temperature changes, each metal layer moves laterally, so as to reduce stress between adjacent metal layers, and weaken negative influence generated by stress and improve reliability of the porpezite IC packaging projection.
Description
Technical field
The present invention relates to IC encapsulation field, be specifically related to a kind of porpezite IC encapsulating lug.
Background technology
The upper projection used of drive IC encapsulation is commonly proof gold, cost is high, the combination of a kind of employing copper nickel gold is had to replace pure gold IC encapsulating lug at present, can effectively reduce costs, in view of the cost of gold, layer gold on nickel dam has 3um thick, the connectivity of crossing is spattered fair in short time, as excessively of a specified duration in wet environment, through the thin hole of layer gold, nickel dam oxide etch can be made, and then cause layer gold surface gradually to lose connectivity, and the reducing agent phosphorus often contained in nickel dam, boron decline causing the cohesive force of nickel dam and layer gold, performance reliability is low; Porpezite IC encapsulating lug a kind ofly utilizes the advantage that palladium is anti-corrosion, wear-resisting, discoloration-resistant is good, chemical stability is high, guarantee cohesive force between layer gold, to overcome the defect of copper nickel gold IC encapsulating lug, but because the coefficient of expansion of different metal is different, when variations in temperature, between each metal level, produce stress, be easy to cause matrix be out of shape or crack, even can peel off and come off, therefore also there is the low problem of reliability in this porpezite IC encapsulating lug.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of porpezite IC encapsulating lug, existing porpezite IC encapsulating lug can be solved when variations in temperature, between each metal level, produce stress, be easy to cause matrix be out of shape or crack, even can peel off and come off, cause the problem of poor reliability.
The present invention is achieved through the following technical solutions:
A kind of porpezite IC encapsulating lug, comprise the carrier, conductive layer, insulating barrier, titanium tungsten layer, the first layer gold, palladium layers and the second layer gold that set gradually from bottom to top, described insulating barrier is provided with hole, exposed portion conductive layer, the surface of described partial electroconductive layer is at least provided with a stress buffer block, described stress buffer block is polyethylene products, the surperficial waviness of described titanium tungsten layer fitting part conductive layer, stress buffer block and insulating barrier, described first layer gold, palladium layers and the second layer gold also waviness.
Further scheme of the present invention is, described carrier is silicon chip.
Further scheme of the present invention is, described conductive layer is aluminium pad.
Further scheme of the present invention is, described insulating barrier is PSV insulating material.
Further scheme of the present invention is that described stress buffer block is uniformly distributed in the surface of partial electroconductive layer.
The present invention's advantage is compared with prior art:
Stress buffer block can absorb the stress between titanium tungsten layer and partial electroconductive layer on the one hand, make each metal level waviness on the other hand, reduce the lateral displacement of each metal level during variations in temperature, thus the stress between reduction adjacent metal, and then weaken the negative effect of stress generation, improve the reliability of porpezite IC encapsulating lug.
Accompanying drawing explanation
Fig. 1 is structural representation of the present invention.
Embodiment
A kind of porpezite IC encapsulating lug as shown in Figure 1, comprise the silicon chip carrier 1 set gradually from bottom to top, aluminium pad conductive layer 2, PSV insulating barrier 3, titanium tungsten layer 4, first layer gold 5, palladium layers 6 and the second layer gold 7, described insulating barrier 3 is provided with hole, exposed portion conductive layer 21, the surface uniform sputter of described partial electroconductive layer 21 has at least one polyethylene stress buffer block 9, the cross section of described polyethylene stress buffer block 9 can be rectangle, triangle or arc, described titanium tungsten layer 4 fitting part conductive layer 21, the surperficial waviness of stress buffer block 9 and insulating barrier 3, described first layer gold 5, palladium layers 6 and the second layer gold 7 also waviness.
Claims (5)
1. a porpezite IC encapsulating lug, comprise the carrier (1) set gradually from bottom to top, conductive layer (2), insulating barrier (3), titanium tungsten layer (4), first layer gold (5), palladium layers (6) and the second layer gold (7), described insulating barrier (3) is provided with hole, exposed portion conductive layer (21), it is characterized in that: the surface of described partial electroconductive layer (21) is at least provided with a stress buffer block (9), described stress buffer block (9) is polyethylene products, described titanium tungsten layer (4) fitting part conductive layer (21), the surperficial waviness of stress buffer block (9) and insulating barrier (3), described first layer gold (5), palladium layers (6) and the second layer gold (7) also waviness.
2. a kind of porpezite IC encapsulating lug as claimed in claim 1, is characterized in that: described carrier (1) is silicon chip.
3. a kind of porpezite IC encapsulating lug as claimed in claim 1, is characterized in that: described conductive layer (2) is aluminium pad.
4. a kind of porpezite IC encapsulating lug as claimed in claim 1, is characterized in that: described insulating barrier (3) is PSV insulating material.
5. a kind of porpezite IC encapsulating lug as claimed in claim 1, is characterized in that: described stress buffer block (9) is uniformly distributed in the surface of partial electroconductive layer (21).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510537870.7A CN105185761A (en) | 2015-08-28 | 2015-08-28 | Porpezite IC packaging projection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510537870.7A CN105185761A (en) | 2015-08-28 | 2015-08-28 | Porpezite IC packaging projection |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105185761A true CN105185761A (en) | 2015-12-23 |
Family
ID=54907751
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510537870.7A Pending CN105185761A (en) | 2015-08-28 | 2015-08-28 | Porpezite IC packaging projection |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105185761A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101989590A (en) * | 2009-07-30 | 2011-03-23 | 瀚宇彩晶股份有限公司 | New bump structure |
| CN202384329U (en) * | 2012-01-05 | 2012-08-15 | 颀邦科技股份有限公司 | Lug structure |
| CN104051406A (en) * | 2013-11-06 | 2014-09-17 | 南茂科技股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN204885142U (en) * | 2015-08-28 | 2015-12-16 | 周义亮 | Palau IC encapsulates lug |
-
2015
- 2015-08-28 CN CN201510537870.7A patent/CN105185761A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101989590A (en) * | 2009-07-30 | 2011-03-23 | 瀚宇彩晶股份有限公司 | New bump structure |
| CN202384329U (en) * | 2012-01-05 | 2012-08-15 | 颀邦科技股份有限公司 | Lug structure |
| CN104051406A (en) * | 2013-11-06 | 2014-09-17 | 南茂科技股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN204885142U (en) * | 2015-08-28 | 2015-12-16 | 周义亮 | Palau IC encapsulates lug |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20151223 |