CN105161537A - MOSFET assembly with low threshold voltage and on resistance - Google Patents
MOSFET assembly with low threshold voltage and on resistance Download PDFInfo
- Publication number
- CN105161537A CN105161537A CN201510466253.2A CN201510466253A CN105161537A CN 105161537 A CN105161537 A CN 105161537A CN 201510466253 A CN201510466253 A CN 201510466253A CN 105161537 A CN105161537 A CN 105161537A
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 13
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 238000002513 implantation Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 abstract description 14
- 239000002019 doping agent Substances 0.000 description 11
- 230000007423 decrease Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000008280 blood Substances 0.000 description 1
- 210000004369 blood Anatomy 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000000452 restraining effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides an MOSFET assembly with low threshold voltage and on resistance, comprising a source, a dielectric layer, an N+ source region, a polycrystalline silicon gate, a gate dielectric layer, a drain, a P well region, an N-type epitaxial region, and a P-type region. The dielectric layer is disposed between the source and the polycrystalline silicon gate. The N+ source region is disposed at the side of the gate dielectric layer. The gate dielectric layer is disposed at the periphery of the polycrystalline silicon gate. The drain is disposed under the N-type epitaxial region. The P-type region is disposed in the P well region. The P well region is disposed under the N+ source region. Under the condition of improving an N-type substrate region, there is no need to improve the doping concentration and depth of the P well region. The MOSFET assembly has the characteristics of low break-over voltage and low on resistance.
Description
Technical field
The present invention relates to a kind of MOSFET assembly, particularly, relate to a kind of MOSFET assembly reducing starting voltage (Lowthresholdvoltage) and conducting resistance.
Background technology
At conventional power MOSFET (Metal-Oxide-SemiconductorField-EffectTransistor, metal-oxide half field effect transistor) in assembly, mainly through the voltage endurance capability that low dopant concentration and certain thickness N-type substrate district provide assembly enough, therefore N-type substrate district is main conducting resistance source, because material has higher critical breakdown voltage in SiC technique, therefore substrate dopant concentration and thickness can be improved to reduce conducting resistance, but high substrate dopant concentration can cause the change of assembly exhaustion region distribution character, in order to the exhaustion region of restraining P wellblock touches the decline that N+source (source) district causes voltage endurance capability, component design needs the dopant concentration and the degree of depth that improve P wellblock, but such way significantly can improve starting voltage and the channel resistance of assembly.
As shown in Figure 1, conventional high-tension MOSFET assembly comprises source electrode 1, dielectric layer 2, N+source (source) district 3, polysilicon gate 4, gate dielectric layer (gate-dielectric) 5, drain electrode 6, P wellblock 7, N-type epitaxial region 8.Voltage endurance capability in conventional high-tension MOSFET assembly primarily of suitable thickness and the N-type substrate of gently mixing provided, therefore can be the main source of the conducting resistance of MOSFET assembly from the resistance in N-type substrate district.
Because material has higher critical collapse Electric Field Characteristics, therefore can improve the dopant concentration of N-type substrate and reduce thickness to obtain enough voltage endurance capabilities, but improving the dopant concentration of N-type substrate needs the concentration of relative raising P wellblock and the degree of depth to avoid exhaustion region to extend to decline that voltage endurance capability is caused in Source (source) region, can improve starting voltage (thresholdvoltage) and the aisle resistance (channelresistance) of element turns like this.
Summary of the invention
For defect of the prior art, the object of this invention is to provide a kind of MOSFET assembly reducing starting voltage and conducting resistance, it is under the situation improving N-type substrate district, does not need the dopant concentration and the degree of depth that improve P wellblock, has the characteristic of low conducting voltage and low on-resistance.
According to an aspect of the present invention, a kind of MOSFET group reducing starting voltage and conducting resistance is provided, it is characterized in that, comprise source electrode, dielectric layer, N+ source region, polysilicon gate, gate dielectric layer, drain electrode, P wellblock, N-type epitaxial region, territory, p type island region, dielectric layer is between source electrode and polysilicon gate, N+ source region is positioned at the side of gate dielectric layer, gate dielectric layer is positioned at the periphery of polysilicon gate, drain electrode is positioned at the below of N-type epitaxial region, territory, p type island region is positioned at P wellblock, and P wellblock is positioned at the below in N+ source region.
Preferably, P type implantation region is provided with between the bottom of described gate dielectric layer and N-type epitaxial region.
Preferably, the length in territory, described p type island region is greater than the length in N+ source region.
Compared with prior art, the present invention has following beneficial effect: the present invention, under the situation improving N-type substrate district, does not need the dopant concentration and the degree of depth that improve P wellblock, has the characteristic of low conducting voltage and low on-resistance.
Accompanying drawing explanation
By reading the detailed description done non-limiting example with reference to the following drawings, other features, objects and advantages of the present invention will become more obvious:
Fig. 1 is the structural representation of conventional high-tension MOSFET assembly.
Fig. 2 is the structural representation that the present invention reduces the MOSFET assembly of starting voltage and conducting resistance.
Embodiment
Below in conjunction with specific embodiment, the present invention is described in detail.Following examples will contribute to those skilled in the art and understand the present invention further, but not limit the present invention in any form.It should be pointed out that to those skilled in the art, without departing from the inventive concept of the premise, some distortion and improvement can also be made.These all belong to protection scope of the present invention.
As shown in Figure 2, the MOSFET assembly that the present invention reduces starting voltage and conducting resistance comprises source electrode 1, dielectric layer 2, N+source (source) district 3, polysilicon gate 4, gate dielectric layer (gate-dielectric) 5, drain electrode 6, P wellblock 7, N-type epitaxial region 8, territory, p type island region 9, dielectric layer 2 is between source electrode 1 and polysilicon gate 4, N+source (source) district 3 is positioned at the side of gate dielectric layer (gate-dielectric) 5, gate dielectric layer (gate-dielectric) 5 is positioned at the periphery of polysilicon gate 4, drain electrode 6 is positioned at the below of N-type epitaxial region 8, territory, p type island region 9 is positioned at P wellblock 7, P wellblock 7 is positioned at the below in N+source (source) district 3.The length in territory, described p type island region is greater than the length in N+ source region, and convenient like this differentiation, significantly reduces the conducting resistance of assembly in addition.
P type implantation region 10 is provided with between the bottom of gate dielectric layer (gate-dielectric) 5 and N-type epitaxial region 8.P type implantation region 10 changes the distribution of grid low-side current by P type implanted ions and protects grid lower gate dielectric layer (gate-dielectric), can the reliability of further lifting subassembly.
The present invention increases a territory, p type island region of heavily mixing in P wellblock, under the situation of dopant concentration increasing N-type substrate, do not need the degree of depth and the dopant concentration that improve P wellblock especially, exhaustion region can be restrained and extend to N+Source region, therefore significantly can reduce the conducting resistance of assembly.The present invention can provide must not change with the dopant concentration of N-type substrate P wellblock concentration and the characteristic of the degree of depth, under the condition of the N-type substrate resistance reduced, must not sacrifice channel resistance and improve starting voltage, particularly in SiC technique.
Above specific embodiments of the invention are described.It is to be appreciated that the present invention is not limited to above-mentioned particular implementation, those skilled in the art can make various distortion or amendment within the scope of the claims, and this does not affect flesh and blood of the present invention.
Claims (3)
1. one kind is reduced the MOSFET group of starting voltage and conducting resistance, it is characterized in that, comprise source electrode, dielectric layer, N+ source region, polysilicon gate, gate dielectric layer, drain electrode, P wellblock, N-type epitaxial region, territory, p type island region, dielectric layer is between source electrode and polysilicon gate, N+ source region is positioned at the side of gate dielectric layer, and gate dielectric layer is positioned at the periphery of polysilicon gate, and drain electrode is positioned at the below of N-type epitaxial region, territory, p type island region is positioned at P wellblock, and P wellblock is positioned at the below in N+ source region.
2. the MOSFET group of reduction starting voltage according to claim 1 and conducting resistance, is characterized in that, is provided with P type implantation region between the bottom of described gate dielectric layer and N-type epitaxial region.
3. the MOSFET group of reduction starting voltage according to claim 1 and conducting resistance, is characterized in that, the length in territory, described p type island region is greater than the length in N+ source region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510466253.2A CN105161537A (en) | 2015-07-31 | 2015-07-31 | MOSFET assembly with low threshold voltage and on resistance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510466253.2A CN105161537A (en) | 2015-07-31 | 2015-07-31 | MOSFET assembly with low threshold voltage and on resistance |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105161537A true CN105161537A (en) | 2015-12-16 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510466253.2A Pending CN105161537A (en) | 2015-07-31 | 2015-07-31 | MOSFET assembly with low threshold voltage and on resistance |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105161537A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103247681A (en) * | 2012-02-02 | 2013-08-14 | 万国半导体股份有限公司 | nano mosfet with trench bottom oxide shielded and third dimensional p-body contact |
| WO2014146870A1 (en) * | 2013-03-18 | 2014-09-25 | Robert Bosch Gmbh | Rectifier diode |
| US9093522B1 (en) * | 2014-02-04 | 2015-07-28 | Maxpower Semiconductor, Inc. | Vertical power MOSFET with planar channel and vertical field plate |
| CN204857733U (en) * | 2015-07-31 | 2015-12-09 | 上海晶亮电子科技有限公司 | Reduce initial voltage and conducting resistance's MOSFET subassembly |
-
2015
- 2015-07-31 CN CN201510466253.2A patent/CN105161537A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103247681A (en) * | 2012-02-02 | 2013-08-14 | 万国半导体股份有限公司 | nano mosfet with trench bottom oxide shielded and third dimensional p-body contact |
| WO2014146870A1 (en) * | 2013-03-18 | 2014-09-25 | Robert Bosch Gmbh | Rectifier diode |
| US9093522B1 (en) * | 2014-02-04 | 2015-07-28 | Maxpower Semiconductor, Inc. | Vertical power MOSFET with planar channel and vertical field plate |
| CN204857733U (en) * | 2015-07-31 | 2015-12-09 | 上海晶亮电子科技有限公司 | Reduce initial voltage and conducting resistance's MOSFET subassembly |
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| CB02 | Change of applicant information |
Address after: 361028, No. 9 East Xinle Road, Haicang District, Fujian, Xiamen Applicant after: Xiamen core bright Electronic Technology Co., Ltd. Address before: 200233 102B room 83, building 700, Yishan Road, Shanghai, Xuhui District, China Applicant before: SHANGHAI JINGLIANG ELECTRONIC TECHNOLOGY CO., LTD. |
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Application publication date: 20151216 |
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| RJ01 | Rejection of invention patent application after publication |