CN105161422A - Method for manufacturing super junction deep groove - Google Patents
Method for manufacturing super junction deep groove Download PDFInfo
- Publication number
- CN105161422A CN105161422A CN201510458145.0A CN201510458145A CN105161422A CN 105161422 A CN105161422 A CN 105161422A CN 201510458145 A CN201510458145 A CN 201510458145A CN 105161422 A CN105161422 A CN 105161422A
- Authority
- CN
- China
- Prior art keywords
- hard mask
- mask layer
- deep groove
- super junction
- described hard
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 43
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 14
- 239000010703 silicon Substances 0.000 claims abstract description 14
- 238000005516 engineering process Methods 0.000 claims abstract description 9
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 4
- 238000001259 photo etching Methods 0.000 claims description 15
- 230000000694 effects Effects 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 239000000376 reactant Substances 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000000206 photolithography Methods 0.000 abstract 1
- 239000013049 sediment Substances 0.000 abstract 1
- 230000007547 defect Effects 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 230000001105 regulatory effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
Abstract
The invention discloses a method for manufacturing a super junction deep groove. The method includes the steps of: forming a hard mask layer on an N type silicon chip; carrying out a photolithography technique to define a formation area of the super junction deep groove; etching the hard mask layer, removing a first photoresist graph, enabling a side wall of the hard mask layer after etching to be smooth through adjustment of an etching technology of the hard mask layer and thereby eliminating subsequent vertical stripes of the side wall of the super junction deep groove. The adjustment of the etching technology of the hard mask layer improves stability and uniformity of an etching process and reinforces sediment in the etching process based on settings of RF source power and a gas flow ratio of CHF3 and CF4, so as to improve roughness of the surface of the side wall of the hard mask layer. The method for manufacturing the super junction deep groove can eliminate vertical stripes of the side wall of the deep groove, thereby improving electrical properties of a super junction device.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit method of manufacturing technology, particularly relate to a kind of manufacture method of super junction deep groove.
Background technology
Adopt the MOS device of super junction (superjunction) structure, because its structure is special, have conducting resistance low, high pressure resistant, the advantage that caloric value is low, is therefore again coolMOS device.One of implementation method of super-junction structures first on N-type silicon chip, etches deep trench, then by extension (EPI) disposable filling p-type silicon, this method cost is relatively low, but technology difficulty is higher.
Wherein the sidewall profile of deep trench directly can affect the effect that follow-up EPI fills.The vertical striped that deep trench sidewall produces in etching process can affect EPI and fill monocrystalline silicon perfection of lattice, produces the defects such as dislocation, thus has a strong impact on the electrology characteristic of super junction.As shown in Figure 1, the side view photo of the super junction deep groove that existing method is formed, can find out that region also exists vertical striped shown in the sidewall of super junction deep groove and dotted line circle 101, this vertical striped can affect EPI and fill monocrystalline silicon perfection of lattice, produce the defects such as dislocation, thus have a strong impact on the electrology characteristic of super junction.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of manufacture method of super junction deep groove, can eliminate the vertical striped of sidewall of deep trench, improves the electrology characteristic of super-junction device.
For solving the problems of the technologies described above, the manufacture method of super junction deep groove provided by the invention comprises the steps:
Step one, on N-type silicon chip, form the hard mask layer be made up of silicon oxide layer.
Step 2, on described hard mask layer spin coating photoresist carry out photoetching and be formed with the first photoetching offset plate figure, described first photoetching offset plate figure defines the forming region of super junction deep groove.
Step 3, for mask, described hard mask layer to be etched with described first photoetching offset plate figure, remove described first photoetching offset plate figure; Make the sidewall of the described hard mask layer after etching smooth by the adjustment of the etching technics to described hard mask layer, by making the smooth vertical striped eliminating follow-up super junction deep groove sidewall of the sidewall of described hard mask layer;
The adjustment of the etching technics of described hard mask layer is comprised: reduce described hard mask layer etch rate by RF source power being set to 400W ~ 800W and etching process stability and uniformity are improved; strengthen the reactant in described hard mask layer etching process in the sedimentary effect of described hard mask layer sidewall strengthen deposit to the protection of described hard mask layer sidewall by the gas flow ratio of CHF3 and CF4 being greater than 4:1, improve the roughness of described hard mask layer sidewall surfaces in conjunction with the protection of deposit to described hard mask layer sidewall in the raising of etching process stability and uniformity and etching process.
Step 4, form super junction deep groove with the described hard mask layer after etching for mask carries out etching to the silicon of the forming region of described super junction deep groove.
Further improvement is, the CHF3 gas flow of the etching technics of hard mask layer described in step 3 is 30sccm ~ 50sccm.
Further improvement is, step 4 also comprises step after forming described super junction deep groove:
Step 5, remove described hard mask layer.
Step 6, in described super junction deep groove, fill P-type silicon.
Further improvement is, adopts epitaxial growth technology to fill P-type silicon in step 6 in described super junction deep groove.
The present invention is regulated by the etching of the hard mask layer to the mask as super junction deep groove, make the sidewall of the hard mask layer after etching smooth, by the smooth vertical striped eliminating super junction deep groove sidewall of sidewall of the hard mask layer after etching, so the present invention can eliminate the vertical striped of sidewall of deep trench, thus EPI filling monocrystalline silicon perfection of lattice can be improved, eliminate the defects such as dislocation, improve the electrology characteristic of super-junction device.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the side view photo of the super junction deep groove that existing method is formed;
Fig. 2 is the flow chart of embodiment of the present invention method;
Fig. 3 A-Fig. 3 E is the structural representation of device in each step of embodiment of the present invention method;
Fig. 4 is the side view photo of the super junction deep groove that embodiment of the present invention method is formed.
Embodiment
As shown in Figure 2, be the flow chart of embodiment of the present invention method; As shown in Fig. 3 A to Fig. 3 E, it is the structural representation of device in each step of embodiment of the present invention method.The manufacture method of embodiment of the present invention super junction deep groove comprises the steps:
Step one, as shown in Figure 3A, N-type silicon chip 1 forms hard mask layer 2.Described hard mask layer 2 is silicon oxide layer.
Step 2, as shown in Figure 3A, spin coating photoresist on described hard mask layer 2 also carries out photoetching and is formed with the first photoetching offset plate figure 3, and described first photoetching offset plate figure 3 defines the forming region of super junction deep groove.
Step 3, as shown in Figure 3 B, etch for mask with described first photoetching offset plate figure 3 to described hard mask layer 2, after etching, described hard mask layer has graphic structure and is labeled as 2a; Remove described first photoetching offset plate figure 3 afterwards.
The embodiment of the present invention makes the sidewall of the described hard mask layer 2a after etching smooth by the adjustment of the etching technics to described hard mask layer 2, by making the smooth vertical striped eliminating follow-up super junction deep groove 4 sidewall of the sidewall of described hard mask layer 2a;
The adjustment of the etching technics of described hard mask layer 2 is comprised: reduce described hard mask layer 2 etch rate by RF source power being set to 400W ~ 800W and etching process stability and uniformity are improved; namely adopting the larger condition of CHF3 accounting to strengthen the reactant in described hard mask layer 2 etching process in the sedimentary effect of described hard mask layer 2 sidewall to strengthen deposit to the protection of described hard mask layer 2 sidewall by the gas flow ratio of CHF3 and CF4 being greater than 4:1, improving the roughness of described hard mask layer 2 sidewall surfaces in conjunction with the protection of deposit to described hard mask layer 2 sidewall in the raising of etching process stability and uniformity and etching process.
Be preferably, the CHF3 gas flow of the etch technological condition of described hard mask layer 2 is 30sccm ~ 50sccm.
Step 4, as shown in Figure 3 C, forms super junction deep groove 4 with the described hard mask layer 2a after etching for mask carries out etching to the silicon of the forming region of described super junction deep groove.
Step 5, as shown in Figure 3 D, remove described hard mask layer 2a.
Step 6, as shown in FIGURE 3 E, adopts epitaxial growth technology to fill P-type silicon 5 in described super junction deep groove 4.
The embodiment of the present invention is regulated by the etching of the hard mask layer 2 to the mask as super junction deep groove, make the sidewall of the hard mask layer 2a after etching smooth, by the smooth vertical striped eliminating the sidewall of super junction deep groove 4 of sidewall of the hard mask layer 2a after etching, as shown in Figure 4, the side view photo of super junction deep groove that embodiment of the present invention method is formed, can find out that region does not exist vertical striped shown in the sidewall of super junction deep groove and dotted line circle 102.So the embodiment of the present invention can eliminate the vertical striped of sidewall of deep trench 4, thus EPI filling monocrystalline silicon perfection of lattice can be improved, eliminate the defects such as dislocation, improve the electrology characteristic of super-junction device.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (4)
1. a manufacture method for super junction deep groove, is characterized in that, comprises the steps:
Step one, on N-type silicon chip, form the hard mask layer be made up of silicon oxide layer;
Step 2, on described hard mask layer spin coating photoresist carry out photoetching and form the first photoetching offset plate figure, described first photoetching offset plate figure defines the forming region of super junction deep groove;
Step 3, for mask, described hard mask layer to be etched with described first photoetching offset plate figure, remove described first photoetching offset plate figure; Make the sidewall of the described hard mask layer after etching smooth by the adjustment of the etching technics to described hard mask layer, by making the smooth vertical striped eliminating follow-up super junction deep groove sidewall of the sidewall of described hard mask layer;
The adjustment of the etching technics of described hard mask layer is comprised: reduce described hard mask layer etch rate by RF source power being set to 400W ~ 800W and etching process stability and uniformity are improved, by the gas flow ratio of CHF3 and CF4 is greater than 4:1 strengthen the reactant in described hard mask layer etching process in the sedimentary effect of described hard mask layer sidewall thus strengthen deposit to the protection of described hard mask layer sidewall, the roughness of described hard mask layer sidewall surfaces is improved in conjunction with the protection of deposit to described hard mask layer sidewall in the raising of etching process stability and uniformity and etching process,
Step 4, form super junction deep groove with the described hard mask layer after etching for mask carries out etching to the silicon of the forming region of described super junction deep groove.
2. the manufacture method of super junction deep groove as claimed in claim 1, is characterized in that: step 4 also comprises step after forming described super junction deep groove:
Step 5, remove described hard mask layer;
Step 6, in described super junction deep groove, fill P-type silicon.
3. the manufacture method of super junction deep groove as claimed in claim 1, is characterized in that: adopt epitaxial growth technology to fill P-type silicon in step 6 in described super junction deep groove.
4. the manufacture method of super junction deep groove as claimed in claim 1, is characterized in that: the CHF3 gas flow of the etching technics of hard mask layer described in step 3 is 30sccm ~ 50sccm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510458145.0A CN105161422A (en) | 2015-07-30 | 2015-07-30 | Method for manufacturing super junction deep groove |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510458145.0A CN105161422A (en) | 2015-07-30 | 2015-07-30 | Method for manufacturing super junction deep groove |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105161422A true CN105161422A (en) | 2015-12-16 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510458145.0A Pending CN105161422A (en) | 2015-07-30 | 2015-07-30 | Method for manufacturing super junction deep groove |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105161422A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107275389A (en) * | 2017-06-30 | 2017-10-20 | 上海华虹宏力半导体制造有限公司 | The channel filling method of super junction |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103258729A (en) * | 2007-12-21 | 2013-08-21 | 朗姆研究公司 | Fabrication of a silicon structure and deep silicon etch with profile control |
| CN104779298A (en) * | 2015-04-24 | 2015-07-15 | 无锡同方微电子有限公司 | Super-junction MOSFET terminal structure and manufacturing method thereof |
-
2015
- 2015-07-30 CN CN201510458145.0A patent/CN105161422A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103258729A (en) * | 2007-12-21 | 2013-08-21 | 朗姆研究公司 | Fabrication of a silicon structure and deep silicon etch with profile control |
| CN104779298A (en) * | 2015-04-24 | 2015-07-15 | 无锡同方微电子有限公司 | Super-junction MOSFET terminal structure and manufacturing method thereof |
Non-Patent Citations (1)
| Title |
|---|
| 敬小成等: "二氧化硅干法蚀刻参数的优化研究", 《半导体技术》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107275389A (en) * | 2017-06-30 | 2017-10-20 | 上海华虹宏力半导体制造有限公司 | The channel filling method of super junction |
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Application publication date: 20151216 |