CN105140214A - Testing structure for monitoring pull-up transistors in SRAM storage array and testing method - Google Patents
Testing structure for monitoring pull-up transistors in SRAM storage array and testing method Download PDFInfo
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- CN105140214A CN105140214A CN201410243329.0A CN201410243329A CN105140214A CN 105140214 A CN105140214 A CN 105140214A CN 201410243329 A CN201410243329 A CN 201410243329A CN 105140214 A CN105140214 A CN 105140214A
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Abstract
The present invention provides a testing structure for monitoring pull-up transistors in an SRAM storage array. The testing structure comprises a long chain type pull-up transistor group which is formed by multiple pull-up transistors at the first side of the long chain type pull-up transistor group and multiple pull-up transistors at the second side opposite to the first side, wherein the pull-up transistors at the same side are connected in parallel, and the source electrodes and gates of the pull-up transistors at different side are electrically connected sequentially. The testing structure also comprises a first pad, a second pad, a third pad and a fourth pad. The first pad is electrically connected to the drain electrodes of the pull-up transistors at the first side. The second pad is electrically connected to the source electrodes of the pull-up transistors at the first side. The third pad is electrically connected to the source electrodes of the pull-up transistors at the second side. The fourth pad is electrically connected to the drain electrodes of the pull-up transistors at the second side. Through the testing structure of the invention, the electrical performance of the pull-up transistors can be effectively monitored.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly relating to a kind of for monitoring the test structure and method of testing that SRAM storage array pulls up transistor.
Background technology
Along with the development of digital integrated circuit, SRAM (StaticRandomAccessMemory, static RAM) becomes important component part indispensable in on-chip memory with the advantage of its low-power consumption, high speed.Along with constantly the reducing of process of chip, the fluctuation how controlling MOS transistor is more and more important for maintenance SRAM yield.
General 6TSRAM memory cell comprises 6 metal-oxide layer semiconductcor field effect transistor Metal-Oxide-SemiconductorField-EffectTransistor, MOSFET), be 2 respectively to pull up transistor, 2 pull-down transistors and 2 transmission transistors, wherein, pull up transistor have that size is little, width is little, feature to the sensitive that fluctuates in processing procedure.
Therefore, be necessary to propose a kind of new test structure, to monitor pulling up transistor of SRAM storage array.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of for monitoring the test structure pulled up transistor in SRAM storage array, comprise: long-chain formula pulls up transistor group, the described long-chain formula group that pulls up transistor pulls up transistor to form with multiple the pulling up transistor being positioned at second side relative with described first side by being positioned at pull up transistor group first side multiple of described long-chain formula, wherein, be positioned at the parallel connection that pulls up transistor of the same side, be positioned at the source electrode pulled up transistor and the electrical connection of grid order of not homonymy
Also comprise the first pad, the second pad, the 3rd pad and the 4th pad, wherein,
Described first pad is electrically connected with multiple drain electrodes pulled up transistor of described first side;
Described second pad is electrically connected with multiple source electrodes pulled up transistor of described first side;
Described 3rd pad is electrically connected with multiple source electrodes pulled up transistor of described second side;
Described 4th pad is electrically connected with multiple drain electrodes pulled up transistor of described second side.
Further, described first pad, described second pad, described 3rd pad and described 4th pad are positioned at Cutting Road.
Further, by multiple rectangular contact window, described first pad is electrically connected with multiple drain electrodes pulled up transistor of described first side;
By multiple shared contact hole, described second pad is electrically connected with multiple source electrodes pulled up transistor of described first side;
By multiple shared contact hole, described 3rd pad is electrically connected with multiple source electrodes pulled up transistor of described second side by multiple rectangular contact window;
By multiple shared contact hole, described 4th pad is electrically connected with multiple drain electrodes pulled up transistor of described second side.
Further, the number of multiple transistors of described first side is 4 or 5, and the number of multiple transistors of described second side is 4 or 5.
Further, described test structure layout depend on described long-chain formula pull up transistor group layout.
The present invention also provides a kind of method of testing based on above-mentioned test structure, and described method of testing is applicable to monitor described long-chain formula and pulls up transistor the short circuit paths of group and leakage current and/or permit the data of Acceptance Tests for obtaining the pull up transistor wafer of group of described long-chain formula.
Further, disconnect described first pad and described 4th pad, connect described second pad and described 3rd pad to test grid whether short circuit.
Further, disconnect described second pad and described 4th pad, connect described first pad and described 3rd pad test grid whether short circuit.
Further, disconnect described 3rd pad and described 4th pad, connect multiple source-drain paths pulled up transistor whether short circuit that described first pad and described second pad test are positioned at described first side.
Further, disconnect described first pad and described second pad, connect multiple source-drain paths pulled up transistor whether short circuit that described 3rd pad and described 4th pad test are positioned at described second side.
Further, described wafer permits the data of Acceptance Tests to comprise Idsat/Vt/Ioff.
Further, using described first pad as drain electrode, described second pad is as source electrode, and described 3rd pad, as grid, is tested multiple the pulling up transistor of described first side, obtains the data that described wafer permits Acceptance Tests.
Further, using described 4th pad as drain electrode, described 3rd pad is as source electrode, and described second pad, as grid, is tested multiple the pulling up transistor of described second side, obtains the data that described wafer permits Acceptance Tests.
Further, calculate the mean value that described wafer permits the data of Acceptance Tests, in order to monitor the whether mismatch of pulling up transistor of described first side and described second side.
In sum, test structure of the present invention, it has two functions: one, can be used as to test pull up transistor leakage current, disconnection or short circuit paths test structure; Two, may be used for test to pull up transistor the test structure of WAT data (such as: Idsat/Vt/Ioff).By test structure of the present invention, the electrical property that effective monitoring pulls up transistor.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Fig. 1 is the layout of existing a kind of 6TSRAM storage array;
Fig. 2 is the layout of existing a kind of SRAM storage array, and wherein left figure is layout, and right figure is the circuit diagram pulled up transistor in corresponding left figure square frame;
Fig. 3 a is the test structure vertical view pulled up transistor of SRAM storage array in the embodiment of the present invention one;
Fig. 3 b is the test circuit figure pulled up transistor of SRAM storage array in the embodiment of the present invention one.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
Should be understood that, the present invention can implement in different forms, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiments will expose thoroughly with complete, and scope of the present invention is fully passed to those skilled in the art.
The object of term is only to describe specific embodiment and not as restriction of the present invention as used herein.When this uses, " one ", " one " and " described/to be somebody's turn to do " of singulative is also intended to comprise plural form, unless context is known point out other mode.It is also to be understood that term " composition " and/or " comprising ", when using in this specification, determine the existence of described feature, integer, step, operation, element and/or parts, but do not get rid of one or more other feature, integer, step, operation, element, the existence of parts and/or group or interpolation.When this uses, term "and/or" comprises any of relevant Listed Items and all combinations.
In order to thoroughly understand the present invention, by following description, detailed structure is proposed, to explain technical scheme of the present invention.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Fig. 1 shows the layout of existing 6TSRAM memory cell, if generally want to measure the electric property of PU1 of pulling up transistor, we need the leakage/source/grid of the PU1 that pulls up transistor/body contact pad different from Cutting Road to be connected.Acceptance Tests (WaferAcceptanceTest, WAT) is permitted to obtain the Idsat/Vt/Ioff value of the PU1 that pulls up transistor by wafer.Because the fluctuation of little the surveyed data of the size that pulls up transistor is large, need to be averaged value calculating to the data of sample Idsat/Vt/Ioff.
Given this, the present invention proposes a kind of new test structure, to monitor pulling up transistor of SRAM storage array.
Embodiment one
Below, be described in detail with reference to the test structure of Fig. 2 and Fig. 3 a-3b to the embodiment of the present invention.
As shown in Figure 2, the layout of existing a kind of SRAM storage array, wherein left figure is layout, and right figure is the circuit diagram pulled up transistor in corresponding left figure square frame.Multiple SRAM memory cell is arranged in SRAM array by row and column.
SRAM storage array is formed on semiconductor base.Semiconductor base comprises silicon.Or substrate comprises germanium, germanium silicide or other semi-conducting materials be applicable to.Semiconductor base also can comprise other suitable characteristic sum structures.
In described semiconductor base, form multiple active area, described multiple active area realizes mutual insulating by being positioned at described intrabasement isolation structure each other.Isolation structure is formed in semiconductor base via suitable technology.In one embodiment, isolation structure is formed via shallow trench isolation (STI) technology.In another embodiment, isolation structure or can be formed via silicon selective oxidation (LOCOS) technology.
Described SRAM storage array also comprises the transistor be formed in multiple active area, such as multiplely pulls up transistor.
SRAM storage array also comprises the interconnection wiring of the first metal layer.Various interconnection structure can be used to coupling NOMS and PMOS transistor to form the SRAM storage array of actual operation.In an example, be electrically connected by pull up transistor first source electrode of PU1 and the second grid pulling up transistor PU2 of the first metal layer interconnection wiring, be electrically connected by pull up transistor first grid of PU1 and the second source electrode pulling up transistor PU2 of the first metal layer interconnection wiring, be connected with the 3rd drain electrode pulling up transistor PU3 by pull up transistor second drain electrode of PU2 of the first metal layer interconnection wiring, be electrically connected by pull up transistor the 3rd source electrode of PU3 and the 4th grid pulling up transistor PU4 of the first metal wiring layer, be electrically connected by pull up transistor the 4th source electrode of PU4 and the 3rd grid pulling up transistor PU3 of the first metal layer interconnection wiring.In this way, several pull up transistor and form chain types and to pull up transistor group.In one example, as as described in Fig. 3 a long-chain formula pull up transistor group 300 by be positioned at long-chain formula pull up transistor 4 of group first side 300a pull up transistor be positioned at as described in 4 of relative the second side 300b of the first side 300a pull up transistor and form, wherein, be positioned at the parallel connection that pulls up transistor of the same side, be positioned at the source electrode pulled up transistor and the electrical connection of grid order of not homonymy.
It is worth mentioning that, although merely illustrate in fig. 3 a the first side 300a and the second side 300b respectively four parallel connections pull up transistor, the present embodiment does not do concrete restriction to the quantity pulled up transistor, and also can adjust according to the size of SRAM storage array.
Continue each the different contact hole in grid, drain electrode end and source terminal further comprising the first metal layer with reference to accompanying drawing 2, SRAM storage array.The position of contact hole feature and configuration are to connect up, and comprise and doped region or grid are electrically connected to metal level.The geometry of contact hole can need according to practical layout and be designed to various different structure.In an example, for general contact hole function, multiple contact holes of SRAM memory cell are rectangle.In an example, contact hole is routed to corresponding metal wire in the first metal layer.In another example, designing one or more contact hole is shared contact hole on first direction.
With reference to figure 3a-3b, wherein, Fig. 3 a is the test structure vertical view pulled up transistor in the SRAM storage array of the embodiment of the present invention, the test circuit figure pulled up transistor of the SRAM storage array of Fig. 3 b embodiment of the present invention.
Particularly, test structure of the present invention is realized by changing the metal connection pulled up transistor in Cutting Road.This test structure layout derives from the layout pulled up transistor in SRAM storage array, does not carry out any amendment to active area and metal wiring layer.
As shown in Figure 3 a, described test structure comprises the first pad pad1, the second pad pad2, the 3rd pad pad3 and the 4th pad pad4.Wherein said first pad pad1 is electrically connected by multiple drain electrodes pulled up transistor of multiple rectangular contact window with described first side 300a.Described second pad pad2 is electrically connected by multiple source electrodes pulled up transistor of multiple shared contact hole with described first side 300a.Described 3rd pad pad3 is electrically connected by multiple source electrodes pulled up transistor of multiple shared contact hole with described second side 300b.Described 4th pad pad4 is electrically connected by multiple drain electrodes pulled up transistor of multiple rectangular contact window with described second side 300b.Exemplarily, multiple numbers pulled up transistor of the first side 300a are 4, and multiple numbers pulled up transistor of the second side 300b are 4.
The number that every side pulls up transistor can also be the quantity that other are applicable to, and such as every side comprises 5 respectively and pulls up transistor, as shown in Figure 3 b.First pad pad1 is electrically connected with 5 drain electrodes pulled up transistor of the first side.Second pad pad2 is electrically connected with 5 source electrodes pulled up transistor of described first side, and is electrically connected with 5 grids pulled up transistor of the second side.3rd pad pad3 is electrically connected with 5 source electrodes pulled up transistor of described second side, and is electrically connected with 5 grids pulled up transistor of the first side.4th pad pad4 is electrically connected with 5 drain electrodes pulled up transistor of the second side.
In sum, according to test structure of the present invention, it has two functions:
One, can be used as to test pull up transistor leakage current, disconnection or short circuit paths test structure;
Two, may be used for test to pull up transistor the test structure of WAT data (such as: Idsat/Vt/Ioff).
By test structure of the present invention, the electrical property that effective monitoring pulls up transistor.
Embodiment two
The present embodiment provides a kind of method of testing of the test structure adopted in embodiment one, and described method of testing is applicable to monitor described long-chain formula and pulls up transistor the short circuit paths of group 300 and leakage current.
Continue with reference to figure 3b, particularly, when testing, disconnecting any two pads, connecting remaining two pads.
In one example, disconnect described first pad Pad1 and described 4th pad Pad4, connect described second pad Pad2 and described 3rd pad Pad3 to test grid whether short circuit.
In one example, disconnect described second pad Pad2 and described 4th pad Pad4, connect described first pad Pad1 and described 3rd pad Pad3 tests grid whether short circuit.
In one example, disconnect described 3rd pad Pad3 and described 4th pad Pad4, connect multiple source-drain paths pulled up transistor whether short circuit that described first pad Pad1 and described second pad Pad2 test are positioned at described first side 300a.
In one example, disconnect described first pad Pad1 and described second pad Pad2, connect multiple source-drain paths pulled up transistor whether short circuit that described 3rd pad Pad3 and described 4th pad Pad4 test are positioned at described second side 300b.
By said method, the test to the short circuit paths that pulls up transistor can be realized, the test to leakage current can also be realized.
Embodiment three
The present embodiment provides a kind of method of testing of the test structure adopted in embodiment one, and described method of testing is applicable to obtain the pull up transistor wafer of group of described long-chain formula and permits the data of Acceptance Tests, such as, and Idsat/Vt/Ioff value.
Continue with reference to figure 3b, particularly, using described first pad Pad1 as drain electrode, described second pad Pad2 is as source electrode, described 3rd pad Pad3, as grid, tests multiple the pulling up transistor of described first side 300a, obtains the data that described wafer permits Acceptance Tests.Multiple numbers pulled up transistor of described first side are 5.
In one example, using described 4th pad Pad4 as drain electrode, described 3rd pad Pad3 is as source electrode, and described second pad Pad2, as grid, tests multiple the pulling up transistor of described second side 300b, obtains the data that described wafer permits Acceptance Tests.Multiple numbers pulled up transistor of described second side are 5.
Directly calculate the mean value that multiple wafer pulled up transistor permits the data of Acceptance Tests afterwards, in order to monitor the whether mismatch pulled up transistor of described first side 300a and described second side 300b.
In sum, adopt the method for testing of the embodiment of the present invention, for measuring multiple Idsat/Vt/Ioff values pulled up transistor in parallel, also can test respectively the first side and pulling up transistor of the second side, well can monitor both sides and to pull up transistor whether mismatch.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (14)
1. one kind for monitoring the test structure pulled up transistor in SRAM storage array, comprise long-chain formula to pull up transistor group, the described long-chain formula group that pulls up transistor pulls up transistor to form with multiple the pulling up transistor being positioned at second side relative with described first side by being positioned at pull up transistor group first side multiple of described long-chain formula, wherein, be positioned at the parallel connection that pulls up transistor of the same side, be positioned at the source electrode pulled up transistor and the electrical connection of grid order of not homonymy, it is characterized in that, also comprise the first pad, the second pad, the 3rd pad and the 4th pad, wherein
Described first pad is electrically connected with multiple drain electrodes pulled up transistor of described first side;
Described second pad is electrically connected with multiple source electrodes pulled up transistor of described first side;
Described 3rd pad is electrically connected with multiple source electrodes pulled up transistor of described second side;
Described 4th pad is electrically connected with multiple drain electrodes pulled up transistor of described second side.
2. test structure according to claim 1, is characterized in that, described first pad, described second pad, described 3rd pad and described 4th pad are positioned at Cutting Road.
3. test structure according to claim 1, is characterized in that,
By multiple rectangular contact window, described first pad is electrically connected with multiple drain electrodes pulled up transistor of described first side;
By multiple shared contact hole, described second pad is electrically connected with multiple source electrodes pulled up transistor of described first side;
By multiple shared contact hole, described 3rd pad is electrically connected with multiple source electrodes pulled up transistor of described second side by multiple rectangular contact window;
By multiple shared contact hole, described 4th pad is electrically connected with multiple drain electrodes pulled up transistor of described second side.
4. test structure according to claim 1, is characterized in that, the number of multiple transistors of described first side is 4 or 5, and the number of multiple transistors of described second side is 4 or 5.
5. test structure according to claim 1, is characterized in that, described test structure layout depend on described long-chain formula pull up transistor group layout.
6., based on a method of testing for the test structure described in claim 1-5, described method of testing is applicable to monitor described long-chain formula and pulls up transistor the short circuit paths of group and leakage current and/or permit the data of Acceptance Tests for obtaining the pull up transistor wafer of group of described long-chain formula.
7. method of testing according to claim 6, is characterized in that, disconnects described first pad and described 4th pad, connects described second pad and described 3rd pad to test grid whether short circuit.
8. method of testing according to claim 6, is characterized in that, disconnects described second pad and described 4th pad, connects described first pad and described 3rd pad test grid whether short circuit.
9. method of testing according to claim 6, is characterized in that, disconnects described 3rd pad and described 4th pad, connects multiple source-drain paths pulled up transistor whether short circuit that described first pad and described second pad test are positioned at described first side.
10. method of testing according to claim 6, is characterized in that, disconnects described first pad and described second pad, connects multiple source-drain paths pulled up transistor whether short circuit that described 3rd pad and described 4th pad test are positioned at described second side.
11. method of testings according to claim 6, is characterized in that, described wafer permits the data of Acceptance Tests to comprise Idsat/Vt/Ioff.
12. method of testings according to claim 6, is characterized in that, using described first pad as drain electrode, described second pad is as source electrode, described 3rd pad, as grid, is tested multiple the pulling up transistor of described first side, obtains the data that described wafer permits Acceptance Tests.
13. method of testings according to claim 6, is characterized in that, using described 4th pad as drain electrode, described 3rd pad is as source electrode, described second pad, as grid, is tested multiple the pulling up transistor of described second side, obtains the data that described wafer permits Acceptance Tests.
14. method of testings according to claim 6, is characterized in that, calculate the mean value that described wafer permits the data of Acceptance Tests, in order to monitor the whether mismatch of pulling up transistor of described first side and described second side.
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| CN109559778A (en) * | 2018-11-30 | 2019-04-02 | 上海华力微电子有限公司 | SRAM tests structure |
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