CN105118907A - LED chip and preparation method thereof - Google Patents
LED chip and preparation method thereof Download PDFInfo
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- CN105118907A CN105118907A CN201510561132.6A CN201510561132A CN105118907A CN 105118907 A CN105118907 A CN 105118907A CN 201510561132 A CN201510561132 A CN 201510561132A CN 105118907 A CN105118907 A CN 105118907A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 9
- 238000000034 method Methods 0.000 claims description 29
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- 238000001259 photo etching Methods 0.000 claims description 12
- 238000005516 engineering process Methods 0.000 claims description 11
- 230000008021 deposition Effects 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 238000001771 vacuum deposition Methods 0.000 claims description 8
- 230000008020 evaporation Effects 0.000 claims description 6
- 238000001704 evaporation Methods 0.000 claims description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- 238000003486 chemical etching Methods 0.000 claims description 2
- 238000001514 detection method Methods 0.000 abstract description 4
- 230000002159 abnormal effect Effects 0.000 abstract 1
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 123
- 239000000956 alloy Substances 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 6
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 230000032798 delamination Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000004064 recycling Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 241000168254 Siro Species 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008033 biological extinction Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000035800 maturation Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000009987 spinning Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
The invention provides an LED chip. The LED chip includes an epitaxial layer, a first CBL layer on the epitaxial layer, a transparent conductive layer coating the upper surface of the first CBL layer, an electrode layer located on the transparent conductive layer, a second CBL layer located at the inner side of the upper periphery of the electrode layer, and a third CBL layer which is arranged on the transparent conductive layer and is located at the outer side of the bottom periphery of the electrode layer. The invention also provides a preparation method of the LED chip. With the LED chip and preparation method thereof of the invention adopted, a situation that the edge of a main electrode and an electrode extension line have large possibility of falling off from a transparent conductive layer can be radically improved, and voltage increase and rework caused by voltage increase, which are brought about by the looseness of products can be completely avoided, and complaining and compensation which are caused by a situation that LED chips with abnormal electrodes arrive at customers because of missed detection can be avoided more effectively.
Description
Technical field
The invention belongs to LED chip and manufacture field, particularly a kind of LED chip and preparation method thereof, and a kind of method preventing LED chip top electrode from coming off.
Background technology
Light-emitting diode (Light-EmittingDiode is called for short LED) is a kind of is the semi-conductor electronic device of luminous energy by electric energy conversion.When the current flows, electronics and hole compound and send monochromatic light within it.LED illumination has been widely used in household, decoration, office, signboard even street lamp.The general structure of large scale LED chip in prior art is shown in Fig. 1 and Fig. 2, comprise containing the isostructural epitaxial loayer 1 of p-GaN and n-GaN, the CBL layer 2 be positioned on epitaxial loayer, the electrode layer 4 that covers the transparency conducting layer 3 above CBL layer 2 and be positioned at above transparency conducting layer 3, described electrode layer 4 comprises main electrode 41 and electrode extended line 42, and the two is all arranged on above transparency conducting layer 3.
The chip photoetching process related generally in current large scale LED chip is CBL photoetching-ITO photoetching-MESA photoetching-PAD photoetching, this is because easily there is the problem of current crowding in large size chip, by the design of electrode extended line with introduce CBL current barrier layer 2 and can solve current crowding problem well, promote chip brightness.As shown in Figure 2, main electrode is generally the metal pad of diameter 60um-90um, and the length of electrode extended line be tens microns to hundreds of micron, width is 4um-8um only.There is when producing in batches the combination of the electrode extended line of the chip of 1%-2% and the metal at main electrode edge and electrically conducting transparent interlayer to occur coming off or loosening, causing voltage raise and cause doing over again, waste great amount of cost and man-hour.In addition, the chip existence of these electrode exceptions flows into the risk in client's hand because of undetected, once occur that this situation will occur because chip voltage raises and cause customer complaint even to be compensated.
Therefore, this area urgently thoroughly solves LED chip top electrode (at least comprising the edge of whole electrode extended line and main electrode) easily from the problem that ITO layer (transparency conducting layer) departs from or loosens.
A kind of LED with accompanying drawing 1 with analog structure is related in patent application CN201110458472, it comprises the substrate being positioned at bottom, the metal electrode being positioned at CBL layer above described substrate, being covered in the ITO layer on described substrate and CBL layer and being positioned in described ITO layer, described CBL layer is corresponding in vertical direction with metal electrode, and the thickness of described ITO layer increases laterally gradually from center.The object of this invention is the technical problem solving LED chip non-uniform light in prior art, provides a kind of LED chip of even bright dipping in light-emitting area.The problem preventing electrode delamination is not related in this patent application.
There is provided a kind of in patent CN201110212710 and have LED chip of adhesiveness current barrier layer and preparation method thereof, described LED chip comprises: Sapphire Substrate; Be formed at the light emitting epitaxial layer of the upper surface of Sapphire Substrate, the P-pad district of this light emitting epitaxial layer has groove, and groove have ripple glaze sidewall and flat bottom surface, the N district of this light emitting epitaxial layer is provided with N-pad; Comply with this groove shapes and be Al
2o
3the current barrier layer of material; Comply with the scattered reflection type reflector of this current blocking Rotating fields, this scattered reflection type reflector is provided with P-pad; And the transparency conducting layer be formed on this light emitting epitaxial layer and scattered reflection type reflector.The present invention also provides a kind of manufacture method that can make the LED chip of this efficient reflective P electrode high-adhesiveness current blocking structures, weak with the adhesiveness solved in prior art between current barrier layer and high reflective electrode, easily come off and the problem such as the P electrode extinction of LED chip, current utilization rate be low.In this invention, the bottom of described P-pad16 connect be placed in described second layer sunk structure 141 flat bottom surface 1411 on and be engaged mutually with described ripple glaze sidewall 1412, so just described P-pad16 can be arranged at described P-pad district securely, and then solve electrode in prior art and hold caducous problem.But what solve in this patent is the weak problem of adhesiveness between CBL layer and electrode layer, and in this patent, relating to the process arranging in the P-pad district of light emitting epitaxial layer and there is the groove of ripple glaze sidewall and flat bottom surface, the method is complicated and the resistance to overturning of LED chip is not high enough.
Disclose a kind of LED chip in the utility model patent CN201420366932 of applicant's earlier application of the present invention and comprise its light-emitting diode.This LED chip comprises epitaxial loayer and is arranged on the transparency conducting layer on epitaxial loayer, and arranges electrode over transparent conductive layer, and partial electrode penetrates transparency conducting layer and is connected with epitaxial loayer.This utility model is connected with epitaxial loayer by partial electrode is penetrated transparency conducting layer, and the adhesion between partial electrode and epitaxial loayer is strengthened, thus decreases the probability that metal electrode comes off from transparency conducting layer; And be beneficial between partial electrode and epitaxial loayer and form Schottky contacts, serve the effect of current barrier layer, be convenient to current spread to electrically conducting transparent layer region, thus improve the brightness of LED chip.The LED chip manufacture craft of this structure is simple, and with low cost, technology maturation, can improve brightness not increasing cost simultaneously, and then improves the reliability of product, is applicable to batch production.The essence of the method also comprises and a part for electrode is directly connected with epitaxial loayer thus for preventing electrode from coming off from transparency conducting layer, but the method is improved largely for preventing the probability of electrode delamination.
Therefore, this area also needs further to make great efforts preventing electrode to make from the direction that transparency conducting layer comes off.
Summary of the invention
The present invention goes to conceive the problem solving electrode and come off from transparency conducting layer from the angle different from above-mentioned prior art.
The invention provides a kind of LED chip, described LED chip comprises epitaxial loayer, the CBL layer be positioned on epitaxial loayer, cover transparency conducting layer above a CBL layer, be positioned at electrode layer above transparency conducting layer, be positioned at the 2nd CBL layer above electrode layer inside periphery and be positioned at above transparency conducting layer and the 3rd CBL layer be positioned at outside electrode layer bottom periphery.
In a kind of concrete execution mode, described 2nd CBL layer is identical with the thickness of the 3rd CBL layer.Preferably, the thickness ratio of a described CBL layer and the 2nd CBL layer is 1 ~ 9:1, is more preferably 2 ~ 4:1.In the present invention, the summation of the thickness of a described CBL layer and the thickness of the 2nd CBL layer can be 900 ~ 2200A, such as, be 1200A.In the present invention, the thickness of the 2nd CBL layer and width is excessive all may affect electrode performance, and the thickness of a CBL layer can be the consistency of thickness with a CBL layer of the prior art, also can be bigger or be slightly less than its thickness.
In a kind of concrete execution mode, the width of described 2nd CBL layer is 0.8 ~ 2.5 micron, is preferably 1 ~ 2 micron; The width of described 3rd CBL layer is 1.5 ~ 5 microns, is preferably 2 ~ 3 microns.
In the present invention, first, second, and third CBL layer is silicon dioxide layer.Second and the 3rd the width of CBL layer too widely can affect electrode performance, and too narrowly just do not have the due anti-loosening and effect of coming off.The width of the 2nd CBL layer 51 be above electrode from the most peripheral of electrode to the width that electrode centers extends, the width of the 3rd CBL layer 52 is side's outward extending width again from the most peripheral of electrode over transparent conductive layer.
In a kind of concrete execution mode, described 2nd CBL layer and the integrated deposition of silica of the 3rd CBL layer prepare.The 2nd CBL layer that mode like this prepares and the 3rd CBL layer can guarantee the compact siro spinning technology between electrode and ITO layer completely.
In a kind of concrete execution mode, described electrode is p-electrode.Those skilled in the art know ground, and described p-electrode is positioned at directly over p-GaN, and p-GaN is connected with p-electrode with transparency conducting layer through a CBL layer; And n-electrode is positioned at directly over n-GaN, and n-electrode is connected directly between on n-GaN layer.Thus the electrode in the present invention is p-electrode.
In a kind of concrete execution mode, described electrode is main electrode and/or electrode extended line.
The present invention also provides a kind of preparation method of LED chip described above, comprises the steps:
Steps A, first use PECVD method deposition of silica on epitaxial loayer prepare a CBL layer,
Step B, use vacuum coating technology evaporation ITO also prepare transparency conducting layer through photoetching,
Step C, utilize vacuum coating technology depositing electrode metal, obtain electrode layer,
Step D, above transparency conducting layer and electrode layer whole deposition of silica, and prepare described 2nd CBL layer and the 3rd CBL layer by chemical etching.
The present invention also provides a kind of method preventing LED chip top electrode from departing from, and comprises the LED chip using LED chip as above or method described above to prepare.
The situation that the invention enables the edge of main electrode in prior art and electrode extended line easily to depart from from transparency conducting layer is improved with obtaining essence, voltage raises and causes the situation of doing over again because loosening to completely avoid product, and the LED chip that more effectively prevent these electrode exceptions flows in client's hand because of undetected and causes telling compensation.
Accompanying drawing explanation
Fig. 1 is the main TV structure schematic diagram of LED chip in prior art,
Fig. 2 be in prior art and LED chip of the present invention electrode and transparency conducting layer overlook connection diagram,
Fig. 3 is in the present invention second and the 3rd head-down position relation schematic diagram of CBL layer and electrode layer,
Fig. 4 is the main TV structure schematic diagram of LED chip in the present invention.
Wherein: 1, epitaxial loayer, the 2, the one CBL layer, 3, transparency conducting layer, 4, electrode layer, 41, main electrode, 42, electrode extended line, the 51, the 2nd CBL layer, the 52, the 3rd CBL layer.
Embodiment
Composition graphs 1, in current conventional method, large scale LED chip photolithography process is as follows.
1) with PECVD method cvd silicon oxide on epitaxial loayer 1, remove the unwanted silica of part by photoetching, remaining silica forms CBL layer 2, i.e. current barrier layer;
2) with vacuum coating technology evaporation ITO, remove unwanted ITO by the method for photoetching, leave the ITO of needs, form transparency conducting layer 3;
3) remove p-GaN and quantum well layer selectively by the method for dry etching, expose n-GaN, carry out the enhancing of ITO alloy, ITO and GaN ohmic contact, alloy temperature 450 DEG C-650 DEG C;
4) photoetching is done with negative glue, expose the position of p and n-electrode, recycling vacuum coating technology depositing electrode metal on the epitaxial wafer finishing negative-working photoresist, then the metal peeled off except for the electrodes cleaning of removing photoresist, now on P-GaN, define P electrode, n-GaN defines N electrode;
5) electrode metal forms ohmic contact, alloy temperature 150 DEG C-450 DEG C.
For solving electrode delamination or loosening problem, the present invention proposes a kind of easily loosening electrode extended line and the way of main electrode edge clamping between two-layer CBL.I.e. first deposition fraction SiO
2form a CBL layer 2, then electrode evaporation 4, then deposition fraction SiO
2form the 2nd CBL layer 51 and the 3rd CBL layer 52 simultaneously.Other technique is identical with the existing technique in conventional method.In a kind of concrete execution mode, composition graphs 3 and Fig. 4, LED chip of the present invention makes idiographic flow and is:
1) first deposit on epitaxial loayer 1 by PECVD method and account for the SiO that CBL layer design thickness is 3/4ths thickness
2, remove the unwanted SiO of part by the method for photoetching
2, leave the SiO of needs
2form a CBL layer;
2) with vacuum coating technology evaporation ITO, remove unwanted ITO by the method for photoetching, leave the ITO of needs, form transparency conducting layer 3;
3) remove p-GaN and quantum well layer selectively by the method for dry etching, expose n-GaN, carry out the enhancing of ITO alloy, ITO and GaN ohmic contact, alloy temperature 450 DEG C-650 DEG C;
4) photoetching is done with negative glue, expose the position of p and n-electrode, recycling vacuum coating technology depositing electrode metal on the epitaxial wafer finishing negative-working photoresist, then the metal peeled off except for the electrodes cleaning of removing photoresist, now on P-GaN, define P electrode, n-GaN defines N electrode;
5) the CBL layer of 1/4th thickness that deposition is remaining, comprises the 2nd CBL layer 2 and the 3rd CBL layer 3;
6) by the SiO of photoetching by (centre position as two places in Fig. 4 the 2nd CBL layer 2) and all the other regions (peripheral position as two places in Fig. 4 the 3rd CBL layer 3) in the middle of middle above P main electrode and electrode extended line
2remove, stay the SiO above main electrode or electrode extended line
2width is 1 ~ 2 micron, i.e. the 2nd CBL layer 51, the SiO on main electrode or electrode extended line side
2width is 2 ~ 3 microns, i.e. the 3rd CBL layer 52;
7) electrode metal forms ohmic contact, alloy temperature 150 DEG C-450 DEG C.
Step 2 in this method) ITO evaporation and step 3) in the order of " dry etching optionally removes p-GaN and quantum well layer exposes n-GaN " this two step can put upside down.The epitaxial loayer preparing LED chip of the present invention use such as can by being purchased acquisition.The method of operation of each concrete steps involved in preparation method of the present invention is the method for well known to a person skilled in the art.In addition, in the present invention, namely described large size chip needs the chip using electrode extended line.
Embodiment
LED chip structure schematic diagram in the present invention is shown in Fig. 3 and Fig. 4.In the structure of its epitaxial layers 1, a CBL layer 2, transparency conducting layer 3 and electrode layer 4 and Fig. 1, the LED chip structure of prior art is basically identical, but the thickness of a described CBL layer is 3/4 of CBL layer thickness in Fig. 1.Also comprise the 2nd CBL layer 51 and the 3rd CBL layer 52 in LED chip structure of the present invention, the consistency of thickness of the two, is 1/4 of CBL layer thickness in Fig. 1.As seen from Figure 4, the CBL layer in the present invention is positioned at the middle position in electrode width direction, and second and the 3rd CBL layer be all positioned at the both sides of edges in electrode width direction; A CBL layer in the present invention is positioned at the below in electrode height direction, and second and the 3rd CBL layer be positioned at top or the side in electrode height direction.Electrode shown in Fig. 1 and Fig. 4 is all p-electrode, and the thickness of electrode is 1.5 microns.
First to traditionally photoetching process, i.e. as above step 1) ~ 5) 1000 every sheets of large size chip manufacturing all carry out the detection of electrode push-pull effort, find that there is 15 phenomenons that there is electrode extended line 42 or main electrode 41 edge and come off.And to present invention process, i.e. as above step 1) ~ 7) 1000 every sheets of large size chip manufacturing all carry out the detection of electrode push-pull effort, because electrode extended line and main electrode edge clamping all do not have obscission between two-layer CBL.
Known through a survey data again, these 15 have the chip detection result of electrode delamination situation to be that whole voltage raises, are elevated to 3.25 volt of-3.35 volt by normal 3.15 volt of-3.22 volt.And use the inventive method to make 1000 chips are all normal through a survey data voltage.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a LED chip, described LED chip comprises epitaxial loayer (1), the CBL layer (2) be positioned on epitaxial loayer, cover CBL layer (2) top transparency conducting layer (3), be positioned at transparency conducting layer (3) top electrode layer (4), be positioned at the 2nd CBL layer (51) inside the periphery of electrode layer (4) top and be positioned at above transparency conducting layer (3) and the 3rd CBL layer (52) be positioned at outside electrode layer (4) bottom periphery.
2. LED chip according to claim 1, it is characterized in that, described 2nd CBL layer (51) is identical with the thickness of the 3rd CBL layer (52).
3. LED chip according to claim 2, is characterized in that, a described CBL layer (2) is 1 ~ 9:1 with the thickness ratio of the 2nd CBL layer (51).
4. LED chip according to claim 3, is characterized in that, a described CBL layer (2) is 2 ~ 4:1 with the thickness ratio of the 2nd CBL layer (51).
5. LED chip according to claim 1, it is characterized in that, the width of described 2nd CBL layer (51) is 0.8 ~ 2.5 micron, is preferably 1 ~ 2 micron; The width of described 3rd CBL layer (52) is 1.5 ~ 5 microns, is preferably 2 ~ 3 microns.
6. according to LED chip described in any one in Claims 1 to 5, it is characterized in that, described 2nd CBL layer (51) and the 3rd CBL layer (52) integrated deposition of silica prepare.
7. according to LED chip described in any one in Claims 1 to 5, it is characterized in that, described electrode is p-electrode.
8. according to LED chip described in any one in Claims 1 to 5, it is characterized in that, described electrode is main electrode and/or electrode extended line.
9., as a preparation method for LED chip as described in any one in claim 1 ~ 8, comprise the steps:
Steps A, first use PECVD method prepare a CBL layer (2) at the upper deposition of silica of epitaxial loayer (1),
Step B, use vacuum coating technology evaporation ITO also prepare transparency conducting layer (3) through photoetching,
Step C, utilize vacuum coating technology depositing electrode metal, obtain electrode layer (4),
Step D, above transparency conducting layer and electrode layer whole deposition of silica, and prepare described 2nd CBL layer (51) and the 3rd CBL layer (52) by chemical etching.
10. the method preventing LED chip top electrode from departing from, comprises and using as the LED chip in claim 1 ~ 8 as described in any one or the LED chip for preparing of method as claimed in claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510561132.6A CN105118907A (en) | 2015-09-06 | 2015-09-06 | LED chip and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510561132.6A CN105118907A (en) | 2015-09-06 | 2015-09-06 | LED chip and preparation method thereof |
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| CN105118907A true CN105118907A (en) | 2015-12-02 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104103728A (en) * | 2014-08-06 | 2014-10-15 | 湘能华磊光电股份有限公司 | Machining method and machining device for preventing light-emitting diode chip electrode from falling |
| US20150008475A1 (en) * | 2011-10-24 | 2015-01-08 | Formosa Epitaxy Incorporation | Light emmiting diode chip |
| CN104319326A (en) * | 2014-10-21 | 2015-01-28 | 厦门市三安光电科技有限公司 | Light-emitting diode manufacturing method |
-
2015
- 2015-09-06 CN CN201510561132.6A patent/CN105118907A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150008475A1 (en) * | 2011-10-24 | 2015-01-08 | Formosa Epitaxy Incorporation | Light emmiting diode chip |
| CN104103728A (en) * | 2014-08-06 | 2014-10-15 | 湘能华磊光电股份有限公司 | Machining method and machining device for preventing light-emitting diode chip electrode from falling |
| CN104319326A (en) * | 2014-10-21 | 2015-01-28 | 厦门市三安光电科技有限公司 | Light-emitting diode manufacturing method |
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Application publication date: 20151202 |