CN105117264A - Method for converting BIN file into ATP file - Google Patents
Method for converting BIN file into ATP file Download PDFInfo
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- CN105117264A CN105117264A CN201510592946.6A CN201510592946A CN105117264A CN 105117264 A CN105117264 A CN 105117264A CN 201510592946 A CN201510592946 A CN 201510592946A CN 105117264 A CN105117264 A CN 105117264A
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Abstract
The invention discloses a method for converting an executable BIN file into an ATP file capable of being recognized by a test instrument. The method comprises the following steps that firstly, the composition structure of the BIN file is analyzed, and header information, synchronization words and a device ID of the BIN file are distinguished; secondly, data distribution is carried out on a TDI data input port in a JTAG; thirdly, a test head is added, the test head comprises tested Time Set Basic (TSB), JTAG pins and other test pins, and generated test code streams are placed behind the test head; finally, test codes with the verification function are added, and the ATP file is generated. The method can be used in the chip grade and finished product grade testing processing of an integrated circuit to test a programmable logic device with a JTAG port. The method has the advantages that no special storage and control device for producing test codes needs to be added, test codes can be conveniently generated, test difficulty is lowered, test time is shortened, and the method can be conveniently applied in ATE test engineering development.
Description
Art
The invention belongs to integrated circuit testing field, be applied to the integrated circuit of band jtag interface, the particularly test of the programmable logic device (PLD) such as FPGA (FieldProgrammableGateArray field programmable gate array), CPLD (ComplexProgrammableLogicDevice CPLD), be the discernible ATP file of testing tool by executable BIN file transform, be convenient to the generation of test patterns.
Background technology
JTAG (JointTestActionGroup, combined testing action group) be a kind of international standard test protocol, be mainly used in chip internal to test and emulate system, debug, JTAG technology is a kind of embedded type debugging technology, it encapsulates special test circuit TAP (TestAccessPort at chip internal, test access mouth), the jtag test device A TE(AutomaticTestEquipment by special) internal node is tested.
The test code that can identify due to ATE is kept in the file of ATP form, and this file has special form, so usually need, for testing apparatus configures special storage and control device, for writing survey beta code, and to be kept among ATP file.Which adds the difficulty that test code generates, delay test job progress.
Summary of the invention
In order to solve the problem of the Test code generation difficulty in the programmable logic device (PLD) test process of band jtag interface, the invention provides a kind of method executable BIN file transform being become the discernible ATP file of testing tool, being convenient to the generation of test patterns.Use the method, test code can be write by applied software development instrument, generate BIN file, then BIN file transform is become ATP file, so not only avoid the demand being equipped with extra memory part and control device, and reduce test code generation difficulty, improve testing efficiency.
The present invention is the technical thought that its technical barrier of solution is taked: first, uses applied software development instrument to generate the BIN file with set function; Secondly, be ATP file by switching software by BIN file transform; Again, for ATP file adds the test patterns being used for functional verification; Finally ATP file content be converted to the discernible test patterns of ATE and test.Wherein, described switching software realizes the robotization that BIN file transform provided by the invention is ATP document conversion method.
A kind of BIN file transform provided by the invention is that the conversion method of ATP file comprises the following steps:
(1) analyze BIN file composition structure, distinguish header, synchronization character, the device ID in BIN file;
(2) data distribution is carried out to the TDI data input port in JTAG;
(3) add measuring head, comprising the TSB (TimeSetBasic) of test, the pin of JTAG and all the other test pin, be placed in thereafter by the test code streams of generation;
(4) test patterns of authentication function is added;
(5) ATP file is generated.
The invention has the beneficial effects as follows: compared with traditional integrated circuit (IC) testing method for being with jtag interface, BIN file transform provided by the invention is that the method for ATP file avoids the demand being equipped with extra memory part and control device, and reduce test code generation difficulty, improve testing efficiency, the testing engineering exploitation of ATE can be applied to easily.
Accompanying drawing explanation
Fig. 1 is document conversion method process flow diagram;
Fig. 2 is integrated circuit testing process flow diagram;
Fig. 3 is the BIN file layout figure that application software produces;
Fig. 4 is switching software surface chart of the present invention;
Fig. 5 is the ATP file layout figure generated.
Embodiment
According to the method that a kind of BIN file transform of the present invention is ATP file, for the test process of the integrated circuit of band jtag interface, comprise the following steps:
1) in applied software development instrument, write code, the content of chip testing that what this code packages contained is, such as, by FPGA programming realization totalizer, namely use applied software development instrument to write totalizer code.Need the pin of specifying the integrated circuit realizing set function in this process;
2) the BIN file that can be used for JTAG and download is generated by applied software development instrument;
3) the BIN file of generation is converted to ATP file by switching software;
4) in ATP file, add the pin information of test, add testing authentication information, guarantee that integrated circuit realizes set function;
5) ATP file transform is become the discernible test patterns of ATE, carry out integrated circuit testing.
Last it is noted that obviously, above-described embodiment is only for example of the present invention is clearly described, and the restriction not to embodiment.For those of ordinary skill in the field, can also make other changes in different forms on the basis of the above description.Here exhaustive without the need to also giving all embodiments.And thus the apparent change of amplifying out or variation be still among protection scope of the present invention.
Claims (3)
1. a BIN file transform is the method for ATP file, can be used on ic core chip level and become in grade test process, test is implemented to the programmable logic device (PLD) with jtag interface, it is characterized in that: first, analyze BIN file composition structure, distinguish header, synchronization character, the device ID in BIN file; Secondly, data distribution is carried out to the TDI data input port in JTAG; 3rd, add measuring head, comprising the TSB (TimeSetBasic) of test, the pin of JTAG and all the other test pin, be placed in thereafter by the test code streams of generation; Finally, add the test patterns of authentication function and generate ATP file.
2. a kind of BIN file transform according to claim 1 is the method for ATP file, it is characterized in that: the implementation step of described method comprises, and uses applied software development instrument to generate the BIN file with set function; Secondly, be ATP file by switching software by BIN file transform; Again, for ATP file adds the test patterns being used for functional verification; Finally ATP file content be converted to the discernible test patterns of ATE and test.
3. a kind of BIN file transform according to claim 2 is the method for ATP file, it is characterized in that: described switching software realizes the robotization of described conversion method, comprise analysis BIN file layout, the TDI data input port in JTAG carried out to data distribution, add measuring head and generate ATP file function.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201510592946.6A CN105117264A (en) | 2015-09-17 | 2015-09-17 | Method for converting BIN file into ATP file |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510592946.6A CN105117264A (en) | 2015-09-17 | 2015-09-17 | Method for converting BIN file into ATP file |
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| CN105117264A true CN105117264A (en) | 2015-12-02 |
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| CN201510592946.6A Pending CN105117264A (en) | 2015-09-17 | 2015-09-17 | Method for converting BIN file into ATP file |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106646197A (en) * | 2016-12-26 | 2017-05-10 | 中国电子科技集团公司第五十八研究所 | Method for generating modulation signal tested by ATE (automatic test equipment) |
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| US20070035322A1 (en) * | 2005-08-10 | 2007-02-15 | Joong-Wuk Kang | Testing method detecting localized failure on a semiconductor wafer |
| CN101894029A (en) * | 2010-06-21 | 2010-11-24 | 中兴通讯股份有限公司 | Method and device for upgrading complex programmable logic device on line |
| CN104515947A (en) * | 2014-12-12 | 2015-04-15 | 中国电子科技集团公司第五十八研究所 | Rapid configuration and test method for programmable logic device in system programming |
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2015
- 2015-09-17 CN CN201510592946.6A patent/CN105117264A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070035322A1 (en) * | 2005-08-10 | 2007-02-15 | Joong-Wuk Kang | Testing method detecting localized failure on a semiconductor wafer |
| CN101894029A (en) * | 2010-06-21 | 2010-11-24 | 中兴通讯股份有限公司 | Method and device for upgrading complex programmable logic device on line |
| CN104515947A (en) * | 2014-12-12 | 2015-04-15 | 中国电子科技集团公司第五十八研究所 | Rapid configuration and test method for programmable logic device in system programming |
Non-Patent Citations (1)
| Title |
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| 张凯虹等: ""一种FPGA验证与测试方法介绍"", 《电子与封装》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106646197A (en) * | 2016-12-26 | 2017-05-10 | 中国电子科技集团公司第五十八研究所 | Method for generating modulation signal tested by ATE (automatic test equipment) |
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Application publication date: 20151202 |