CN105116413A - High-speed parallel acquisition system clock synchronization device - Google Patents
High-speed parallel acquisition system clock synchronization device Download PDFInfo
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- CN105116413A CN105116413A CN201510563065.1A CN201510563065A CN105116413A CN 105116413 A CN105116413 A CN 105116413A CN 201510563065 A CN201510563065 A CN 201510563065A CN 105116413 A CN105116413 A CN 105116413A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
- G01S13/88—Radar or analogous systems specially adapted for specific applications
- G01S13/89—Radar or analogous systems specially adapted for specific applications for mapping or imaging
- G01S13/90—Radar or analogous systems specially adapted for specific applications for mapping or imaging using synthetic aperture techniques, e.g. synthetic aperture radar [SAR] techniques
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Abstract
The invention relates to a high-speed parallel acquisition system clock synchronization device. According to the synchronization device, a signal conditioning unit is configured; a clock input amplitude range is set; before a switch unit is switched on, signal amplitude is increased to be sufficient to make a post-amplifier saturate; and therefore, clock signals at a triggering initial time point can be consistently identified at each channel, and the synchronization of a multi-channel data acquisition system can be realized. With the synchronization device adopted, the synchronism of the data acquisition system is concentrated on the switching on and switching off of a radio frequency switch, and the transient time of the switching on and switching off of the switch can be substantially compressed, and error influences caused by clock jitter at an A/D sampling starting position can be eliminated, and therefore, clock signal amplitude can be consistently identified at each channel, and excellent stability and reliability can be realized; and the extremely-low phase noise characteristic of a radio frequency circuit is utilized, so that single ended-to-differential low noise conversion of high-speed clock signals can be completed, and the utilization efficiency of the device can be improved, and the size of the device can be effectively reduced, and the realization of the miniaturization of circuits can be benefitted.
Description
Technical field
The present invention relates to data collecting field, relate more specifically to a kind of high-speed parallel acquisition system clock synchronization apparatus and method.
Background technology
The high resolution capacity of radar, antijamming capability and radar signal bandwidth are closely related, such as, in order to improve distance accuracy and range resolution, imaging identification is carried out to target, require the signal of radar emission have large bandwidth, time wide product, i.e. additional bandwidth FM signal in broad pulse, improve radar overall performance with spread signal frequency band, this relates to large bandwidth Signal Collection Technology.
Cannot directly carry out effective A/D conversion to bandwidth more than the signal of more than GHz at present, in order to realize the normal work of radar system and other broadband systems, the work of employing multi-channel parallel is the technical way of large bandwidth signal acquiring system.And in data acquisition system (DAS) more than two-way, all need to do strict logic control and sequential coupling to multichannel subsystem, namely to solve the stationary problem between road.After same signal homophase is loaded into different acquisition passage, guarantee that two groups of collection first mistimings reflected in signal waveform of Number Sequence are zero.This is a very important basic index, is requiring that in waveform acquisition process strict especially, different interchannel synchronous working is the basis of follow-up all data processings to sequential, phase place etc.
In Channels Synchronous Data Acquisition System, sampling with trigger that can reach be synchronously the key accurately sampling signaling point.The work of A/D converter part, mainly determines its switching time and sampling instant by external reference clock and sampling shot clock.When the sampling rate up to 2GHz, sampling interval only has 500ps, even if the sampling instant of two-way ADC has the error of ps level, cause asynchronous be also appreciable.The error t of two-way ADC sampling instant
dwith the phase error P of two-way ADC sampled data
dthere is following relation:
P
d＝2π×f
clk×t
d，
Wherein, f
clkfor sample frequency.
For interchannel synchronous error, prior art often solves at numeric field, or processes sampling clock and trigger pip, in conjunction with phase-locked loop and by means such as optimization circuits, realizes the synchronous of multi-channel A/D.Although existing method is applicable when A/D device sampling rate is lower, but when it come to high-speed a/d, such as in synthetic-aperture radar receiving cable Sampling Rate at more than 2GHz, now circuit is very responsive to signal jitter, when powering at every turn or reset, the error of ps level may be brought interchannel asynchronous, in this case said method be difficult to ensure multi-group data multiple acquisition channels between delay-time difference be substantially 0 or keep steady state, be also just difficult to fundamentally solve stationary problem.
Summary of the invention
In order to solve the synchronism problem of multi-path data acquiring system, the object of the present invention is to provide a kind of high-speed parallel acquisition system clock synchronization apparatus and method.As preferably, synchronous device of the present invention and method have low jitter, low time inclined characteristic, by configuration peripheral circuit, significantly compression triggers the crank-up time of initial time, effectively overcome the error effect that A/D sampling reference position clock jitter brings, make the clock of multi-channel data acquisition unit be fully operational in synchronous regime.
Particularly, as one aspect of the present invention, the invention provides a kind of high-speed parallel acquisition system clock synchronization apparatus, described high-speed parallel acquisition system clock synchronization apparatus is by configuration signal conditioning unit, clock input range scope is set, before switching means conductive, signal amplitude is brought up to the degree being enough to make post-amplifier saturated, make the clock signal triggering initial time obtain consistent identification in each passage, realize the synchronous of multi-path data acquiring system.
As preferably, the invention provides a kind of high-speed parallel acquisition system clock synchronization apparatus, comprising:
One signal condition unit, for regulating the amplitude of the clock signal of input, was increased to the amplitude of described clock signal the degree making the amplifying unit of rear class saturated before switch element control signal is arrived;
One switch element, for controlling the break-make of the clock signal from signal condition unit, and then the initial sum cut-off time of control A/D element circuit sampling;
One amplifying unit, be used on the one hand controlling, when connecting, the amplitude of the described clock signal from described switch element is outputted to suitable level at described switch element, and operate in saturation, improve the steepness of on-off circuit rising edge/negative edge, on the other hand, for described clock signal is converted to differential signal from single-ended signal, meet the requirement of A/D difference sampling clock.
As another aspect of the present invention, the invention provides a kind of high-speed parallel acquisition system clock synchronizing method, comprise the following steps:
Configuration signal conditioning unit, clock input range scope is set, before switching means conductive, signal amplitude is brought up to the degree being enough to make post-amplifier saturated, make the clock signal triggering initial time obtain consistent identification in each passage, thus realize the synchronous of multi-path data acquiring system.
As preferably, the invention provides a kind of high-speed parallel acquisition system clock synchronizing method, comprise the following steps:
Regulate the amplitude being input to the clock signal of signal condition unit, before switch element control signal is arrived, the amplitude of described clock signal is increased to the degree making the amplifying unit of rear class saturated;
Control the break-make from the clock signal of signal condition unit, and then the initial sum cut-off time of control A/D element circuit sampling;
Control, when connecting, the amplitude of the described clock signal from described switch element is outputted to suitable level at described switch element, and operate in saturation, improve the steepness of on-off circuit rising edge/negative edge;
Described clock signal is converted to differential signal from single-ended signal, meets the requirement of A/D difference sampling clock.
Known based on technique scheme, synchronous device of the present invention and method have following beneficial effect: utilize synchronous device of the present invention the synchronism of signal acquiring system only can be concentrated in the break-make of radio-frequency (RF) switch, again by configuration peripheral circuit, the transit time (i.e. the rising edge of switch and negative edge) of switch on and off moment is significantly compressed, eliminate the error effect that A/D sampling reference position clock jitter brings, clock signal amplitude is made to obtain consistent identification in each passage, realize the synchronous working of hyperchannel A/D unit, there is good stability and reliability, can fundamentally Solving Multichannel high-speed a/d sampling synchronism problem, in addition, utilize the phase noise characteristic that radio circuit is extremely low, complete high-speed clock signal and change from the low noise of single-ended-to-difference, and, amplifying unit in circuit is amplified to suitable level clock signal on the one hand, utilize its differential amplification function on the other hand, achieve the conversion of clock signal from single-ended-to-difference, kill two birds with one stone, while the utilization ratio improving device, effectively reduce volume, the miniaturization being beneficial to circuit realizes.
Accompanying drawing explanation
Fig. 1 is the structure principle chart of high-speed parallel acquisition system clock synchronization apparatus of the present invention;
Fig. 2 is the circuit diagram of high-speed parallel acquisition system clock synchronization apparatus of the present invention;
Fig. 3 is the photo in kind (physical dimension: 51mm × 36mm) as the high-speed parallel acquisition system clock synchronization apparatus of one embodiment of the invention;
Fig. 4 is the serial oscillogram of the 2GHz clock signal as the embodiment of the present invention, and wherein Fig. 4 (a) is the oscillogram of 2GHz clock signal only after switch element; Fig. 4 (b) is the oscillogram of this signal after synchronous device of the present invention; Fig. 4 (c) is for vowing amplitude, the phase diagram of the synchronous device output terminal of the present invention of net test.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly understand, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in further detail.
The invention discloses a kind of high-speed parallel acquisition system clock synchronization apparatus, its concrete principle is: by configuration peripheral circuit, significantly compression triggers the crank-up time of initial time, namely by configuration signal conditioning unit, clock input range scope is set, before switching means conductive, signal amplitude is brought up to the degree being enough to make post-amplifier saturated, thus the steepness of switch rising edge is improve by the saturated mode of amplifier, decrease the periodicity triggering moment critical amplitude, the clock signal triggering initial time is made to obtain consistent identification in each passage, effectively overcome the error effect that A/D sampling reference position clock jitter brings, the clock of multi-channel data acquisition unit is made to be fully operational in synchronous regime, achieve the synchronous of multi-path data acquiring system, thus make synchronous device of the present invention and method have low jitter, characteristic inclined time low.
Particularly, high-speed parallel acquisition system clock synchronization apparatus disclosed by the invention, mainly comprises:
One two-way power division network, export in order to clock signal of system is divided into two-way, one tunnel to the sampling clock of signal condition unit as A/D unit, another road to the Clock management chip of FPGA input end on A/D plate, as the work clock (when needing) of FPGA;
One signal condition unit, for regulating the amplitude of the high-speed clock signal inputted by two-way power division network, was increased to the amplitude of this clock signal the degree making the amplifying unit of rear class saturated before switch element control signal is arrived;
One switch element, for controlling the break-make of the clock signal from signal condition unit, and then the initial sum cut-off time of control A/D element circuit sampling;
One amplifying unit, is used for the amplitude of preceding clock signal to output to suitable level on the one hand, and operate in saturation, improve the steepness of on-off circuit rising edge/negative edge, on the other hand, this clock signal is converted to differential signal from single-ended signal, meets the requirement of A/D difference sampling clock.
Two multichannel power division networks, the differential clock signal for amplifying unit is exported is divided into constant amplitude homophase, on all four multipath output signals, meets the request for utilization of rear class multichannel data acquisition system, and two multichannel power division network magnitude-phase characteristics are completely the same;
One electricity supply and control unit, for providing power supply needed for above-mentioned each element circuit and control signal.
Wherein, the input signal of amplifying unit is controlled by the switch element of prime, and its output amplitude meets the power level requirement of follow-up hyperchannel A/D unit sampling clock, exports phase place and meets the differential phase requirement that two-way differs 180 °.
Wherein, two multichannel power division networks complete the power dividing function of preceding clock signal, and multiple output terminal need meet amplitude, phase place is completely the same, have the isolation of more than 20dB each other, and the insertion loss introduced requirement such as little grade as far as possible.
Below in synthetic-aperture radar (SAR) from the clock synchronization apparatus that grinds at double channel data acquisition systematic difference, be specifically described.
The double channel data acquisition system of the present embodiment need complete the wideband IF signal sampling of centre frequency 1.5 ± 0.4GHz, and the requirement of sample frequency is as shown in the table:
Table 1 sampling clock index request
| Sequence number | Project | Index |
| 1 | Incoming frequency | 2GHz |
| 2 | Power input | 15dBm |
| 3 | Differential ends output power | ≥1dBm |
| 4 | Differential ends phase error | ≤2° |
Fig. 2 is the circuit diagram of the synchronous device as one embodiment of the invention, mainly comprises in figure: the first electric capacity C1, the second electric capacity C2, the 3rd electric capacity C3, the 4th electric capacity C4, the 5th electric capacity C5, the first power splitter PD1, the second power splitter PD2, the 3rd power splitter PD3, signal condition unit GC1, switch element S1, amplifying unit AMP1, power supply and control module.
First electric capacity C1, the second electric capacity C2, the 3rd electric capacity C3, the 4th electric capacity C4, the 5th electric capacity C5 play coupling in circuit, require to have good magnitude-phase characteristics at clock frequency place.For the sample frequency of 2GHz in embodiment, the high frequency capacitance of 100pF is selected to meet request for utilization.
Signal condition unit GC is mainly used in the amplitude size regulating clock signal, can realize, also can realize with fixed attenuator with voltage-controlled attenuator.In the present embodiment, the attenuation network selecting π type fixed resistance to form, regulates signal amplitude.
Switch element S1 is for controlling the break-make of clock signal, and then the initial sum cut-off time of control A/D circuit sampling, its characteristic needs reliable and stable, the SW-311 of M/A COM Inc. of the U.S. can be selected, or the HE-118 that domestic electricity Ke group 13 of alternative model China produces, the two frequency of operation all can arrive 3GHz, and all have employed GaASMMIC technique, and be integrated with TTL driver at chip internal, control level and TTL/CMOS level compatibility, have high switching speed (ns level) and extremely low insertion loss.Difference is not had, final choice home products through both verification experimental verifications test effect.
Amplifying unit AMP1 requires to be used for clock signal amplitude to output to suitable level on the one hand, and operate in saturation, improve the steepness of on-off circuit rising edge/negative edge, on the other hand, the single-ended signal of clock signal is converted to differential signal, meets the requirement of A/D difference sampling clock.Owing to requiring higher to amplifying unit, select the ADL5565 differential amplifier of ADI company of the U.S. here, the highest frequency of this amplifier can arrive 6GHz, and has high Slew Rate and extremely wide dynamic range, can realize the conversion of single-ended-to-difference.
First power splitter PD1, the second power splitter PD2, the 3rd power splitter PD3 are the power division to signal, latter two power splitter requires higher to amplitude-phase consistency, because three's frequency of operation is identical, here 0 ° of power splitter GP-2Y+ of mini-circuits company of the U.S. is all selected, this device has good amplitude-phase consistency and good isolation at below 3.3GHz, and volume is very little, is beneficial to miniaturization and realizes.
Electricity supply and control unit is for providing power supply needed for above-mentioned each element circuit and control signal, comprise+the 5V of amplifying unit,-the 5V of switch element, the TTL control signal of switch element, totally three road signals, wherein+5V power supply and switch controlling signal are directly provided by signal generation system, control signal need be synchronous with the trigger instants of signal generation unit, and-5V power supply is converted by+5V, select the PTN04050A power supply changeover device of American TI Company, realize the efficient conversion of+5V to-5V, this power acquisition is used without pin configuration, there is very little volume and very high reliability.
Fig. 4 is clock signal waveform figure, and wherein Fig. 4 (a) is the oscillogram of 2GHz clock signal only after switch, and Fig. 4 (b) is the oscillogram of this signal after this synchronous device.As can be seen from Fig. 4 (b), after this synchronous device, the clock rise time significantly reduces, except one-period is less, second period signal has obviously reached in range of normal value, such first periodic signal below the threshold value of A/D sample frequency amplitude, from second period, each road acquisition system starts normal work, and synchronism is well ensured.Amplitude, phase diagram that Fig. 4 (c) is this synchronous device difference port, recorded by AgilentN5244A vector network analyzer, upper as can be seen from figure, 2GHz signal differential end phase differential 178.72 °, amplitude difference 0.01dB, closely ideal value.
Signal condition unit GC1, for regulating the amplitude size of input clock signal, can use voltage-controlled attenuator, and also can replace with fixed attenuator, the latter is more simple and quick.
In addition, amplifying unit AMP1 can adopt differential amplifier, also can use single-ended amplifier to replace, determine according to A/D unit the need of difference sampling clock.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a high-speed parallel acquisition system clock synchronization apparatus, described high-speed parallel acquisition system clock synchronization apparatus is by configuration signal conditioning unit, clock input range scope is set, before switching means conductive, signal amplitude is brought up to the degree being enough to make post-amplifier saturated, make the clock signal triggering initial time obtain consistent identification in each passage, realize the synchronous of multi-path data acquiring system.
2. a high-speed parallel acquisition system clock synchronization apparatus, comprising:
One signal condition unit, for regulating the amplitude of the clock signal of input, was increased to the amplitude of described clock signal the degree making the amplifying unit of rear class saturated before switch element control signal is arrived;
One switch element, for controlling the break-make of the clock signal from signal condition unit, and then the initial sum cut-off time of control A/D element circuit sampling;
One amplifying unit, be used on the one hand controlling, when connecting, the amplitude of the described clock signal from described switch element is outputted to suitable level at described switch element, and operate in saturation, improve the steepness of on-off circuit rising edge/negative edge, on the other hand, for described clock signal is converted to differential signal from single-ended signal, meet the requirement of A/D difference sampling clock.
3. high-speed parallel acquisition system clock synchronization apparatus as claimed in claim 2, the amplitude of the output signal of wherein said amplifying unit meets the power level requirement of follow-up hyperchannel A/D unit sampling clock, exports phase place and meets the differential phase requirement that two-way differs 180 °.
4. high-speed parallel acquisition system clock synchronization apparatus as claimed in claim 2, wherein said high-speed parallel acquisition system clock synchronization apparatus also comprises two multichannel power division networks, differential clock signal for described amplifying unit is exported is divided into constant amplitude homophase, on all four multipath output signals, meet the request for utilization that rear class hyperchannel A/D cell data gathers, and the magnitude-phase characteristics of two described multichannel power division networks is completely the same.
5. high-speed parallel acquisition system clock synchronization apparatus as claimed in claim 4, when wherein said two multichannel power division networks complete the power dividing function of described clock signal, multiple output terminal meets more than 20dB isolation each other, and the requirement that the insertion loss introduced is as far as possible little.
6. a high-speed parallel acquisition system clock synchronizing method, comprises the following steps:
Configuration signal conditioning unit, clock input range scope is set, before switching means conductive, signal amplitude is brought up to the degree being enough to make post-amplifier saturated, make the clock signal triggering initial time obtain consistent identification in each passage, thus realize the synchronous of multi-path data acquiring system.
7. a high-speed parallel acquisition system clock synchronizing method, comprises the following steps:
Regulate the amplitude being input to the clock signal of signal condition unit, before switch element control signal is arrived, the amplitude of described clock signal is increased to the degree making the amplifying unit of rear class saturated;
Control the break-make from the clock signal of signal condition unit, and then the initial sum cut-off time of control A/D element circuit sampling;
Control, when connecting, the amplitude of the described clock signal from described switch element is outputted to suitable level at described switch element, and operate in saturation, improve the steepness of on-off circuit rising edge/negative edge;
Described clock signal is converted to differential signal from single-ended signal, meets the requirement of A/D difference sampling clock.
8. high-speed parallel acquisition system clock synchronizing method as claimed in claim 7, the amplitude of the output signal of wherein said amplifying unit meets the power level requirement of follow-up hyperchannel A/D unit sampling clock, exports phase place and meets the differential phase requirement that two-way differs 180 °.
9. high-speed parallel acquisition system clock synchronizing method as claimed in claim 7, wherein said high-speed parallel acquisition system clock synchronization apparatus also comprises two multichannel power division networks, differential clock signal for described amplifying unit is exported is divided into constant amplitude homophase, on all four multipath output signals, meet the request for utilization that rear class hyperchannel A/D cell data gathers, and the magnitude-phase characteristics of two described multichannel power division networks is completely the same.
10. high-speed parallel acquisition system clock synchronizing method as claimed in claim 9, when wherein said two multichannel power division networks complete the power dividing function of described clock signal, multiple output terminal meets more than 20dB isolation each other, and the requirement that the insertion loss introduced is as far as possible little.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108616279A (en) * | 2016-12-12 | 2018-10-02 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of low jitter multichannel intermediate-freuqncy signal acquisition clock circuit |
| CN109194332A (en) * | 2018-08-22 | 2019-01-11 | 电子科技大学 | A kind of 40GSPS acquisition system signal drive circuit of four-way input |
| CN114019364A (en) * | 2021-11-05 | 2022-02-08 | 上海创远仪器技术股份有限公司 | Method, device, processor and storage medium for realizing measurement of on-off time of radio frequency switch based on vector network analyzer structure |
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| CN105094014A (en) * | 2015-07-30 | 2015-11-25 | 中国科学院电子学研究所 | High-speed parallel D/A clock synchronization apparatus |
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| CN101846739A (en) * | 2010-04-29 | 2010-09-29 | 河海大学 | Mixed domain emulation method of SAR (Synthetic Aperture Radar) extended scene primary data |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108616279A (en) * | 2016-12-12 | 2018-10-02 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of low jitter multichannel intermediate-freuqncy signal acquisition clock circuit |
| CN109194332A (en) * | 2018-08-22 | 2019-01-11 | 电子科技大学 | A kind of 40GSPS acquisition system signal drive circuit of four-way input |
| CN109194332B (en) * | 2018-08-22 | 2021-06-04 | 电子科技大学 | Four-channel input 40GSPS acquisition system signal driving circuit |
| CN114019364A (en) * | 2021-11-05 | 2022-02-08 | 上海创远仪器技术股份有限公司 | Method, device, processor and storage medium for realizing measurement of on-off time of radio frequency switch based on vector network analyzer structure |
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