CN114019364A - Method, device, processor and storage medium for realizing measurement of on-off time of radio frequency switch based on vector network analyzer structure - Google Patents
Method, device, processor and storage medium for realizing measurement of on-off time of radio frequency switch based on vector network analyzer structure Download PDFInfo
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Abstract
The invention relates to a method for realizing on-off time measurement of a radio frequency switch based on a vector network analyzer structure, which comprises the steps of setting an external trigger signal; the vector network analyzer receives an external trigger signal, and the ADC module starts to sample the clock frequency; carrying out digital frequency mixing on the switch stabilization time or the switch off time and a digital local oscillator respectively to obtain two paths of I/Q signals; and performing filtering processing to calculate an amplitude value. The invention also relates to a device for realizing the measurement of the on-off time of the radio frequency switch based on the vector network analyzer structure, a processor and a computer readable storage medium. By adopting the method, the device, the processor and the computer readable storage medium for realizing the measurement of the on-off time of the radio frequency switch based on the structure of the vector network analyzer, the indexes such as the isolation degree, the insertion loss and the like before or after the switch is opened or closed can be measured by utilizing the large dynamic range of the vector network analyzer, the operation is convenient and simple, the curve from the buffering to the stabilization of the switch can be seen, and the performances of various types of switches can be visually compared.
Description
Technical Field
The invention relates to the technical field of test and measurement, in particular to the field of a vector network analyzer, and specifically relates to a method, a device, a processor and a computer readable storage medium for realizing on-off time measurement of a radio frequency switch based on a vector network analyzer structure.
Background
Due to the working characteristics of the switch, the switch can be kept stable after being electrified and opened for a period of time after being buffered, and the shorter the time from opening to stability, the faster the switching speed is, and the better the performance is. Therefore, it is very important to accurately measure the on-off delay time of the switch.
The method for measuring the on-off delay time of the switch in the prior art is to measure the on-off waveform of the switch by using an oscilloscope and calculate the on-off time of the switch through a waveform curve. The traditional measuring method has more defects, which are specifically represented as follows:
the results are not accurate enough: due to limitations of oscilloscopes, such as:
1. most oscilloscopes cannot display the change of power along with time, so the test method has large error and inaccurate test result;
2. the oscilloscope does not have a radio frequency source as an input signal of the switch;
3. when testing the high-frequency switch, external local oscillators, mixers and the like are needed, and the method has the defects of complexity and easy error of external equipment.
Therefore, the method of using the oscilloscope to measure the switch has many defects, complex process and inaccurate result.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a method, a device, a processor and a computer readable storage medium for realizing the measurement of the on-off time of a radio frequency switch based on a vector network analyzer structure, which have the advantages of high precision, simple and convenient operation and wider application range.
In order to achieve the above object, the method, the apparatus, the processor and the computer readable storage medium for measuring the on-off time of the radio frequency switch based on the structure of the vector network analyzer of the present invention are as follows:
the method for realizing the measurement of the on-off time of the radio frequency switch based on the structure of the vector network analyzer is mainly characterized by comprising the following steps of:
(1) setting an external trigger signal as an input trigger signal of the vector network analyzer and a control signal of a switch to be tested;
(2) the vector network analyzer receives an external trigger signal, the ADC module starts to sample clock frequency, and the switch to be tested is switched on or off according to the external trigger signal;
(3) the vector network analyzer receives the sampling data, and digitally mixes the switch stabilization time or the switch off time with a digital local oscillator respectively to obtain two paths of signals I/Q;
(4) and filtering the two paths of I/Q signals through an FIR low-pass filter, transmitting the signals to a digital signal processor, calculating an amplitude value according to the I/Q data, and displaying the data of each sampling point by an upper computer in a waveform curve form.
Preferably, the step (3) specifically includes the following steps:
(3.1) mixing the local oscillation signal and the radio frequency signal to obtain intermediate frequency data;
(3.2) filtering the intermediate frequency data through an anti-aliasing filter, carrying out A/D sampling, and transmitting the intermediate frequency data to the FPGA through a low-voltage differential signal;
and (3.3) carrying out digital down-conversion to convert the digital intermediate frequency to zero intermediate frequency so as to obtain two paths of signals I/Q.
Preferably, the step (4) specifically includes the following steps:
(4.1) filtering the I/Q signals by an FIR filter;
(4.2) reading the data passing through the FIR filter by using a digital signal processor, converting the data into a power value representing the amplitude, and transmitting the power value to an upper computer;
and (4.3) the upper computer displays the data of each sampling point in a wave curve form.
Preferably, the a/D sampling in step (3.2) is specifically:
the sampling rate of the a/D samples is obtained according to the following equation:
fs＝(4f0)/(2n+1)；
fs>＝2B；
wherein f issFor the sampling rate, B is the bandwidth of the intermediate frequency signal, f0At an intermediate frequency.
Preferably, the step (4.2) specifically comprises the following steps:
the data passing through the FIR filter is stored in a first-in first-out memory;
and reading and converting the power value into a power value representing the amplitude through a digital signal processor and transmitting the power value to an upper computer.
Preferably, the ADC module in step (2) samples a clock frequency, and the measurement accuracy of the on-off time of the radio frequency switch is improved by increasing the clock frequency.
This device based on vector network analyzer structure realizes radio frequency switch on-off time measurement, its key feature is, the device include:
a processor configured to execute computer-executable instructions;
and the memory stores one or more computer executable instructions, and when the computer executable instructions are executed by the processor, the steps of the method for realizing the measurement of the on-off time of the radio frequency switch based on the structure of the vector network analyzer are realized.
The processor for realizing the measurement of the on-off time of the radio frequency switch based on the vector network analyzer structure is mainly characterized in that the processor is configured to execute computer executable instructions, and when the computer executable instructions are executed by the processor, the steps of the method for realizing the measurement of the on-off time of the radio frequency switch based on the vector network analyzer structure are realized.
The computer readable storage medium is mainly characterized in that a computer program is stored on the computer readable storage medium, and the computer program can be executed by a processor to realize the steps of the method for realizing the measurement of the on-off time of the radio frequency switch based on the structure of the vector network analyzer.
By adopting the method, the device, the processor and the computer readable storage medium for realizing the measurement of the on-off time of the radio frequency switch based on the structure of the vector network analyzer, the indexes such as the isolation degree, the insertion loss and the like before or after the switch is opened or closed can be measured by utilizing the large dynamic range of the vector network analyzer, when the switch is tested, the connection is carried out as required, other complicated operations are not needed, the convenience and the simplicity are realized, the curve from the buffering to the stabilization of the switch can be seen, and the performances of various types of switches can be visually compared.
Drawings
Fig. 1 is a schematic diagram of the working principle of the method for measuring the on-off time of the radio frequency switch based on the structure of the vector network analyzer.
Fig. 2 is a schematic flow chart of a method for measuring the on-off time of the radio frequency switch based on the structure of the vector network analyzer.
Fig. 3 is a schematic diagram of a direct FIR filter of the present invention.
Fig. 4 is a schematic waveform diagram of an oscilloscope measurement switch according to an embodiment of the present invention.
Fig. 5 is a schematic diagram of a waveform curve of a structure-measuring switch according to an embodiment of the present invention.
Detailed Description
In order to more clearly describe the technical contents of the present invention, the following further description is given in conjunction with specific embodiments.
The invention discloses a method for realizing the measurement of the on-off time of a radio frequency switch based on a vector network analyzer structure, which comprises the following steps:
(1) setting an external trigger signal as an input trigger signal of the vector network analyzer and a control signal of a switch to be tested;
(2) the vector network analyzer receives an external trigger signal, the ADC module starts to sample clock frequency, and the switch to be tested is switched on or off according to the external trigger signal;
(3) the vector network analyzer receives the sampling data, and digitally mixes the switch stabilization time or the switch off time with a digital local oscillator respectively to obtain two paths of signals I/Q;
(4) and filtering the two paths of I/Q signals through an FIR low-pass filter, transmitting the signals to a digital signal processor, calculating an amplitude value according to the I/Q data, and displaying the data of each sampling point by an upper computer in a waveform curve form.
As a preferred embodiment of the present invention, the step (3) specifically comprises the following steps:
(3.1) mixing the local oscillation signal and the radio frequency signal to obtain intermediate frequency data;
(3.2) filtering the intermediate frequency data through an anti-aliasing filter, carrying out A/D sampling, and transmitting the intermediate frequency data to the FPGA through a low-voltage differential signal;
and (3.3) carrying out digital down-conversion to convert the digital intermediate frequency to zero intermediate frequency so as to obtain two paths of signals I/Q.
As a preferred embodiment of the present invention, the step (4) specifically comprises the following steps:
(4.1) filtering the I/Q signals by an FIR filter;
(4.2) reading the data passing through the FIR filter by using a digital signal processor, converting the data into a power value representing the amplitude, and transmitting the power value to an upper computer;
and (4.3) the upper computer displays the data of each sampling point in a wave curve form.
As a preferred embodiment of the present invention, the step (3.2) performs a/D sampling, specifically:
the sampling rate of the a/D samples is obtained according to the following equation:
fs＝(4f0)/(2n+1)；
fs>＝2B；
wherein f issFor the sampling rate, B is the bandwidth of the intermediate frequency signal, f0At an intermediate frequency.
As a preferred embodiment of the present invention, the step (4.2) specifically comprises the following steps:
the data passing through the FIR filter is stored in a first-in first-out memory;
and reading and converting the power value into a power value representing the amplitude through a digital signal processor and transmitting the power value to an upper computer.
As a preferred embodiment of the present invention, in the step (2), the ADC module samples a clock frequency, and the measurement accuracy of the on-off time of the radio frequency switch is improved by increasing the clock frequency.
The invention relates to a device for realizing the measurement of the on-off time of a radio frequency switch based on a vector network analyzer structure, wherein the device comprises:
a processor configured to execute computer-executable instructions;
and the memory stores one or more computer executable instructions, and when the computer executable instructions are executed by the processor, the steps of the method for realizing the measurement of the on-off time of the radio frequency switch based on the structure of the vector network analyzer are realized.
The processor for realizing the measurement of the on-off time of the radio frequency switch based on the vector network analyzer structure is configured to execute computer executable instructions, and when the computer executable instructions are executed by the processor, the steps of the method for realizing the measurement of the on-off time of the radio frequency switch based on the vector network analyzer structure are realized.
The computer readable storage medium of the present invention has stored thereon a computer program executable by a processor to perform the steps of the method for implementing the measurement of the on-off time of the rf switch based on the structure of the vector network analyzer described above.
In the embodiment of the invention, as shown in fig. 1, an external trigger signal is set and used as an input trigger signal of the vector network analyzer and a control signal of the switch to be tested, so that the sampling start time of the vector network analyzer is synchronous with the on-off start time of the switch.
The method for measuring the on-off time of the radio frequency switch based on the structure of the vector network analyzer comprises the following steps:
step 1: setting an external trigger signal which is simultaneously used as an input trigger signal of the vector network analyzer and a control signal of the switch to be tested, so that the sampling starting time of the vector network analyzer is synchronous with the on-off starting time of the switch;
step 2: after the vector network analyzer receives the edge of the trigger signal, the ADC module starts sampling, and the switch starts to be switched on or switched off at the signal edge;
and step 3: a sampling module of the vector network analyzer receives sampling data, the sampling time is longer than the predicted switch stabilization time or closing time, and digital frequency mixing is respectively carried out on the sampling data and a digital local oscillator with the same frequency and the same sampling frequency and the phase difference of 90 degrees, so that two paths of signals of I/Q are obtained;
and 4, step 4: and 3, after the high-frequency signals generated by digital mixing are respectively suppressed to an acceptable range through FIR low-pass filtering, the signals are sequentially transmitted to the DSP in sequence, the DSP processes the signals, calculates the I/Q data into an amplitude value representing power and transmits the amplitude value to upper computer software, and the upper computer can display the data of each sampling point in a waveform curve mode. The curve can visually show the specific process from buffering to stabilization of the switch or the stabilization time of the switch can be obtained by calculating the power change of each point in the power curve. The FPGA is a field programmable logic gate array, and the DSP is a digital signal processor.
The external trigger signal can be generated by a function signal generator or provided by other equipment, and only the amplitude, the offset, the frequency and the duty ratio can meet the requirements of a vector network analyzer and a switch at the same time.
ADC sampling clock frequency is FsCan be increased by increasing FsThe measurement precision of the on-off time of the radio frequency switch is improved.
In the digital down-conversion process, the digital local oscillator module fixes the output frequency to be f0＝Fs。
The data after FIR filtering is firstly cached in a memory due to high throughput rate, and then is uploaded to upper computer software through a communication link.
The upper computer software can flexibly configure the number of sampling points according to the requirement, and the trend of the curve is more visually displayed.
As shown in fig. 2, the local oscillator signal and the radio frequency signal are mixed and then transmitted to the intermediate frequency, and the intermediate frequency data is filtered by the anti-aliasing filter, a/D sampled and transmitted to the FPGA through the low voltage differential signal.
Sampling rate of A/DThe bandpass sampling theorem should be satisfied, and the sampling rate should be greater than or equal to twice the bandwidth of the intermediate frequency signal: f. ofs>2B and satisfies fs＝(4f0) V. (2n +1), where fsIs the sampling rate, B is the bandwidth of the intermediate frequency signal, f0At an intermediate frequency.
And after the intermediate frequency data is subjected to digital down-conversion, the digital intermediate frequency is down-converted to zero intermediate frequency to obtain orthogonal I/Q data so as to facilitate the processing of subsequent baseband signals.
The digital down-conversion mainly comprises orthogonal transformation and a low-pass filter, and the intermediate frequency data is multiplied by two paths of orthogonal local oscillation signals generated by a digital controlled oscillator to obtain two paths of I/Q signals.
The FIR filtering refers to filtering processing by an FIR filter, which is called a finite long single-bit impulse response filter for short and is a non-recursive filter. An FIR filter with constant coefficients is an LTI (linear time invariant) digital filter. The relationship between the output of the FIR of length N and the input time sequence x (N) is given by a finite convolution sum, which is as follows:
as shown in fig. 3, is a diagram of a direct type FIR filter. Expressed is an N-1 order FIR filter with N taps (coefficients). Therefore, the system consists of N multipliers and N-1 accumulators.
The DSP refers to data filtered by the FIR filter, the data are stored in a first-in first-out memory, and then the data are read by the DSP, converted into power values representing amplitudes and transmitted to an upper computer according to a certain format.
The upper computer waveform curve display means that data transmitted to the upper computer by the DSP visually displays the overall trend in the form of a waveform curve through software.
As shown in fig. 4, the waveform is obtained by testing the on/off of the switch with an oscilloscope. Where the purple curve represents the external trigger signal and the yellow curve represents the switch from conduction to stable waveform. And the time from the cursor A to the cursor B is the on-off time of the radio frequency switch. It can be seen from the figure that, because the curve has a certain fluctuation, the specific stable state cannot be accurately judged, and therefore, the on-off time of the radio frequency switch obtained in this way has a certain measurement error.
As shown in fig. 5, the test switch is a measured switch, and a waveform curve is finally obtained through the whole system test process. The abscissa shows the number of sampling points, and it can be seen from the figure that after 727 points, the whole curve tends to be stable, i.e. the switch works stably. In the test process, the sampling clock of the ADC is 100MHz, and the sampling time of one point is 10ns, so the time for opening or closing the switch is 10 × 727 ═ 7270ns, that is, 7.27 us.
As can be seen from the actual measurement process and result of the same switch in fig. 4 and 5, the operation and debugging are complicated when the oscilloscope is used for testing, the accuracy of the oscilloscope is insufficient, the change of the power along with the time cannot be displayed, and the time when the waveform curve is stable cannot be accurately positioned. When the scheme of the invention is used for measurement, the operation is convenient, the specific moment of opening or closing the switch can be accurately positioned through the power change curve graph of each sampling point, and the error of the result obtained by calculation is small.
The ADC sampling clock is F provided by FPGAsIf F issThe sampling interval time of each point is 10ns when the frequency is 100 MHz; if FsAt 1GHz, the sampling interval time for each point is 1 ns. Therefore, the shorter the sampling point time interval is, the higher the measurement accuracy is.
For a specific implementation of this embodiment, reference may be made to the relevant description in the above embodiments, which is not described herein again.
It is understood that the same or similar parts in the above embodiments may be mutually referred to, and the same or similar parts in other embodiments may be referred to for the content which is not described in detail in some embodiments.
It should be noted that the terms "first," "second," and the like in the description of the present invention are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Further, in the description of the present invention, the meaning of "a plurality" means at least two unless otherwise specified.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and alternate implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.
It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by suitable instruction execution devices. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, and the corresponding program may be stored in a computer readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.
In addition, functional units in the embodiments of the present invention may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a separate product, may also be stored in a computer readable storage medium.
The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
By adopting the method, the device, the processor and the computer readable storage medium for realizing the measurement of the on-off time of the radio frequency switch based on the structure of the vector network analyzer, the indexes such as the isolation degree, the insertion loss and the like before or after the switch is opened or closed can be measured by utilizing the large dynamic range of the vector network analyzer, when the switch is tested, the connection is carried out as required, other complicated operations are not needed, the convenience and the simplicity are realized, the curve from the buffering to the stabilization of the switch can be seen, and the performances of various types of switches can be visually compared.
In this specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Claims (9)
1. A method for realizing on-off time measurement of a radio frequency switch based on a vector network analyzer structure is characterized by comprising the following steps:
(1) setting an external trigger signal as an input trigger signal of the vector network analyzer and a control signal of a switch to be tested;
(2) the vector network analyzer receives an external trigger signal, the ADC module starts to sample clock frequency, and the switch to be tested is switched on or off according to the external trigger signal;
(3) the vector network analyzer receives the sampling data, and digitally mixes the switch stabilization time or the switch off time with a digital local oscillator respectively to obtain two paths of signals I/Q;
(4) and filtering the two paths of I/Q signals through an FIR low-pass filter, transmitting the signals to a digital signal processor, calculating an amplitude value according to the I/Q data, and displaying the data of each sampling point by an upper computer in a waveform curve form.
2. The method for realizing the measurement of the on-off time of the radio frequency switch based on the vector network analyzer structure according to claim 1, wherein the step (3) specifically comprises the following steps:
(3.1) mixing the local oscillation signal and the radio frequency signal to obtain intermediate frequency data;
(3.2) filtering the intermediate frequency data through an anti-aliasing filter, carrying out A/D sampling, and transmitting the intermediate frequency data to the FPGA through a low-voltage differential signal;
and (3.3) carrying out digital down-conversion to convert the digital intermediate frequency to zero intermediate frequency so as to obtain two paths of signals I/Q.
3. The method for realizing the measurement of the on-off time of the radio frequency switch based on the vector network analyzer structure according to claim 1, wherein the step (4) specifically comprises the following steps:
(4.1) filtering the I/Q signals by an FIR filter;
(4.2) reading the data passing through the FIR filter by using a digital signal processor, converting the data into a power value representing the amplitude, and transmitting the power value to an upper computer;
and (4.3) the upper computer displays the data of each sampling point in a wave curve form.
4. The method for realizing the measurement of the on-off time of the radio frequency switch based on the vector network analyzer structure of claim 2, wherein the step (3.2) is performed with a/D sampling, specifically:
the sampling rate of the a/D samples is obtained according to the following equation:
fs＝(4f0)/(2n+1)；
fs>＝2B；
wherein f issFor the sampling rate, B is the bandwidth of the intermediate frequency signal, f0At an intermediate frequency.
5. The method for realizing the measurement of the on-off time of the radio frequency switch based on the vector network analyzer structure according to claim 3, wherein the step (4.2) specifically comprises the following steps:
the data passing through the FIR filter is stored in a first-in first-out memory;
and reading and converting the power value into a power value representing the amplitude through a digital signal processor and transmitting the power value to an upper computer.
6. The method for realizing the measurement of the on-off time of the radio frequency switch based on the vector network analyzer structure of claim 1, wherein the ADC module in the step (2) samples the clock frequency, and the measurement precision of the on-off time of the radio frequency switch is improved by improving the clock frequency.
7. A device for realizing on-off time measurement of a radio frequency switch based on a vector network analyzer structure is characterized by comprising:
a processor configured to execute computer-executable instructions;
a memory storing one or more computer-executable instructions that, when executed by the processor, perform the steps of the method of implementing radio frequency switch on-off time measurement based on a vector network analyzer structure of any one of claims 1 to 6.
8. A processor for implementing rf switch on-off time measurement based on a vector network analyzer structure, wherein the processor is configured to execute computer executable instructions, and when the computer executable instructions are executed by the processor, the processor implements the steps of the method for implementing rf switch on-off time measurement based on a vector network analyzer structure according to any one of claims 1 to 6.
9. A computer-readable storage medium having stored thereon a computer program executable by a processor to perform the steps of the method of any one of claims 1 to 6 for performing rf switch on-off time measurement based on a vector network analyzer architecture.
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