CN105099659A - Right-oblique chaotic system with folded attractor and circuit - Google Patents
Right-oblique chaotic system with folded attractor and circuit Download PDFInfo
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- CN105099659A CN105099659A CN201510551256.6A CN201510551256A CN105099659A CN 105099659 A CN105099659 A CN 105099659A CN 201510551256 A CN201510551256 A CN 201510551256A CN 105099659 A CN105099659 A CN 105099659A
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Abstract
The invention relates to a chaotic system and a circuit, and in particular relates to a right-oblique chaotic system with a folded attractor and a circuit. Typical chaotic systems, such as a Luorenz system, a Chen system and a Lu system, have three balance points, wherein one is a zero balance point; another two are non-zero balance points; the systems have two nonlinear terms; and the attractor generated by this kind of systems is a double-wing attractor. A three-dimensional chaotic system only having one nonlinear term is provided by the invention; the chaotic system is the right-oblique chaotic system capable of generating the folded attractor; the type of the chaotic system is increased; and a new choice is provided for applying the chaotic system in engineering practices.
Description
Technical field
The present invention relates to a kind of chaos system and circuit, particularly a kind of Right deviation chaos system containing folding attractor and circuit.
Background technology
Typical chaos system such as Lorenz system, Chen system and Lu system all have three balance points, one is wherein had to be zero balancing point, another two is non-zero balancing point, there are two nonlinear terms, the attractor that this type systematic produces is double-wing chaotic attractor, the present invention proposes the three-dimensional chaotic system that only has nonlinear terms, this chaos system is a Right deviation chaos system that can produce containing folding attractor, add the type of chaos system, provide a kind of selection newly for chaos system is applied to engineering practice.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of Right deviation chaos system containing folding attractor and circuit, and the present invention adopts following technological means to realize goal of the invention:
1, containing a Right deviation chaos system for folding attractor, it is characterized in that:
In i formula, a, b, c, d, e are parameter;
Work as a=0.2, when b=5, c=0, d=1, e=0.3, system i is:
System ii is a kind of Right deviation chaos system containing folding attractor.
2, a kind of Right deviation chaos system circuit containing folding attractor, it is characterized in that: according to Mathematical Modeling ii constructing analog circuit, operational amplifier U1, operational amplifier U2, operational amplifier U3 and resistance and electric capacity is utilized to form anti-phase adder and anti-phase fractional order integrator, multiplier U4 and multiplier U5 realizes multiplying, described operational amplifier U1, operational amplifier U2 and operational amplifier U3 adopt LF347N, multiplier U4 and multiplier U5 to adopt AD633JN;
Described operational amplifier U1 concatenation operation amplifier U2 and operational amplifier U3, described operational amplifier U2 concatenation operation amplifier U1, multiplier U4 and multiplier U5, described operational amplifier U3 connects multiplier U4 and multiplier U5, described multiplier U4 concatenation operation amplifier U2, described multiplier U5 concatenation operation amplifier U3;
The 1st of described operational amplifier U1, 2 pins are unsettled, 3rd, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin is connected with the 7th pin by resistance R12, 7th pin meets output-x, connected with the 13rd pin of operational amplifier U1 by resistance R19, connected with the 13rd pin of operational amplifier U2 by resistance R4, connected with the 13rd pin of operational amplifier U3 by resistance R18, 8th pin connects and exports x, connected with the 6th pin of operational amplifier U1 by resistance R11, 9th pin is connected with the 8th pin by electric capacity C1, 13rd pin is connected with the 14th pin by resistance R9, 14th pin is connected with 9 pins by resistance R10,
The 1st of described operational amplifier U2, 2 pins are unsettled, 3rd, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin is connected with the 7th pin by resistance R31, 7th pin meets output-y, connect the 1st pin of multiplier U5, 8th pin connects and exports y, connect the 3rd pin of multiplier U4, connected with the 13rd pin of operational amplifier U1 by resistance R2, connected with the 13rd pin of operational amplifier U2 by resistance R1, connected with the 6th pin of operational amplifier U2 by resistance R30, 9th pin is connected with the 8th pin by electric capacity C2, 13rd pin completes is crossed resistance R5 and is connected with the 14th pin, 14th pin is connected with the 9th pin by resistance R3,
The 1st of described operational amplifier U3, 2 pins are unsettled, 3rd, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin is connected with the 7th pin by resistance R14, 7th pin meets output-z, connected with the 13rd pin of operational amplifier U3 by resistance R8, 8th pin connects and exports z, connect the 1st pin of multiplier U4, connect the 3rd pin of multiplier U5, connected with the 6th pin of operational amplifier U3 by resistance R13, 9th pin is connected with the 8th pin by electric capacity C3, 13rd pin completes is crossed resistance R15 and is connected with the 14th pin, 14th pin is connected with the 9th pin by resistance R16,
The equal ground connection of 2nd, 4,6 pin of described multiplier U4, the 5th pin meets VEE, and the 7th pin is connected with operational amplifier U2 the 13rd pin by resistance R17, and the 8th pin meets VCC;
The equal ground connection of 2nd, 4,6 pin of described multiplier U5, the 5th pin meets VEE, and the 7th pin is connected with the 13rd pin of operational amplifier U3 by resistance R7, and the 8th pin meets VCC.
Useful fruit of the present invention is: propose a kind of Right deviation chaos system containing folding attractor, add the type of chaos system, provide a kind of selection newly for chaos system is applied to engineering practice.
Accompanying drawing explanation
Fig. 1 is circuit structure block diagram of the present invention.
Fig. 2 is the actual connection layout of circuit of U1 of the present invention.
Fig. 3 is the actual connection layout of circuit of U2 and U4 of the present invention.
Fig. 4 is the actual connection layout of circuit of U3 and U5 of the present invention.
Fig. 5 is the phasor in y-z direction of the present invention.
Embodiment
Below in conjunction with accompanying drawing and preferred embodiment, the present invention is further described in detail, see Fig. 1-Fig. 5.
1, containing a Right deviation chaos system for folding attractor, it is characterized in that:
In i formula, a, b, c, d, e are parameter;
Work as a=0.2, when b=5, c=0, d=1, e=0.3, system i is:
System ii is a kind of Right deviation chaos system containing folding attractor.
2, a kind of Right deviation chaos system circuit containing folding attractor, it is characterized in that: according to Mathematical Modeling ii constructing analog circuit, operational amplifier U1, operational amplifier U2, operational amplifier U3 and resistance and electric capacity is utilized to form anti-phase adder and anti-phase fractional order integrator, multiplier U4 and multiplier U5 realizes multiplying, described operational amplifier U1, operational amplifier U2 and operational amplifier U3 adopt LF347N, multiplier U4 and multiplier U5 to adopt AD633JN;
Described operational amplifier U1 concatenation operation amplifier U2 and operational amplifier U3, described operational amplifier U2 concatenation operation amplifier U1, multiplier U4 and multiplier U5, described operational amplifier U3 connects multiplier U4 and multiplier U5, described multiplier U4 concatenation operation amplifier U2, described multiplier U5 concatenation operation amplifier U3;
The 1st of described operational amplifier U1, 2 pins are unsettled, 3rd, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin is connected with the 7th pin by resistance R12, 7th pin meets output-x, connected with the 13rd pin of operational amplifier U1 by resistance R19, connected with the 13rd pin of operational amplifier U2 by resistance R4, connected with the 13rd pin of operational amplifier U3 by resistance R18, 8th pin connects and exports x, connected with the 6th pin of operational amplifier U1 by resistance R11, 9th pin is connected with the 8th pin by electric capacity C1, 13rd pin is connected with the 14th pin by resistance R9, 14th pin is connected with 9 pins by resistance R10,
The 1st of described operational amplifier U2, 2 pins are unsettled, 3rd, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin is connected with the 7th pin by resistance R31, 7th pin meets output-y, connect the 1st pin of multiplier U5, 8th pin connects and exports y, connect the 3rd pin of multiplier U4, connected with the 13rd pin of operational amplifier U1 by resistance R2, connected with the 13rd pin of operational amplifier U2 by resistance R1, connected with the 6th pin of operational amplifier U2 by resistance R30, 9th pin is connected with the 8th pin by electric capacity C2, 13rd pin completes is crossed resistance R5 and is connected with the 14th pin, 14th pin is connected with the 9th pin by resistance R3,
The 1st of described operational amplifier U3, 2 pins are unsettled, 3rd, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin is connected with the 7th pin by resistance R14, 7th pin meets output-z, connected with the 13rd pin of operational amplifier U3 by resistance R8, 8th pin connects and exports z, connect the 1st pin of multiplier U4, connect the 3rd pin of multiplier U5, connected with the 6th pin of operational amplifier U3 by resistance R13, 9th pin is connected with the 8th pin by electric capacity C3, 13rd pin completes is crossed resistance R15 and is connected with the 14th pin, 14th pin is connected with the 9th pin by resistance R16,
The equal ground connection of 2nd, 4,6 pin of described multiplier U4, the 5th pin meets VEE, and the 7th pin is connected with operational amplifier U2 the 13rd pin by resistance R17, and the 8th pin meets VCC;
The equal ground connection of 2nd, 4,6 pin of described multiplier U5, the 5th pin meets VEE, and the 7th pin is connected with the 13rd pin of operational amplifier U3 by resistance R7, and the 8th pin meets VCC.
Resistance R3=R5=R9=R10=R11=R12=R13=R14=R15=R16=R30=R31=10k Ω in circuit,
R7=R17=10K Ω, R1=R4=R8=100K Ω, R2=20K Ω, R19=200K Ω, R18=333.3K Ω, electric capacity C1=C2=C3=10nF in circuit.
Certainly, above-mentioned explanation is not limitation of the present invention, and the present invention is also not limited only to above-mentioned citing, and the change that those skilled in the art make in essential scope of the present invention, remodeling, interpolation or replacement, also belong to protection scope of the present invention.
Claims (2)
1., containing a Right deviation chaos system for folding attractor, it is characterized in that:
In i formula, a, b, c, d, e are parameter;
Work as a=0.2, when b=5, c=0, d=1, e=0.3, system i is:
System ii is a kind of Right deviation chaos system containing folding attractor.
2. the Right deviation chaos system circuit containing folding attractor, it is characterized in that: according to Mathematical Modeling ii constructing analog circuit, operational amplifier U1, operational amplifier U2, operational amplifier U3 and resistance and electric capacity is utilized to form anti-phase adder and anti-phase fractional order integrator, multiplier U4 and multiplier U5 realizes multiplying, described operational amplifier U1, operational amplifier U2 and operational amplifier U3 adopt LF347N, multiplier U4 and multiplier U5 to adopt AD633JN;
Described operational amplifier U1 concatenation operation amplifier U2 and operational amplifier U3, described operational amplifier U2 concatenation operation amplifier U1, multiplier U4 and multiplier U5, described operational amplifier U3 connects multiplier U4 and multiplier U5, described multiplier U4 concatenation operation amplifier U2, described multiplier U5 concatenation operation amplifier U3;
The 1st of described operational amplifier U1, 2 pins are unsettled, 3rd, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin is connected with the 7th pin by resistance R12, 7th pin meets output-x, connected with the 13rd pin of operational amplifier U1 by resistance R19, connected with the 13rd pin of operational amplifier U2 by resistance R4, connected with the 13rd pin of operational amplifier U3 by resistance R18, 8th pin connects and exports x, connected with the 6th pin of operational amplifier U1 by resistance R11, 9th pin is connected with the 8th pin by electric capacity C1, 13rd pin is connected with the 14th pin by resistance R9, 14th pin is connected with 9 pins by resistance R10,
The 1st of described operational amplifier U2, 2 pins are unsettled, 3rd, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin is connected with the 7th pin by resistance R31, 7th pin meets output-y, connect the 1st pin of multiplier U5, 8th pin connects and exports y, connect the 3rd pin of multiplier U4, connected with the 13rd pin of operational amplifier U1 by resistance R2, connected with the 13rd pin of operational amplifier U2 by resistance R1, connected with the 6th pin of operational amplifier U2 by resistance R30, 9th pin is connected with the 8th pin by electric capacity C2, 13rd pin completes is crossed resistance R5 and is connected with the 14th pin, 14th pin is connected with the 9th pin by resistance R3,
The 1st of described operational amplifier U3, 2 pins are unsettled, 3rd, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin is connected with the 7th pin by resistance R14, 7th pin meets output-z, connected with the 13rd pin of operational amplifier U3 by resistance R8, 8th pin connects and exports z, connect the 1st pin of multiplier U4, connect the 3rd pin of multiplier U5, connected with the 6th pin of operational amplifier U3 by resistance R13, 9th pin is connected with the 8th pin by electric capacity C3, 13rd pin completes is crossed resistance R15 and is connected with the 14th pin, 14th pin is connected with the 9th pin by resistance R16,
The equal ground connection of 2nd, 4,6 pin of described multiplier U4, the 5th pin meets VEE, and the 7th pin is connected with operational amplifier U2 the 13rd pin by resistance R17, and the 8th pin meets VCC;
The equal ground connection of 2nd, 4,6 pin of described multiplier U5, the 5th pin meets VEE, and the 7th pin is connected with the 13rd pin of operational amplifier U3 by resistance R7, and the 8th pin meets VCC.
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Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102916802A (en) * | 2012-09-27 | 2013-02-06 | 滨州学院 | Fractional-order automatic switching chaotic system method for four Lorenz type systems and analog circuit |
CN104811296A (en) * | 2015-05-27 | 2015-07-29 | 王春梅 | Method for building Lorenz super-chaos system beneficial for ultimate frontier estimation and circuit |
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Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102916802A (en) * | 2012-09-27 | 2013-02-06 | 滨州学院 | Fractional-order automatic switching chaotic system method for four Lorenz type systems and analog circuit |
CN104811296A (en) * | 2015-05-27 | 2015-07-29 | 王春梅 | Method for building Lorenz super-chaos system beneficial for ultimate frontier estimation and circuit |
Non-Patent Citations (1)
Title |
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刘崇新编著: "3.4.2 系统参数变化对系统影响的分析", 《分数阶混沌电路理论与应用》 * |
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