CN105097955B - 具有带一个浮动隔离的双隔离的晶体管 - Google Patents

具有带一个浮动隔离的双隔离的晶体管 Download PDF

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CN105097955B
CN105097955B CN201510266596.4A CN201510266596A CN105097955B CN 105097955 B CN105097955 B CN 105097955B CN 201510266596 A CN201510266596 A CN 201510266596A CN 105097955 B CN105097955 B CN 105097955B
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transistor
region
isolation region
metal layer
drain
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CN105097955A (zh
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Y·张
P·L·霍沃
S·P·彭德哈卡
J·林
G·马图尔
S·巴尔斯特
V·斯诺
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Texas Instruments Inc
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Abstract

一种半导体器件(200)包括至少第一晶体管(117)，该第一晶体管包含在第一级金属层上方的至少第二级金属层(第二金属层)(230)，该第一级金属层通过源极触头耦合到以第一掺杂剂类型掺杂的源极区(117b)。第二级金属层通过漏极触头耦合到以第一掺杂剂类型掺杂的漏极区(117d)。栅极堆叠(117c)在源极区和漏极区之间，使得第二级金属层通过触头与其耦合。第二级金属层通过触头耦合到以第二掺杂剂类型掺杂的第一隔离区域(117e)。源极区和漏极区在第一隔离区内。以第一掺杂剂类型掺杂的第二隔离区(117g)包围第一隔离区，并且不耦合到第二级金属层，从而其电浮动。

Description

具有带一个浮动隔离的双隔离的晶体管
技术领域
所公开的实施例涉及具有双结隔离的功率金属氧化物半导体(MOS)晶体管。
背景技术
与常规的对称MOS晶体管相比，不对称源极/漏极MOS晶体管(例如，漏极延伸MOS(DEMOS)或横向扩散MOS(LDMOS)晶体管)具有能够在更高的电压下工作的漏极结构。由DEMOS和LDMOS晶体管提供的较高工作电压能够在各种应用中使用，包括例如用于电机驱动，而使用常规的对称MOS晶体管一般是不可能的。
在典型的电机驱动应用中，电平移位电路耦合到高侧栅极驱动器，该高侧栅极驱动器使用脉冲宽度调制(PWM)信号驱动半桥电路的高侧晶体管的栅极，并且低侧栅极驱动器使用PWM互补信号驱动半桥电路的低侧晶体管的栅极。高侧栅极驱动器包括一对串联堆叠的LDMOS或DEMOS晶体管，其中高侧晶体管的高侧连接到被称为启动端/高压端(Boot)节点的节点，该节点在与VCC串联的二极管的阴极侧上，并且高侧栅极驱动器的低侧晶体管的低侧连接到半桥的开关(SW)节点，该SW节点处于高侧和低侧半桥晶体管之间的节点处。
LDMOS和DEMOS晶体管可以利用垂直结隔离。但是，例如，对于NMOS功率晶体管，这种器件仅可能满足某种额定值的需求，而不能满足在诸如用于电机驱动的高侧栅极驱动器的应用中由于当使用BiMOS工艺流程时可能发生的垂直穿通而所需的较高额定值，该垂直穿通可能穿过PBL上方的n阱与PBL下方的n+掩埋层(NBL)之间的p+掩埋层(PBL)而发生。横向结隔离是垂直结隔离的已知替代方案，其包括双结隔离，该双结隔离包括P隔离环和n隔离环，这可以进一步将晶体管的电压额定值提高几伏。
发明内容
提供该概述以便以简化形式介绍所公开的概念的简要选择，这些概念在以下包括所提供的附图的具体实施方式中被进一步描述。该概述不旨在限制要求保护的主题的范围。
所公开的实施例认识到具有p隔离(PISO)和外部n隔离(NISO)环的双横向结隔离可以提高包括漏极延伸MOS(DEMOS)和横向扩散MOS(LDMOS)晶体管的功率晶体管的电压额定值。然而，当双横向结隔离的DEMOS和LDMOS被应用于电路诸如驱动半桥电路的高侧MOS晶体管的栅极的高侧栅极驱动器的低侧栅极驱动晶体管时，在动态电路工作期间(即，切换)，低侧栅极驱动晶体管的NISO节点(对应于NISO环)的负下冲(negative undershoot)可能发生，这会导致注入少数载流子到衬底内，诸如注入电子到NMOS晶体管的p衬底内。
所公开的实施例使用具有浮动NISO节点的双横向结隔离晶体管替代高侧栅极驱动器的低侧LDMOS或DEMOS晶体管，这在一个实施例中可以通过不连接NISO节点到键合焊盘来实现。浮动NISO节点的创新方法与总是试图将每个节点系连到某一电势的常规电路设计思想相反。
附图说明
现在将参照附图，这些附图不必依照比例绘制，其中：
图1A根据示例性实施例示出了电路组合，其包括(i)IC管芯，该IC管芯包括耦合到高侧栅极驱动器的电平移位电路块，该高侧栅极驱动器驱动半桥电路的高侧晶体管的栅极；(ii)半桥电路，其中低侧栅极驱动晶体管是所公开的具有浮动NISO节点的双横向结隔离的LDMOS或DEMOS晶体管。
图1B根据示例性实施例描述了栅极驱动器的浮动NISO LDMOS/DEMOS晶体管在导致SW节点的负下冲(低于地电压)的切换事件期间的动态操作，其中由功率二极管取代图1A所示的半桥电路的低侧晶体管(开关)。
图2A是根据示例性实施例包括示例性浮动NISO LDMOS/DEMOS晶体管和高侧栅极驱动晶体管(显示为方框)的半导体器件的横截面图，而图2B是不具有所示出的金属前电介质或金属化的图2A所示的示例性浮动NISO LDMOS/DEMOS晶体管的增强顶视图。
图3是针对图1B示出的电路布置以及市售参考电路布置(REF)绘制在SW节点处的最大负电压幅度(Vswitch-max，y轴)与脉冲时间(x轴)的关系的测量数据，其中图1B示出的电路布置在25℃、40℃和125℃下测量，而市售参考电路布置(REF)在25℃下测量，所述参考电路布置包括栅极驱动器以及相同的半桥，其中低侧LDMOS没有浮动NISO节点。
具体实施方式
示例实施例是参照附图进行描述的，其中相同的附图标记被用来指示类似或等价的元件。动作或事件的示出顺序不应当视为是限制性的，因为一些动作或事件可以以不同的顺序发生和/或与其他动作或事件同时发生。此外，可能不需要某些示出的动作或事件来实现根据本公开的方法。
图1A根据示例性实施例示出一种电路组合100，其包括：(i)IC管芯110，该IC管芯110形成在衬底105的半导体表面上并且包括耦合到高侧栅极驱动器115(HS栅极驱动器115)的电平移位器电路块112，该高侧栅极驱动器115用示出的脉冲宽度调制(PWM)信号驱动半桥电路120的高侧晶体管(开关)122的栅极，(ii)半桥电路120。HS栅极驱动器115包括高侧栅极驱动晶体管116和低侧栅极驱动晶体管117，以及在高侧栅极驱动晶体管116和低侧栅极驱动晶体管117之间的栅极节点118。低侧栅极驱动晶体管117是所公开的具有浮动NISO节点的双横向结隔离的LDMOS或DEMOS晶体管(以下称为浮动NISO LDMOS/DEMOS晶体管117)。半桥电路120的低侧晶体管(开关)121被显示为接收PWM互补信号，该PWM互补信号通常由低侧栅极驱动器(图1A中未示出)提供。半桥电路120的低侧晶体管(开关)121可以是功率MOSFET或功率二极管，其中图1A示出功率MOSFET的情况，而图1B示出功率二极管的情况。
尽管在图1A和本文的其他附图中描述了NMOS晶体管，但本领域的普通技术人员应当清楚的是，通过用p掺杂替代n掺杂区域，并且反之亦然，可将在此所公开的信息用于PMOS晶体管。如在此所使用，当扩散区被称为以特定掺杂剂类型掺杂时，这意味着半导体表面中的一个区域，在该区域中，所提到的掺杂剂类型(例如，n型)的掺杂浓度高于第二类型(例如，p型)的掺杂剂的掺杂浓度。
制造晶体管LDMOS/DEMOS晶体管的通用方面和形成上述晶体管的工艺可以在多种参考文献中找到，包括Sridhar等人的题为“thick gate oxide for LDMOS and DEMOS”的美国专利第8,470,675号，该专利通过引用合并于此。简言之，DEMOS晶体管通过在器件的漏极和沟道之间添加漏极漂移区而具有延伸的漏极，在该区域而非沟道区中俘获大部分电场，并且如本文所用，DEMOS晶体管还包括被称为双扩散漏极MOS(DDDMOS)的变体。LDMOS晶体管使用由类似于DEMOS晶体管结构的额外掺杂所产生的漏极漂移区。
高侧栅极驱动晶体管116也可以是双横向结隔离的LDMOS或DEMOS晶体管。半桥电路120被显示为是与管芯110的电路(耦合到HS栅极驱动器115的电平移位器电路块112)分开的电路(外部)。半桥电路120的输出端被显示为OUT，其用于驱动图示的电感器125两端产生的电阻负载。该半桥的输出端处的布置可以从图1A和图1B所示的布置变化以体现为不同的拓扑结构，诸如与电容器串联到地的电感器，其中OUT在电容器两端获得。这种替代拓扑结构还被识别为导致如本文所描述的负下冲发生。
在典型的半桥电路中，当高侧晶体管(开关)122断开并且低侧晶体管(开关)121接通时，来自电感器125的感应电流可以流经图1A中的低侧晶体管(开关)121的体二极管121a或图1B所示的功率二极管121'，这将迫使显示为119的开关(SW)节点(SW节点119)下冲到低于地的电压电平。开关节点119的下冲被识别为要求低侧栅极驱动晶体管117的源极和漏极与地面和启动端(boot)完全隔离。如果低侧栅极驱动晶体管117的节点不被完全隔离(通常是不存在介电隔离方案或双结隔离的情况)，这导致在半桥电路120的切换期间由负下冲引起的电子被注入到地(即，其可以与由IC管芯110上的所有器件所共享的高电阻p衬底在电气上一样)，使得可能导致低侧栅极驱动晶体管117的故障和损坏。改进的负下冲抗干扰性被认为是重要的，特别是对于高电压(例如，>15V)的高侧栅极驱动器IC应用，例如，用于电机驱动应用。
图1B根据示例性实施例描绘了在引起SW节点119的负下冲(低于接地)的切换事件期间HS栅极驱动器115的浮动NISO LDMOS/DEMOS晶体管117的动态操作，其中由功率二极管121'替代图1A所示的半桥电路120的低侧晶体管(开关)121，半桥电路现在显示为120'。浮动NISO LDMOS/DEMOS晶体管117的寄生npn双极晶体管的n集电极对应于图1B中显示为浮动的NISO节点117g(也在以下描述的图2A和图2B中示出)，其中电感器电流流经功率二极管121'。
浮动NISO LDMOS/DEMOS晶体管117的源极直接系连到半桥电路120'(或图1A中的半桥120)的SW节点119；使得其漏极将跟随具有开关节点119的电势的源极，因为浮动NISOLDMOS/DEMOS晶体管117的栅极使晶体管接通。在NISO节点117g浮动的情况下，浮动NISOLDMOS/DEMOS晶体管117的源极和漏极都与启动端和地(Psub)完全隔离，由此相比于常规地将NISO系连到固定电势如源极电势，提供了浮动NISO LDMOS/DEMOS晶体管117的改进的负下冲抗干扰性。
NISO节点117g与启动端节点之间的结隔离可以是NISO节点117g与p衬底(参见图2A和图2B中的衬底105)之间的额定20V和额定700V，其中高额定电压如额定700V由轻掺杂衬底来实现，诸如掺杂水平<5×1014cm-3，包括在一些实施例中≤2×1014cm-3。相反，如果NISO节点以常规方式连接到固定电势诸如源极电势(例如，GND)，则由于特别是内置在薄p-衬底材料中的器件的漏极的NWELL与NISO节点117g之间的穿通，LDMOS/DEMOS晶体管很可能经受低击穿电压，诸如12伏或更小的击穿电压，其中该薄p-衬底材料可以用于高级低电压(40V或更低)线性BiCMOS(LBC)或双极(Bipolar)-CMOS-DMOS(BCD)技术。因此，当启动端节点/Vcc是15伏或更大时，常规的LDMOS/DEMOS晶体管可能经历潜在破坏性的结击穿。
图2A是根据示例实施例的包括示例性HS栅极驱动器的半导体器件200的横截面图，其中该HS栅极驱动器包含所公开的浮动NISO LDMOS/DEMOS晶体管117和为了简化而显示为方框的高侧栅极驱动晶体管118，而图2B是不具有所示出的金属前电介质(PMD)215或金属化的图2A所示的示例性浮动NISO LDMOS/DEMOS晶体管117的俯视图。浮动NISO LDMOS/DEMOS晶体管117被显示为形成在显示为p-衬底的衬底105的半导体表面中。衬底105和/或半导体表面通常可以包括硅、硅-锗或包括III-V族或II-VI族半导体材料的其他半导体材料。
一种特定结构是在硅衬底上的硅/锗(SiGe)半导体表面。当p-衬底被轻掺杂时，例如，掺杂密度<5×1014cm-3，使得IC管芯110上的电平移位器可以提供高击穿电压，则少数载流子注入的问题导致更高的电压降，从而引起额外的电压电平下冲，相比于具有更高掺杂的衬底诸如p+衬底的其他技术，浮动NISO LDMOS/DEMOS晶体管117需要忍受/承受该电压电平下冲。场氧化物(FOX)被显示为图2B中的FOX 117f，该FOX 117f由LOCOS形成且其特征喙部也可以实现为浅沟槽隔离(STI)场氧化物。
如图2A所示，浮动NISO LDMOS/DEMOS晶体管117包括具有穿过其中的触头诸如填充有钨(W)插塞的金属前电介质215、耦合到这些触头的第一金属互连层220、在第一金属互连层220上的第一层间电介质(ILD)225以及在第一ILD 225上的至少第二金属互连层230。如本文所用，触头是半导体材料与金属材料之间的界面/接口。所显示的触头包括可选的硅化物层219。虽然图2A中的金属层未被显示为镶嵌到相应的电介质中(例如用于铜金属化)，但所公开的实施例也包括镶嵌的金属层。
图2A所示的触头包括连接到源极区117b、漏极区(D)117d的触头，该源极区117b使用第一掺杂剂类型的掺杂剂来掺杂并显示为n+源极区(S)117b，被n+掺杂的该漏极区(D)117d与S117b是不对称的并且包括在与D117d连接的n+触头与栅极堆叠117c之间的漏极漂移区。在n+S 117b上方的触头还提供了穿过其p阱206区和PBL 207连接到背栅(BG)117e的p+触头，这提供了p隔离(PISO)环(从而提供用于BG 117e/PISO的偏压)，该p隔离环可以被称为“源极d阱”(d阱代表双扩散p阱)，其提供与p+BL(PBL)207的低阻抗竖直连接。因此，BG117e不必具有显示用于偏置的触头，因为它被系连到源极117b。包括栅极电介质117c2上的栅极电极(例如，掺杂多晶硅)117c1的栅极堆叠117c处于S117b和D117d之间。尽管未示出，但是可以存在双栅极。
BG 117e还包括越过D117d的连接到p阱206的p+触头，该p阱耦合到所示出的PBL207。如图2A所示，S 117b和D117d在BG 117e内，并且可以被BG 117e包围。虽然PBL 207被显示为延伸在D117d、S 117b以及栅极堆叠117c下面的全部区域上，但PBL 207可以可选地在范围上更受限制，只要它提供D117d的n阱与NBL 209/NISO节点117g之间的适当隔离并且被连接到与源极117b(源极d阱)接触的触头下面的p阱206区即可。
显示为NISO节点117g的第二隔离区包括与n阱211接触的n+触头，该n阱211耦合到n+BL(NBL)209，其中NISO节点117g包围BG 117e(参见以下描述的图2B)。场氧化物(FOX)117f被显示在相应区域之间。NISO节点117g被显示为不存在通过PMD 215的任何触头，使得它是电浮动的，其更一般地不耦合到第二级金属互连层225，还更一般地不连接到上部金属互连层，从而不存在与任何键合焊盘的连接。相应地，例如，对于NISO节点117g，可以存在用于仅连接到第一金属互连层220的触头，使得NISO节点117g仍将是电浮动的。
所公开的实施例可以实现为包括具有所公开的浮动NISOLDMOS/DEMOS晶体管117的栅极驱动器和半桥的芯片，如图1A所示。其它实施例包括栅极驱动器芯片，该栅极驱动器芯片包括高侧栅极驱动晶体管116、作为较低的高侧栅极驱动晶体管的所公开的浮动NISOLDMOS/DEMOS晶体管117以及作为分立器件的浮动NISO LDMOS/DEMOS晶体管117管芯。
示例
所公开的实施例通过以下的特定示例来进一步说明，该示例不应当被解释为以任何方式限制本公开的范围或内容。图3是绘制在25℃、40℃、125℃下针对图1B示出的电路结构以及在25℃下测量的市售参考电路结构(也显示为参考(REF))的在SW节点119处的最大负电压幅度(Vswitch-max，y轴)与脉冲时间(x轴)之间的关系的测量数据，其中该市售参考电路结构包括栅极驱动器以及相同的半桥结构，其中低侧LDMOS没有浮动NISO节点。如上所述，图1B所示的电路结构包括所公开的浮动NISO LDMOS/DEMOS NMOS晶体管117，其作为HS栅极驱动器115的低侧晶体管并且其源极被耦合到SW节点119。如果Vswitch-max限值被超过，则在切换期间从电感器125接收的衬底电流将流入HS栅极驱动器115的低侧晶体管，使得它可能无法生存或输出波形可能不如预期。
在25℃下的相对长的脉冲时间(>500ns)内，Vswitch-max的量值保持在大约20V(-20V)，使得在18V(-18V)下HS栅极驱动器115将是完好的，但在22V(-22V)下HS栅极驱动器115可能会被损坏。对于较短的脉冲时间，Vswitch-max的量值增加，例如，对于100ns，Vswitch-max限值为约45(-45V)，使得在44V(-44V)下HS栅极驱动器115将是完好的，但是在48V(-48V)下HS栅极驱动器115可能会被损坏。
在25℃下测量的市售参考电路结构(REF)包括栅极驱动器以及相同的半桥结构，其中低侧LDMOS没有浮动NISO节点117g，该NISO节点被认为通过电阻器连接到启动端节点或SW节点119。如图3所示，针对从约100纳秒至500纳秒的脉冲时间，显示REF的Vswitch-max通常限制为比图1B所示的电路结构(包括作为低侧晶体管的所公开的浮动NISO LDMOS/DEMOS NMOS晶体管117)低5V。因此，图3证明，在经受来自SW节点119的脉冲的显著量值负电压幅度的如图1B所示的电路结构或类似电路结构中使用所公开的浮动NISO LDMOS/DEMOSNMOS晶体管117，与具有常规连接到固定电势的NISO节点的其他等效电路结构相比，提供优异的负下冲抗干扰性安全工作区域(SOA)曲线。
所公开的实施例可以用于形成半导体管芯，该半导体管芯可以被集成到各种组装流程中以形成各种不同的器件和相关产品。该半导体管芯可以包括在其中的各种元件和/或在其上的各种层，包括势垒层、介电层、器件结构、有源元件和无源元件，这些元件包括源极区、漏极区、位线、基极、发射极、集电极、导线、导电通孔等。此外，该半导体管芯可以通过多种工艺(包括双极型晶体管、绝缘栅双极晶体管(IGBT)、CMOS、BiCMOS和MEMS)来形成。
本公开所涉及的领域的技术人员将认识到，许多其他的实施例和实施例的变体在所要求保护的发明的范围之内是可能的，并且可以在不背离本公开的范围的情况下，对所描述的实施例进行进一步的添加、删除、替换和修改。

Claims (20)

1.一种半导体器件，其包括：
形成在以第一掺杂剂类型掺杂的衬底的半导体表面中的晶体管，所述晶体管包括：
第二级金属层，所述第二级金属层在第一级金属层上面，所述第一级金属层通过触头耦合到以第二掺杂剂类型掺杂的源极区；
所述第二级金属层通过触头耦合到漏极区，所述漏极区包括以所述第二掺杂剂类型掺杂的漏极漂移区；
栅极堆叠，其包括在所述源极区和所述漏极区之间的栅极电介质上的栅极电极，使得所述第二级金属层通过触头与所述栅极堆叠耦合；
所述第二级金属层通过触头耦合到以所述第一掺杂剂类型掺杂的第一隔离区；
所述源极区和所述漏极区由所述第一隔离区包围，以及
以所述第二掺杂剂类型掺杂的第二隔离区，所述第二隔离区围绕所述第一隔离区，其中所述第二隔离区不耦合到所述第二级金属层，从而其电浮动。
2.根据权利要求1所述的半导体器件，其中所述晶体管包括漏极延伸的MOS晶体管即DEMOS晶体管或横向扩散MOS晶体管即LDMOS晶体管。
3.根据权利要求1所述的半导体器件，其中所述晶体管包括n沟道晶体管。
4.根据权利要求1所述的半导体器件，其中所述晶体管包括p沟道晶体管。
5.根据权利要求1所述的半导体器件，其中所述晶体管是第一晶体管，所述半导体器件进一步包括在所述半导体表面中形成的与所述第一晶体管钩串联的第二晶体管。
6.根据权利要求1所述的半导体器件，其中所述半导体表面具有小于5×1014cm-3的掺杂密度。
7.根据权利要求6所述的半导体器件，其中所述晶体管是第一晶体管，所述半导体器件进一步包括在所述半导体表面中形成的与所述第一晶体管钩串联的第二晶体管以及在所述半导体表面中形成的被耦合以驱动所述第一晶体管的所述栅极电极和所述第二晶体管的所述栅极电极的电平移位器。
8.根据权利要求1所述的半导体器件，其中所述衬底包括硅并且所述栅极电极包括多晶硅。
9.根据权利要求1所述的半导体器件，其中所述第一隔离区在所述源极区、所述栅极堆叠和所述漏极区下面连续延伸。
10.一种用于晶体管的方法，其包括：
提供具有形成在以第一掺杂剂类型掺杂的衬底的半导体表面中的双隔离件的晶体管，所述晶体管包括：
以第二掺杂剂类型掺杂的源极区；
包括以所述第二掺杂剂类型掺杂的漏极漂移区的漏极区；
包括在所述源极区和所述漏极区之间的栅极电介质上的栅极电极的栅极堆叠；
以所述第一掺杂剂类型掺杂的第一隔离区；
所述源极区和所述漏极区由所述第一隔离区包围，以及
以所述第二掺杂剂类型掺杂的第二隔离区，所述第二隔离区包围所述第一隔离区，以及
在所述晶体管被操作的情况下将所述第二隔离区配置为电浮动。
11.根据权利要求10所述的方法，其中所述晶体管包括漏极延伸的MOS晶体管即DEMOS晶体管或横向扩散MOS晶体管即LDMOS晶体管。
12.根据权利要求10所述的方法，其中所述晶体管包括n沟道晶体管。
13.根据权利要求10所述的方法，其中所述晶体管包括p沟道晶体管。
14.根据权利要求10所述的方法，其中所述晶体管是第一晶体管，所述方法进一步包括提供在所述半导体表面中形成的与所述第一晶体管串联连接的第二晶体管。
15.根据权利要求10所述的方法，其中所述半导体表面具有小于5×1014cm-3的掺杂密度。
16.根据权利要求10所述的方法，其中所述晶体管是第一晶体管，所述方法进一步包括在所述半导体表面中形成的与所述第一晶体管钩串联的第二晶体管以及在所述半导体表面中形成的被耦合以驱动所述第一晶体管的所述栅极电极和所述第二晶体管的所述栅极电极的电平移位器。
17.根据权利要求10所述的方法，其中所述衬底包括硅并且所述栅极电极包括多晶硅。
18.根据权利要求10所述的方法，其中所述第一隔离区在所述源极区、所述栅极堆叠和所述漏极区下面连续延伸。
19.根据权利要求10所述的方法，其中所述使所述第二隔离区电浮动包括不将所述第二隔离区耦合到第一级金属层上面的至少第二级金属层。
20.根据权利要求10所述的方法，其中所述使所述第二隔离区电浮动包括不提供至所述第二隔离区的触头。
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