CN105097754A - Resin encapsulated power-purpose semiconductor apparatus and manufacturing method thereof - Google Patents
Resin encapsulated power-purpose semiconductor apparatus and manufacturing method thereof Download PDFInfo
- Publication number
- CN105097754A CN105097754A CN201410647851.5A CN201410647851A CN105097754A CN 105097754 A CN105097754 A CN 105097754A CN 201410647851 A CN201410647851 A CN 201410647851A CN 105097754 A CN105097754 A CN 105097754A
- Authority
- CN
- China
- Prior art keywords
- wire
- resin
- power semiconductor
- semiconductor apparatus
- movable pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention discloses a resin encapsulated power-purpose semiconductor apparatus and a manufacturing method thereof which can prevent short cut among wires and guarantee proper insulation distance at the same time, thus achieving minimization. The apparatus (20) includes: a semiconductor element (3), a lead frame (2) for energizing the semiconductor element (3); and a plurality of wires (7) which connect the semiconductor element (3) and the lead frame (2). The semiconductor element (3), the lead frame (2) and the plurality of wires (7) are encapsulated by a moulded resin. The plurality of wires (7) are arranged side by side such that the plurality of wires (7) extend in a direction which intersects the flow direction of the moulded resin (15). According to the apparatus (20), each wire (7) on a downstream side of the flow direction has a wiring length greater than or equal to the wiring length of the wire (7) on an upstream side of the flow direction.
Description
Technical field
The present invention relates to a kind of power semiconductor apparatus of resin packed and the manufacture method of resin packed power semiconductor apparatus, relate to a kind of method guaranteeing the reliability of inherent toroidal conductor.
Background technology
As existing semiconductor device, the known structure (such as with reference to patent documentation 1) that will crude aluminum wire utilized between built-in substrate and lead frame to connect.
Patent documentation 1: Japanese Unexamined Patent Publication 2013-175609 publication
As an example of FA (Factoryautomation) instrument, inverter, servo amplifier and programmable logic controller (PLC) can be enumerated.In the power semiconductor apparatus of FA instrument, there is following problem.Multiple stage FA instrument arranges in the horizontal direction in control board, if but width is that such as 10mm is wide, then when arrangement 10 instruments, the width that there is control board extends to the harmful effect of 100mm.In the form of FA instrument, exist be called as shelf type, by the type of lower thickness.The FA instrument of shelf type meets the miniature requirement of user, but for the FA instrument of shelf type, the large this point of thickness becomes king-sized problem.
Therefore, there is following expectation, that is, the width of the power semiconductor apparatus used in FA instrument self is also reduced as far as possible.
When manufacturing resin packed power semiconductor apparatus, if utilize wire to be connected with substrate at the electrode arranged at lead frame everywhere, and inject moulding resin from horizontal direction to the lead frame be configured in mould and substrate, then mould resin at mould inner mould and flow in the horizontal direction.Moulding resin flow time be in liquefaction, if but liquefaction resin collide from the direction vertical with the bearing of trend of wire and wire, then the wire making wire be out of shape rushes askew phenomenon.
When rush due to wire askew and make the wire of different voltage contact with each other the insulation distance needed for maybe cannot guaranteeing in proof voltage, the fault that is short-circuited or leakage failure, therefore following problems is produced, namely, need numerous and diverse inspection operation, or produce restriction etc. during can guaranteeing reliability.
Therefore, in resin packed power semiconductor apparatus, in order to prevent wire short circuit, guaranteeing suitable insulation distance, must guarantee that the interval between wire is more than or equal to certain distance, hampering the miniaturization of resin packed power semiconductor apparatus.
Summary of the invention
The present invention proposes in view of the foregoing, its object is to, obtain a kind of short circuit preventing between wire and while guaranteeing suitable insulation distance, realize miniaturized resin packed power semiconductor apparatus and the manufacture method of resin packed power semiconductor apparatus.
In order to solve above-mentioned problem, realize object, resin packed power semiconductor apparatus of the present invention has the multiple wires configured side by side, multiple wire is encapsulated by moulding resin together with semiconductor element, the feature of this resin packed power semiconductor apparatus is, multiple wire arranges along the flow direction of moulding resin, and the wiring lengths of the wire in the downstream of flow direction is more than or equal to the wiring lengths of the wire of the upstream side of flow direction.
The effect of invention
According to the present invention, there is following effect, though that is, wire distortion, also can not with the conductive contact in downstream, can short circuit be prevented, and suitable insulation distance can be guaranteed.
Accompanying drawing explanation
Fig. 1 is the profile of the execution mode 1 of resin packed power semiconductor apparatus involved in the present invention.
Fig. 2 is the vertical view of the resin packed power semiconductor apparatus involved by execution mode 1.
Fig. 3 is the vertical view of the resin packed power semiconductor apparatus involved by execution mode 1.
Fig. 4 is the enlarged drawing of wire.
Fig. 5 is the figure that the direction seeming linearly from conductor loop shows the process that wire is toppled over.
Fig. 6 is the figure of the wire of the execution mode 2 representing power semiconductor apparatus involved in the present invention.
Fig. 7 represents alternately to exchange once to connect to be connected with secondary and the figure of state after distribution.
Fig. 8 is the profile of the molding die for the manufacture of the power semiconductor arrangement involved by execution mode 4.
Fig. 9 is the figure of the state after the injection having represented moulding resin.
Figure 10 represents the figure that there is the state in the space of movable pin after potting resin to script.
Figure 11 represents that moulding resin fills the figure of the wire shape of front and back.
Figure 12 is the profile of wire.
The explanation of label
1 substrate, 2 lead frames, 3 semiconductor elements, 4,5,6 electrodes, 7 wires, 7a connection side, 7b bis-connection side, 7c top, 8 movable pins, 9 insulating coatings, 10 moulds, 11 molds, 12 bed dies, 13 cavitys, 14 movable pin driving mechanisms, 15 moulding resins, 16 insulating trips, 17 metal bases, 20 resin packed power semiconductor apparatus.
Embodiment
Below, based on accompanying drawing, describe the execution mode of power semiconductor apparatus involved in the present invention in detail.In addition, the present invention does not limit by present embodiment.
Execution mode 1
Fig. 1 is the profile of the execution mode 1 of resin packed power semiconductor apparatus involved in the present invention.Fig. 2 is the vertical view of the resin packed power semiconductor apparatus involved by execution mode 1.In resin packed power semiconductor apparatus 20, for supporting fixing semiconductor element 3 and the lead frame 2 be connected with outside wiring is configured to, three-dimensionally do not interfere with substrate 1.Semiconductor element 3 is configured with at lead frame 2.At the opposing face at the position of the configuring semiconductor element 3 of lead frame 2, configuration insulating trip 16 and metal base 17, the heating of semiconductor element 3 is dispelled the heat via metal base 17.Be arranged at the electrode 4 of semiconductor element 3 or between the electrode 5 of substrate 1 and the electrode 6 being arranged at lead frame 2, utilize multiple wire 7 to connect.As the material of wire 7, although according to standard, the workability of the aluminium that can engage with normal temperature is excellent, and the composite material of copper or copper and aluminium also can as the materials'use of wire 7, in addition, also can using the materials'use of the composition of other metals or metal as wire 7.
Substrate 1, lead frame 2, semiconductor element 3 and wire 7 are encapsulated by moulding resin 15.In fig. 2, flow direction when utilizing moulding resin 15 to carry out resin-encapsulated is represented with arrow A.
Fig. 3 is the vertical view of the resin packed power semiconductor apparatus involved by execution mode 1, shows the state injected before moulding resin 15.Wire 7 before molding configures substantially in parallel, and the upstream side on the flow direction of moulding resin 15 is configured with shorter wire 7, is configured with longer wire 7 in downstream.Therefore, when being conceived to adjacent 2 wire 7, the wiring lengths of the wire 7 in downstream is more than or equal to the wiring lengths of the wire 7 of upstream side.
When utilizing moulding resin 15 to carry out molding, wire 7 is subject to the impact that moulding resin 15 flows, and as shown in Figure 2, is out of shape in the mode depicting the arc protruded to downstream.For the amount of movement when each wire 7 there occurs distortion because of moulding resin 15, the shorter amount of movement of wire 7 is less, and the longer amount of movement of wire 7 is larger, and therefore, after injection moulding resin 15, the distance between wire 7 broadens.
In execution mode 1, by being configured to by wire 7, the wire 7 that the upstream side configuration on the flow direction of moulding resin 15 is shorter, at the wire 7 that downstream configuration is longer, thus prevents the unnecessary minimizing of the distance between short circuit and wire 7.Thereby, it is possible to improve the rate of finished products of resin packed power semiconductor apparatus 20.
Fig. 4 is the enlarged drawing of wire.Connected between electrode 4a, 4b of semiconductor element 3 and the electrode 5 of substrate 1 by wire 7.Be the upstream that moulding resin 15 injects on the right side of Fig. 4, left side is downstream.Be configured to by semiconductor element 3, from upstream, to downstream, wire 7 shortens successively.Although wire 7 is out of shape because of the flowing of moulding resin 15, because the upstream side of the flowing at moulding resin 15 is shorter, longer in downstream, therefore prevent the distance between wire 7 from becoming too short.With the example shown in Fig. 4 on the contrary, when upstream is configured with longer wire 7 and is configured with shorter wire 7 in downstream, larger than the displacement of short wire 7 compared with the displacement of long wire 7, therefore, produce the risk that the distance between wire 7 unnecessarily diminishes, resin packed power semiconductor apparatus 20 cannot be made miniaturized.
Experimental verification is implemented to the size of the displacement of wire 7.First, for wire 7 distortion needed for power, power required till make wire 7 become bowed shape due to the flowing to horizontal direction, when the aluminum conductor of φ 300 μm, is 0.4mN ~ 1mN, very little.For wire 7, if start to apply power, then carry out strain at first, if but apply power further, then start plastic deformation.If once the plastic deformation of wire 7 starts, then wire 7 is till becoming bowed shape equally, does not stop distortion.The arcuate shape formed when wire 7 is deformed into and becomes the same bowed shape, becomes the shape in the entire length of wire 7, the arc of roughly the same radius being toppled over.
Fig. 5 is the figure that the direction seeming linearly from conductor loop shows the process that wire is toppled over.The right side of figure is the upstream that moulding resin 15 injects, and left side is downstream.Produce viscous drag due to the flowing of moulding resin 15, guiding line 7 applies the power F in the direction parallel with flowing.The root generation plastic deformation of wire 7, little by little makes wire 7 constantly topple over.Along with wire 7 is toppled over, relative to the direction of the viscous drag produced due to moulding resin 15, produce the component Fa in the direction stretched by the wire 7 and component Fb of toppling direction.
If wire 7 is constantly toppled over, then the component Fb in the direction that wire 7 will be made to topple over diminishes, and time the component Fb root diminished to connecting portion becomes elastic range, reaches capacity.Under state the component Fb root diminished to connecting portion becomes elastic range, there is following tendency, even that is, identical conductor loop height, observe from vertical, the wire 7 that total length is longer, the distance that wire 7 is toppled over is larger.Its reason is, the root generation plastic deformation of the connecting portion of wire 7, and make wire 7 become arc and there occurs the shape of toppling over, but conductor length is shorter, becomes regime of elastic deformation more further, the amplitude of toppling over narrows, and conductor length is larger, and the amplitude of toppling over is larger.
Namely, by the arrangement of wire 7 is configured to as shown in Figure 4, from the upstream side of moulding resin 15 to downstream, conductor length becomes large, thus become the direction that the gap between wire 7 broadens further, as long as guarantee minimal space, therefore, it is possible to make resin packed power semiconductor apparatus miniaturized further.
The total length of wire 7 is determined by the length of the horizontal direction of wire 7 and conductor loop height.If conductor length is more than or equal to 20mm, then the mobile ad-hoc of wire 7 is large, but is subject to the restriction of molding die thickness due to conductor loop height, so substantially become identical height, specifically, becomes about 2mm ~ 4mm.Namely, if wire 7 contacts with mould upper surface, then produce wire 7 and do not rushed askew phenomenon because of friction, because whether the amount of movement of wire 7 can because contacting with mould upper surface and change significantly, so be difficult to control, and when with contacting dies, the aluminum conductor as distribution component exposes at the upper surface of power semiconductor apparatus, therefore, product becomes defective products.Therefore, wire 7 is relative to mould upper surface needs gap to a certain degree.
The ring height of wire 7 has reproducibility mechanically, usually can realize when carrying out experimental verification dropping on ± about 0.2mm scope in precision.But the resin component used in the feed system of wire, specifically, be called as the parts of wire conduct, they cause frictional resistance to change due to the wearing and tearing when being sent by wire.In addition, wire conduct offers the parts guiding the hole of wire or the resin sleeve that wire is passed at front tool.That is, conductor loop height change in the scope of ± 0.2mm usually, but to produce ± the change of about 0.5mm in the long run.
Thus, for conductor loop height, minimumly relative to mould upper surface the distance corresponding with resin thickness required in 0.5mm+ insulation must be guaranteed.In the case of epoxy resins, by guaranteeing the resin thickness of such as about 0.2mm, thus when upper surface does not have conductive electrical contact thing, can insulating properties be guaranteed, therefore, preferably needing to guarantee that aggregate value is more than or equal to the gap of 0.7mm.That is, restriction is existed for conductor loop height, height freely cannot be realized, therefore, must be appreciated that above-mentioned restriction and setting height.
For 7 groups, the wire that adjacent length is different, even if there is the distortion of the wire 7 accompanied with the flowing of moulding resin 15, be more than or equal to conductor loop height as long as the distance between adjacent wire 7 ensured, then adjacent wire 7 can be avoided to contact with each other.That is, if the gap that the MIN wire 7 of not interfering each other rushes askew distance can be vacated, even if then configure many groups, also identical effect can be played.
Execution mode 2
Fig. 6 is the figure of the wire of the execution mode 2 representing power semiconductor apparatus involved in the present invention.In the present embodiment, for adjacent wire 7, make the orientation of a connection side 7a and secondary connection side 7b, the direction namely pulling out conductor loop is consistent.That is, make multiple wire 7 from connection side 7a to secondary connection side 7b towards unanimously.
Arcuate shape determines by the impact of conductor loop height and conductor length.In addition, the height of conductor loop, the track indeed through the head to wire jointing device carries out NC (NumericalControl) and controls to process.Common track is, after engaging a connection side 7a, vertically makes instrument move, after becoming the height preset, pulls out wire and move horizontally, and makes instrument drop to the height of secondary connection after having moved horizontally.In the process of with making tool level movement, the position once connected of wire 7 is fixed, and from here, makes extend and pull out wire 7 with linking the slightly curved shape of line between this position and the incidental wire conduct of wire bonding tool.
First, after once connecting, instrument and wire conduct vertically rise.When instrument and wire conduct vertically rise, wire is also vertically pulled out.After instrument and wire conduct vertically rise, along with instrument and wire conduct flatly move, angle constantly diminishes.Distortion when instrument and wire conduct flatly move, become to be connected with conductor loop from the region once connected interregional be called as neck, make wire 7 there occurs distortion by once connecting and transfer printing goes out the end in the region of tool shape.Along with the movement of instrument and wire conduct, neck generation plastic deformation.Then, connect towards secondary instrument and wire conduct are declined time, constantly to shorten from the distance of wire conduct to the root once connected, but from the wire that wire conduct is extracted out, can not tension force under retraction degree owing to being only applied in, so wire constantly relaxes.Due to wire relaxes, form arc when instrument and wire conduct drop to the height of secondary connection.It is roughly determine by from square root sum square once connecting lifting height and the horizontal direction distance counted that wire is drawn out of the longest length.In other words, the extraction length of wire can be calculated by three squares of theorems.
The distance once connected between secondary connection after the length that wire 7 is drawn out of is greater than secondary connection, therefore, the difference of the length that the once connection after connecting according to secondary is drawn out of with the distance between secondary connection and wire 7, determines the shape of arc.After the root of a connection side 7a is out of shape because of plastic deformation, its result, produce and corresponding with the strain being called as resilience return deficiency, on the other hand, at secondary connection side 7b, the plastic deformation of root shape is connected by secondary and produces first, and the wire 7 not distortion after secondary connection, therefore do not produce resilience, if compared by the root of the root of a connection side 7a and secondary connection side 7b, then form the uneven arc of a connection side tilting.That is, the highest in arc top 7c is formed in compared with arcuate center to the position that connection side 7a offsets slightly.
As noted above, the ring-shaped of wire 7, in a connection side 7a and secondary connection side 7b, the angle of a connection side 7a is larger, therefore, by making the direction of pull-out conductor loop consistent, even if thus when by the wire 7 of equal length side by side distribution, also can make the position consistency of the top 7c of ring, the gap between wire 7 can be guaranteed.That is, as shown in Figure 6, when being engaged by wire 7 when making the direction of pull-out conductor loop consistent, interval arranged side by side can be maintained, therefore, it is possible to make the distance between adjacent wire 7 nearer.Thereby, it is possible to make resin packed power semiconductor apparatus miniaturized.
Fig. 7 represents alternately to exchange once to connect to be connected with secondary and the figure of state after distribution.When alternately exchanging a connection side 7a and secondary connection side 7b after distribution, the position of the top 7c of ring alternately changes, and when interval configures adjacent wire 7 compactly, the distance between wire 7 becomes near.Therefore, in order to prevent wire 7 short circuit each other, guaranteeing insulation distance, the interval of wire 7 must be widened, hampering the miniaturization of power semiconductor apparatus.
Execution mode 3
In execution mode 3, for adjacent wire, be set as by conductor loop height, be positioned at the wire in the downstream of the flowing of moulding resin, conductor loop height is higher.Change this point for making conductor loop height correspond to each wire, the lifting height after the once connection in can being controlled by NC is set and easily realizes.Because the wire in downstream is toppled over more significantly, therefore, even if wire is toppled over, be also make the wire in downstream away from the wire of upstream side.Therefore, even if the configuration between adjacent wire is become compact, be also difficult to the contact caused between wire, therefore, it is possible to make resin packed power semiconductor apparatus miniaturized.
Execution mode 4
Fig. 8 is the profile of the molding die for the manufacture of the power semiconductor arrangement involved by execution mode 4.Mould 10 is the structures forming cavity 13 between mold 11 and bed die 12, has the movable pin driving mechanism 14 that movable pin 8 is passed in and out in cavity 13 from mold 11.
Movable pin 8 is declined by movable pin driving mechanism 14, outstanding to inject at moulding resin 15 in forward direction cavity 13.
Movable pin 8 is configured between adjacent wire 7.Moulding resin 15 is injected under the state that movable pin 8 drops in cavity 13, but because the wire 7 of the upstream side being positioned at movable pin 8 contacts with movable pin 8, so at the position abutted with movable pin 8, can not be askew by the downstream side blow to the position contacted with movable pin 8.That is, wire 7 forms the shape arc limited by a connecting portion and movable pin 8 and the arc that limited by movable pin 8 and secondary connecting portion combined.Because the wire 7 in downstream does not abut with movable pin 8, so further by askew to downstream side blow.Thus, the distance between wire 7 can not be made to narrow, therefore, it is possible to configure wire 7 more to high-density.Fig. 9 be represent the injection of moulding resin 15 complete after the figure of state.
Near the moment that resin injection completes, movable pin driving mechanism 14 is utilized to make movable pin 8 rise and extract from cavity 13.
Complete at resin injection, after hardening of resin, extracting from cavity 13, exist in the space of movable pin 8 originally and there is not moulding resin 15, but by before completing in the sclerosis of moulding resin 15, movable pin 8 is extracted from cavity 13, even if thus very low amount, resin also has mobility, therefore, there is potting resin in the space of movable pin 8 to script.
Such as, if extracted from cavity by movable pin 8 in the moment that moulding resin 15 has injected, then owing to being continuously applied briquetting pressure, therefore there is potting resin in the space of movable pin 8 to script.Figure 10 represents the figure that there is the state in the space of movable pin after potting resin to script.
Figure 11 represents that moulding resin fills the figure of the wire shape of front and back.As shown in figure 11, wire 7 becomes the shape making arc-shaped recess in the position abutted with movable pin 8, and the gap between wire 7 can be made nearer.
Power semiconductor involved by present embodiment, the vestige of movable pin remains on the face that contacts with molding die upper surface.If movable pin bends, then can fracture when movable pin is extracted, therefore need intensity to a certain degree.Specifically, such as, adopt diameter to be the iron and steel etc. of 2mm, necessary intensity can be played.When there is no parts immediately below movable pin, pin can be made to drop to the region do not abutted with the surface of the lead frame or insulated substrate that are configured with power component of power semiconductor apparatus.But, such as below lead frame, insulation resin sheet is configured in use, when making the technique of lead frame and the bonding sclerosis of insulating trip carry out the power semiconductor apparatus of the form manufactured when being undertaken shaping by moulding resin 15 simultaneously, produce following problem, that is, if pin is extracted by the moment roughly completed to the injection of mould at moulding resin 15, then the pressure of moulding resin 15 sharply declines, plus-pressure to insulating trip reduces, and cannot give full play to the insulating properties of insulating trip.That is, in order to give full play to insulating properties and the cementability of insulating trip, must insulating trip be made in mould in thermoplastic period, applying the briquetting pressure of moulding resin 15, compression insulating trip.
According to above-mentioned technique, at the remained on surface of moulding resin through the vestige of above-mentioned operation.Because the movable volume of movable pin is larger, more can lose by build-up of pressure, therefore there is the situation of the mobile height not wishing to increase movable pin.In addition, there is the situation of also not wishing the diameter increasing movable pin.That is, can say, increase the intensity this point of movable pin, be not countermeasure in the resin packed power semiconductor apparatus of type using insulating trip.For the diameter of movable pin, from the angle of above-mentioned 2 reasons, the intensity of namely selling and volume-variation, diameter is between 1.5mm ~ 3mm be suitable.
When movable pin 8 not being extracted from cavity 13, expose at the position wire 7 originally contacted with movable pin 8, therefore, with contact in the vestige of the pin on the surface of power semiconductor apparatus and wire 7 exposed, from the angle of insulating properties, because needs increase creeping discharge distance, so be not countermeasure.By movable pin 8 being extracted the position to not contacting with wire 7, thus wire 7 can be realized not in the state that the mark region of movable pin 8 is exposed, exposing of wire 7 can be prevented.As noted above, owing to there is the operation making movable pin decline, the operation injecting moulding resin 15 and extract the operation of movable pin before moulding resin 15 hardening, so can contact and support wire 7 with movable pin 8 when moulding resin 15 injects, the distance between wire can be guaranteed, therefore, it is possible to make power semiconductor apparatus miniaturized.
Execution mode 5
The wire 7 used in the power semiconductor apparatus involved by embodiments of the present invention 5 has insulating coating 9.Figure 12 is the profile of wire.In addition, there is the mechanism of being peeled off by insulating coating 9 in wire jointing device.In order to be peeled off by insulating coating 9, and to utilize compared with the forming temperature of moulding resin 15 fusing point and boiling point is high and the Ins. ulative material that the absorptivity of laser is high forms insulating coating 9.The wire interconnecting piece irradiating laser of guiding line joining tool, removes coating layer resin by ablation.Utilize the wire 7 of insulating coating 9 and the wire bonding tool of tape insulation coating layer removal mechanism that have as shown in figure 12, can realize using the distribution that the wire 7 with insulating coating 9 carries out.Thus, even if wire 7 contacts with each other, also owing to remaining insulating coating 9 in the midway of conductor loop, the short circuit between wire 7 therefore can not be caused.Therefore, even if the configuration between adjacent wire is become compact, be also difficult to cause the contact between wire 7, therefore, it is possible to make resin packed power semiconductor apparatus miniaturized.
Industrial applicibility
As noted above, resin packed power semiconductor apparatus involved in the present invention, can realize in miniaturized this point useful while guaranteeing the interval between adjacent wire.
Claims (6)
1. a resin packed power semiconductor apparatus, it has: semiconductor element; For the lead frame be energized to this semiconductor element; And by multiple wires that described semiconductor element is connected with described lead frame, described semiconductor element, described lead frame and described multiple wire are encapsulated by moulding resin, described multiple wire is arranged as side by side, and the direction that the flow direction with described moulding resin intersects extends
The feature of this resin packed power semiconductor apparatus is,
The wiring lengths of the wire in the downstream of described flow direction, is more than or equal to the wiring lengths of the wire of the upstream side of described flow direction.
2. resin packed power semiconductor apparatus according to claim 1, is characterized in that,
Described multiple wire from link position to secondary link position towards unanimously.
3. resin packed power semiconductor apparatus according to claim 1, is characterized in that,
Described multiple wire has insulating coating.
4. resin packed power semiconductor apparatus according to claim 2, is characterized in that,
Described multiple wire has insulating coating.
5. resin packed power semiconductor apparatus according to any one of claim 1 to 4, is characterized in that,
The wire in the downstream of described flow direction, conductor loop height is higher.
6. the manufacture method of a resin packed power semiconductor apparatus, its use has the mold of movable pin and between this mold, forms the bed die of cavity when this mold engages, this manufacture method is for the manufacture of resin packed power semiconductor apparatus, the semiconductor element that this resin packed power semiconductor apparatus is configured to utilize moulding resin to be connected with substrate the multiple wire by configuring side by side encapsulates
The feature of the manufacture method of this resin packed power semiconductor apparatus is, has following operation:
Make described movable pin outstanding in the described cavity being configured with described semiconductor element from described mold, to make the front end of described movable pin between described multiple wire;
In the mode of described moulding resin along the also column direction flowing of described multiple wire, in described cavity, inject described moulding resin, make described movable pin support the wire in the downstream of the flow direction of described moulding resin; And
Before the sclerosis of described moulding resin completes, described movable pin to be contained in described mold and to extract from described cavity.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014098061A JP6316086B2 (en) | 2014-05-09 | 2014-05-09 | Resin-encapsulated power semiconductor device and manufacturing method thereof |
| JP2014-098061 | 2014-05-09 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105097754A true CN105097754A (en) | 2015-11-25 |
| CN105097754B CN105097754B (en) | 2019-03-15 |
Family
ID=54577854
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410647851.5A Active CN105097754B (en) | 2014-05-09 | 2014-11-14 | Resin packed power semiconductor apparatus and its manufacturing method |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP6316086B2 (en) |
| CN (1) | CN105097754B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113363231A (en) * | 2020-03-06 | 2021-09-07 | 三菱电机株式会社 | Semiconductor device with a plurality of semiconductor chips |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2018110169A (en) * | 2016-12-28 | 2018-07-12 | 富士電機株式会社 | Semiconductor device and manufacturing method for semiconductor device |
| US11710802B2 (en) | 2019-08-13 | 2023-07-25 | Lite-On Opto Technology (Changzhou) Co., Ltd. | Sensing device |
| CN112397630A (en) * | 2019-08-13 | 2021-02-23 | 光宝光电(常州)有限公司 | Light emitting device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63137440A (en) * | 1986-11-28 | 1988-06-09 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| CN1218290A (en) * | 1997-11-21 | 1999-06-02 | 三星电子株式会社 | Semiconductor integrated circuit device having dummy bonding wires |
| CN1848421A (en) * | 2005-04-04 | 2006-10-18 | 松下电器产业株式会社 | Lead frame and semiconductor device |
| WO2014046058A1 (en) * | 2012-09-20 | 2014-03-27 | ローム株式会社 | Power module semiconductor device and inverter device, power module semiconductor device producing method, and mold |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1167808A (en) * | 1997-08-21 | 1999-03-09 | Hitachi Ltd | Semiconductor device and its manufacture |
| WO2008081630A1 (en) * | 2006-12-29 | 2008-07-10 | Sanyo Electric Co., Ltd. | Semiconductor device and method for manufacturing the same |
| JP5542853B2 (en) * | 2012-02-27 | 2014-07-09 | 三菱電機株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| JP5932555B2 (en) * | 2012-08-03 | 2016-06-08 | 三菱電機株式会社 | Power semiconductor device |
| JP6021695B2 (en) * | 2013-03-06 | 2016-11-09 | 三菱電機株式会社 | Semiconductor device manufacturing method and semiconductor device manufacturing apparatus |
-
2014
- 2014-05-09 JP JP2014098061A patent/JP6316086B2/en active Active
- 2014-11-14 CN CN201410647851.5A patent/CN105097754B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63137440A (en) * | 1986-11-28 | 1988-06-09 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| CN1218290A (en) * | 1997-11-21 | 1999-06-02 | 三星电子株式会社 | Semiconductor integrated circuit device having dummy bonding wires |
| CN1848421A (en) * | 2005-04-04 | 2006-10-18 | 松下电器产业株式会社 | Lead frame and semiconductor device |
| WO2014046058A1 (en) * | 2012-09-20 | 2014-03-27 | ローム株式会社 | Power module semiconductor device and inverter device, power module semiconductor device producing method, and mold |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113363231A (en) * | 2020-03-06 | 2021-09-07 | 三菱电机株式会社 | Semiconductor device with a plurality of semiconductor chips |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105097754B (en) | 2019-03-15 |
| JP6316086B2 (en) | 2018-04-25 |
| JP2015216228A (en) | 2015-12-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4961441B2 (en) | Molded coil manufacturing method | |
| CN105097754A (en) | Resin encapsulated power-purpose semiconductor apparatus and manufacturing method thereof | |
| EP0545487B1 (en) | Semiconductor device encapsulated in resin | |
| JP5422191B2 (en) | Molded coil manufacturing method | |
| CN107170694A (en) | Position adjusting mechanism, resin encapsulation equipment, the manufacture method of resin encapsulation method and resin-encapsulated product | |
| JPH0484446A (en) | Semiconductor resin sealing mold mechanism | |
| WO2011155493A1 (en) | Method for producing resin molded article by injection molding, and injection molding device | |
| JP2009261220A (en) | Method of manufacturing stator | |
| JP4952502B2 (en) | Temperature detection element fixing structure, manufacturing method thereof, and mold | |
| JP2008230025A (en) | Plastic lens molding method | |
| JP2011218623A (en) | Insert molding apparatus, and insert molding method | |
| JP2010147271A (en) | Method for manufacturing molded coil | |
| JP2011088411A (en) | Method for molding powdery molded form of minute component | |
| KR100224649B1 (en) | Semiconductor molding die having radial runners | |
| US8119049B1 (en) | Continuous injection molding processes and systems with retractable core | |
| CN102233639B (en) | Resin sealing device and resin sealing method | |
| JP6425908B2 (en) | Injection molding method, injection mold and molded article | |
| JP2017140767A (en) | Manufacturing method of insert molded article and mold for insert molding | |
| JP6888525B2 (en) | Manufacturing method of energizing member module | |
| WO2010004903A1 (en) | Leadframe and method for manufacturing the same | |
| JP2006341581A (en) | Molding device, manufacturing method of the same, and molding method | |
| JP2009164286A (en) | Insert-molded product,and molding method thereof | |
| JP4055988B2 (en) | Chip inductor manufacturing method and apparatus | |
| JP4107306B2 (en) | Semiconductor device manufacturing equipment | |
| EP3156203B1 (en) | Release assistance device for molded article |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |