CN105097660A - Semiconductor element manufacturing method and manufactured element - Google Patents
Semiconductor element manufacturing method and manufactured element Download PDFInfo
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- CN105097660A CN105097660A CN201410209279.4A CN201410209279A CN105097660A CN 105097660 A CN105097660 A CN 105097660A CN 201410209279 A CN201410209279 A CN 201410209279A CN 105097660 A CN105097660 A CN 105097660A
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Abstract
The invention discloses a semiconductor element manufacturing method and a manufactured element. According to the embodiment, the method comprises: providing a substrate and a dielectric layer formed on the substrate; forming a plurality of trenches on the dielectric layer, wherein the trenches are separated by the dielectric layer; forming a first barrier cap layer in the trenches to be used as barrier liners of the trenches; filling a conductor in the trenches; removing partial conductor in the trenches to form a plurality of recesses, wherein the left conductor is provided with a flat surface; and forming a second barrier layer at the recesses to be used as barrier caps of the trenches.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor element and obtained element thereof, and particularly relate to a kind of manufacture method improving the semiconductor element of the characteristic electron of obtained semiconductor element by forming barrier layer.
Background technology
Semiconductor element size reduces day by day in recent years.Concerning semiconductor technologies, outside the size continuing to reduce semiconductor structure, improving speed, enhanced performance, raising density and reduce costs, is all important developing goal.Along with reducing of semiconductor element size, the characteristic electron of element also must maintain or even be improved, to reach the requirement of market product.Such as, each layer of semiconductor structure and affiliated element, as defectiveness or damage, can cause on the characteristic electron of structure the impact that cannot ignore, be manufacture the major issue that should be noted of semiconductor element one of.
Generally speaking, have the semiconductor element of excellent electrical performance, its wire and related elements must have good nature, such as wire must have complete surperficial profile, the each layer be stacked on wire need have the flatness of height, otherwise easily produces improperly that conductive species is excessive after applying voltage operates.If the excessive rear formation conducting bridge (conductivebridges) of conductive species and the adjacent wire of bridge joint, semiconductor element operation failure will be caused.Therefore, how formed in semiconductor fabrication process and there is the smooth wire of full surface profile and surface, solve the problem that may produce unnecessary conducting bridge, to improve the characteristic electron of obtained element, one of real important topic for relevant dealer.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method of semiconductor element and obtained element thereof, form the level and smooth and wire of flat surfaces of tool, and then improve the characteristic electron of obtained semiconductor element.
According to embodiment, a kind of manufacture method of semiconductor element is proposed.A substrate and a dielectric layer is provided to be formed on substrate; Form multiple groove in dielectric layer place, and those grooves are separated with dielectric layer.Form one first barrier layer afterwards in groove, using the barrier liner as groove.Fill a conductor in groove.Part removes the conductor in groove, to form multiple depression (recesses), removes rear remaining conductor and has a flat surfaces.Form one second barrier layer in recess, using the barrier lid (barriercaps) as groove.In embodiment, the upper surface of residue conductor is lower than the upper surface of dielectric layer and the upper surface lower than the first barrier layer.
According to embodiment, propose a kind of semiconductor structure, comprise a substrate and a dielectric layer is formed on substrate, and many wires are formed at dielectric layer place, and those wires are separated with dielectric layer.Those wires wherein one comprise a channel shaped and are formed in dielectric layer place, and one first barrier layer is formed at groove using the barrier liner as groove, has a conductor of flat surfaces, and one second barrier layer.Wherein groove is filled by conductor part and is formed a depression (recess), and the second barrier layer is formed at recess using the barrier lid as this conductor.
In order to have better understanding to above-mentioned and other aspect of the present invention, preferred embodiment cited below particularly, and the accompanying drawing appended by coordinating, be described in detail below:
Accompanying drawing explanation
Figure 1A ~ Fig. 1 E is the schematic diagram of the semiconductor device manufacturing method of one embodiment of the invention;
Fig. 2 A and Fig. 2 B is with the upper schematic diagram of the wire of embodiment method and semiconductor element obtained in the conventional way respectively;
Fig. 3 is the schematic diagram producing unnecessary conducting bridge after applying voltage between groove, and the wire that wherein conducting bridge bridge joint is adjacent, causes element operation to lose efficacy;
Fig. 4 is the schematic diagram that its time-dependence dielectric layer of wire of tool different surface roughness punctures test performance.
Symbol description
10: substrate
12: dielectric layer
121: upper surface
14: groove
16, the 16 ': the first barrier layer
The upper surface of 161: the first barrier layers
18: conductive material layer
18 ': conductor
18 ' ': residue conductor
181: the upper surface of conductor
21: depression
23, the 23 ': the second barrier layer
The upper surface of 231: the second barrier layers
D: the degree of depth of depression
Embodiment
Embodiments of the invention propose a kind of manufacture method of semiconductor element.According to embodiment, the manufacture method of semiconductor element is included in conductive trench (being namely filled with conductor in groove, such as copper) and forms depression, and in recess, insert the step of extra barrier layer on conductor.Conductor wherein in groove has extremely smooth surface, thus provides the adhesive force of excellence between conductor and additional barrier layer.Therefore, by the semiconductor element obtained by the manufacture method of the embodiment of the present invention, its characteristic electron can significantly improve, such as improve the puncture voltage (breakdownvoltage) of semiconductor element, and the problem effectively solving the excessive formation conducting bridge of traditional improper conductive species and cause element operation to lose efficacy.
Below propose embodiment, coordinate diagram to describe relevant manufacture method in detail and to apply its obtained component structure.But the present invention is not limited to this.The present invention not demonstrates all possible embodiment.Can be changed and modification structure and manufacture craft without departing from the spirit and scope of the present invention, with the needs of realistic application.Therefore, other enforcement aspects do not proposed in the present invention also may be able to be applied.Moreover the dimension scale on accompanying drawing is not drawn according to actual product equal proportion.Therefore, specification and diagramatic content are only described herein the use of embodiment, but not as the use of limit scope.
Figure 1A ~ Fig. 1 E is the schematic diagram of the semiconductor device manufacturing method of one embodiment of the invention.In embodiment, a substrate 10 and a dielectric layer 12 is provided to be formed on substrate 10.In one embodiment, dielectric layer 12 is such as comprise a ultra low k (ultra-lowk) dielectric material.Form multiple groove (trenches) 14 in dielectric layer 12, and those grooves 14 are separated with dielectric layer 12, as shown in Figure 1A.Moreover, form one first barrier layer (firstbarrierlayer) 16 in groove 14, using the barrier liner (barrierliners) as groove 14.One conductive material layer 18 to be formed at above the first barrier layer 16 and filling groove 14, as shown in Figure 1A.
Afterwards, the structure of Figure 1A is partly removed, such as with cmp (chemicalmechanicalpolishing, CMP) grind, to remove partially conductive material layer 18 above dielectric layer 12 and part first barrier layer 16, and then form the groove 14 being filled with conductor 18 ', as shown in Figure 1B.Now, the upper surface 181 of conductor 18 ' flushes with the upper surface 121 of dielectric layer 12 in fact.
Then, part removes conductor 18 ' in groove 14 to form multiple depression (recesses) 21, and removes rear remaining conductor 18 ' ' there is a flat surfaces (flatsurface), as shown in Figure 1 C.Also show in Fig. 1 C, remaining conductor 18 ' ' the upper surface 121 of flat surfaces lower than dielectric layer 12 and the upper surface 161 of the first barrier layer 16 '.
According to embodiments of the invention, a chemical solution can be applied to form depression 21.In one embodiment, conductor 18 ' in groove 14 is applied one chemical buffer liquid (chemicalbuff) (chemical solution) and is carried out part and remove, and chemical buffer liquid is such as the derivative comprising Tetramethylammonium hydroxide (tetramethylammoniumhydroxide) and an amino alcohol (aminoalcohol) or amino alcohol.In one embodiment, chemical buffer liquid is such as comprise quaternary ammonium salt derivative (quaternaryammoniaderivative), the tertiary amine (substitutedtertiaryamine) replaced, 2-(2-amido ethylamine) ethanol (2-(2-aminoethylamino) ethanol), dimethyl amine ethylene glycol (2-(dimethylamino) ethanol), aliphatic dicarboxylic acid (aliphaticdicarboxylicacid) and Glycolic acid (glycolicacid).
In one application, conductor 18 ' is such as comprise copper (Cu), and copper etch-rate is such as be greater than 0.1A/min.Etching period need be determined according to the desired value of depression 21 degree of depth d and some predetermined etching conditions, the preparation concentration of such as chemical buffer liquid, downforce (downforce) and etch-rate etc.In one embodiment, the dilution ratio (dilutedratio) of chemical buffer liquid is such as in the scope of 1:1 to 1:1000.In one embodiment, a degree of depth d of depression 21 is about
a scope in.In one embodiment, a degree of depth d of depression 21 about
or exceed
in one embodiment, a degree of depth d of depression 21 is about
a scope in.In one embodiment, the conductor 18 ' in groove 14 as shown in Figure 1B and groove 14, without under pressure or light pressure, such as pressure is not more than 5psi, applied chemistry buffer solution and form depression 21.In one embodiment, under the conductor 18 ' in groove 14 and groove 14 ties up to the pressure of 0 ~ 5psi or under the pressure of 0hpa ~ 350hpa, applied chemistry buffer solution and form depression 21.It should be noted that the content of aforesaid chemical buffer liquid and etching condition is only used for the applicable aspect of the present invention is described, and be not used to limit the scope of the invention.
According to the structure obtained by embodiment method, as shown in Figure 1 C, remaining conductor 18 ' ' its upper surface 181 is substantially parallel to the upper surface 121 of dielectric layer 12, and residue conductor 18 ' ' there is no fillet (roundingcorner) generation at intersection that is contiguous and the first barrier layer 16 '.According to the manufacture method of embodiment, remaining conductor 18 ' ' there is very smooth upper surface 181, its surface roughness is extremely low.In one embodiment, residue conductor 18 ' ' flat upper surfaces 181 there is a surface roughness be not more than
Then, in depression 21, place forms another barrier layer, using the barrier lid (barriercaps) as groove 14.As shown in figure ip, in embodiment, form one second barrier layer (secondbarrierlayer) 23 in depression 21 and dielectric layer 12, to form a cover layer.And grind the second barrier layer 23, be such as carry out with cmp (CMP), till the upper surface 121 arriving at dielectric layer 12, as referring to figure 1e.Show in Fig. 1 E, residue conductor 18 ' ' upper surface 181 substantially parallel to the upper surface 231 of the second barrier layer 23 '.
Moreover the first barrier layer 16/16 ' in embodiment and the second barrier layer 23/23 ' can comprise same material or different materials.In one embodiment, first barrier layer 16/16 ' and the second barrier layer 23/23 ' can individually be selected from following material, comprise titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), cobalt phosphorus (CoP), cobalt boron (CoB), cobalt tungsten phosphide (CoWP), cobalt tungsten boride (CoWB), nickel tungsten phosphide (NiWP), phosphatization cobalt tin (CoSnP), nickel tungsten boride (NiWB), copper silicide (CuSi), zirconium nitride (ZrN), nickel-molybdenum-phosphorus (NiMoP), or its combination.In one embodiment, the first barrier layer 16/16 ' and the second barrier layer 23/23 ' are such as the composite beds comprising a tantalum and tantalum nitride (Ta/TaN).In embodiment, when the first barrier layer 16/16 ' and the second barrier layer 23/23 ' select same material, Jia Fanni can be effectively avoided to corrode the generation of (Gavaniccorrosion).
It should be noted that step details and the Material selec-tion of implementation method may have slightly different, it can do suitable change and modification according to needed for the aspect of practical application and condition.Therefore above-mentioned details is describe the use of embodiment, but not as the use of limit scope.
The semiconductor element obtained according to embodiment, as referring to figure 1e, comprise a substrate 10 and a dielectric layer 12 is formed on substrate 10, and many wires (conductivelines) are formed at dielectric layer 12 place, and those wires are separated with dielectric layer 12.In one embodiment, those wires one of them comprise the groove 14 being formed at dielectric layer 12 place, be formed at one first barrier layer 16 ' of groove 14 using the barrier liner (barrierliners) as groove 14, there is a conductor (conductor) 18 ' of a flat surfaces ', with one second barrier layer 23 ' being formed at depression 21 place, using as conductor 18 ' ' a barrier lid (barriercaps).Wherein, groove 14 is by conductor 18 ' ' partly fill and in groove 14, form a depression (recess).According to embodiment, remaining conductor 18 ' ' upper surface 121 of its smooth upper surface 181 lower than dielectric layer 12 and the upper surface 161 lower than the first barrier layer 16 '.In other words, the residue conductor 18 ' in groove 14 ' covered by the second barrier layer 23 ', and the upper surface 161 of the first barrier layer 16 ' flushes with the upper surface 231 of the second barrier layer 23 ' in fact.Therefore, those wires one of them be made up of 3 parts, be the first barrier layer 16 ', the second barrier layer 23 ' and the residue conductor 18 ' that surrounded by the first barrier layer 16 ' and the second barrier layer 23 ' '.And the wire of semiconductor element obtained by the method for embodiment has level and smooth and even curface.
In classical production process, be formed at a conductive layer of also filling groove on dielectric layer, such as layers of copper, with CMP grinding, after grinding, the copper surface at groove place is generally coarse and irregular.And fillet (roundingcorner) can be produced at wire (as copper cash) and the intersection as the first barrier layer 16 '.But, can be confirmed by TEM result, according to the semiconductor element obtained by the manufacture method of embodiment, it remains conductor 18 ' ' there is smooth upper surface 181, and this upper surface 181 is substantially parallel to the upper surface 231 of the second barrier layer 23 ', and without fillet residue conductor 18 ' ' and the first barrier layer 16 ' intersection generation.Moreover TEM result also shows, the adhesion effect (adhesion) that between residue conductor 18 ' ' its surface roughness of flat upper surfaces 181 extremely low, therefore can make residue conductor 18 ' ' and the second barrier layer 23 ' of follow-up formation, tool is good.
Fig. 2 A and Fig. 2 B illustrates respectively with the upper schematic diagram of the wire of embodiment method and semiconductor element obtained in the conventional way.The wire of the semiconductor element obtained compared to tradition has coarse upper surface (Fig. 2 B), and the wire of the semiconductor element obtained with embodiment method has level and smooth upper surface (Fig. 2 A), and surface roughness is extremely low.
Moreover the wire (as copper cash) of tool rough surface, easily produces conductive species improperly excessive and form conducting bridge (conductivebridges), will cause semiconductor element operation failure after applying voltage operates.Fig. 3 produces the schematic diagram of unnecessary conducting bridge between groove after illustrating and applying voltage, wherein conducting bridge is the wire that bridge joint is adjacent, causes element operation to lose efficacy.
In addition, the rough surface of wire (as copper cash) will cause puncture voltage (breakdownvoltage) to decline.Fig. 4 is the schematic diagram that its time-dependence dielectric layer of wire of tool different surface roughness punctures test (time-dependentdielectricbreakdown, TDDB) and shows.According to the TDDB reliability analysis result of Fig. 4, surface roughness (Ra, center line average boldness) is about
wire, the puncture voltage of its element is about 1.7 (regular voltage, normalizedvoltage); And surface roughness (Ra) is about
wire, the puncture voltage of its element is about 1.9.Therefore, the result of Fig. 4 is pointed out, the performance of TDDB and the surface roughness of wire have strong relevant.The surface of wire is more level and smooth (surface roughness value is less), and puncture voltage is higher.
According to above-described embodiment, residue conductor 18 ' due in groove 14 ' by the first barrier layer 16 ' and the second barrier layer 23 ' surround (as referring to figure 1e), and there is good adhesion effect due to residue conductor 18 ' between ' have flat upper surfaces 181 caused and make residue conductor 18 ' ' and the second barrier layer 23 ', its characteristic electron according to the semiconductor element obtained by embodiment can significantly promote, such as improve the puncture voltage of semiconductor element, and the problem effectively avoided traditional element may produce the excessive formation conducting bridge connection adjacent wires of improper conductive species after service voltage and cause element operation to lose efficacy.
Moreover other enforcement aspects of different structure also can apply method of the present invention, and do suitable change and modification according to the demand of practical application to step details.Illustrating only as describing the use of embodiment therefore as Figure 1A ~ Fig. 1 E, but not as the use of limit scope.Therefore tool knows that the knowledgeable is known usually, and in structure, the shape of each element or relative position may be adjusted accordingly according to the difference of the structure of practical application and/or manufacturing process steps.
In sum, although disclose the present invention in conjunction with above embodiment, however itself and be not used to limit the present invention.Persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, can be used for a variety of modifications and variations.Therefore, what protection scope of the present invention should define with the claim of enclosing is as the criterion.
Claims (23)
1. a manufacture method for semiconductor element, comprising:
A substrate and a dielectric layer is provided to be formed on this substrate;
Form multiple groove in this dielectric layer place, and those grooves are separated with this dielectric layer;
Form one first barrier layer in those grooves, using the barrier liner as those grooves;
Fill a conductor in those grooves;
Part removes this conductor in those grooves to form multiple depression, removes rear this conductor remaining and has a flat surfaces; With
Form one second barrier layer in those recess, using the barrier lid as those grooves.
2. manufacture method as claimed in claim 1, this conductor wherein in those grooves is applied a chemical buffer liquid and is carried out part and remove, and this chemical buffer liquid comprises a derivative of Tetramethylammonium hydroxide (tetramethylammoniumhydroxide) and an amino alcohol (aminoalcohol) or amino alcohol.
3. manufacture method as claimed in claim 2, wherein applies this chemical buffer liquid this conductor in those grooves under pressure is not more than 5psi.
4. manufacture method as claimed in claim 1, wherein a upper surface of this conductor remaining is parallel to a upper surface of this second barrier layer.
5. manufacture method as claimed in claim 1, wherein this flat surfaces of this conductor remaining has a surface roughness and is not more than
6. manufacture method as claimed in claim 1, the wherein upper surface of this flat surfaces lower than this dielectric layer of this conductor remaining and a upper surface of this first barrier layer.
7. manufacture method as claimed in claim 6, wherein in those grooves, this conductor remaining covers with this second barrier layer, and this upper surface substantial alignment of this first barrier layer is in this upper surface of this second barrier layer.
8. manufacture method as claimed in claim 6, wherein in those grooves, this conductor remaining is surrounded by this first barrier layer and this second barrier layer.
9. manufacture method as claimed in claim 1, wherein degree of depth for those depressions are about
a scope in.
10. manufacture method as claimed in claim 1, wherein degree of depth for those depressions are about
a scope in.
11. manufacture methods as claimed in claim 1, wherein form this second barrier layer and comprise in the step of those recess:
Cover this second barrier layer on those grooves and this dielectric layer; With
Grind this second barrier layer until arrive at a upper surface of this dielectric layer.
12. manufacture methods as claimed in claim 1, wherein this first barrier layer and this second barrier layer comprise same material.
13. manufacture methods as claimed in claim 1, wherein this dielectric layer comprises a ultra low k dielectric material.
14. 1 kinds of semiconductor elements, comprising:
Substrate and dielectric layer are formed on this substrate; With
Many wires, be formed at this dielectric layer place, and those wires are separated with this dielectric layer, those wires one of them comprise:
Groove, is formed at this dielectric layer place;
First barrier layer, is formed at this groove, using the barrier liner as this groove;
Conductor, has a flat surfaces, and this groove is filled by this conductor part and formed a depression; With
Second barrier layer, is formed at this recess, using the barrier lid as this conductor.
15. semiconductor elements as claimed in claim 14, wherein this flat surfaces of this conductor remaining is parallel to a upper surface of this second barrier layer.
16. semiconductor elements as claimed in claim 14, wherein this flat surfaces of this conductor remaining has a surface roughness and is not more than
17. semiconductor elements as claimed in claim 14, the wherein upper surface of this flat upper surfaces lower than this dielectric layer of this conductor and a upper surface of this first barrier layer.
18. semiconductor elements as claimed in claim 17, wherein this upper surface substantial alignment of this first barrier layer is in a upper surface of this second barrier layer.
19. semiconductor elements as claimed in claim 17, wherein in those grooves, this conductor remaining is surrounded by this first barrier layer and this second barrier layer.
20. semiconductor elements as claimed in claim 14, wherein degree of depth for those depressions are about
a scope in.
21. semiconductor elements as claimed in claim 14, wherein degree of depth for those depressions are about
a scope in.
22. semiconductor elements as claimed in claim 14, wherein this first barrier layer and this second barrier layer make with same material.
23. semiconductor elements as claimed in claim 14, wherein this dielectric layer comprises a ultra low k dielectric material.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090243109A1 (en) * | 2008-03-31 | 2009-10-01 | Markus Nopper | Metal cap layer of increased electrode potential for copper-based metal regions in semiconductor devices |
| US20090283499A1 (en) * | 2003-10-20 | 2009-11-19 | Novellus Systems, Inc. | Fabrication of semiconductor interconnect structure |
| US8158532B2 (en) * | 2003-10-20 | 2012-04-17 | Novellus Systems, Inc. | Topography reduction and control by selective accelerator removal |
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- 2014-05-16 CN CN201410209279.4A patent/CN105097660B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090283499A1 (en) * | 2003-10-20 | 2009-11-19 | Novellus Systems, Inc. | Fabrication of semiconductor interconnect structure |
| US8158532B2 (en) * | 2003-10-20 | 2012-04-17 | Novellus Systems, Inc. | Topography reduction and control by selective accelerator removal |
| US20090243109A1 (en) * | 2008-03-31 | 2009-10-01 | Markus Nopper | Metal cap layer of increased electrode potential for copper-based metal regions in semiconductor devices |
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