CN105097468A - Flattening process - Google Patents
Flattening process Download PDFInfo
- Publication number
- CN105097468A CN105097468A CN201410217176.2A CN201410217176A CN105097468A CN 105097468 A CN105097468 A CN 105097468A CN 201410217176 A CN201410217176 A CN 201410217176A CN 105097468 A CN105097468 A CN 105097468A
- Authority
- CN
- China
- Prior art keywords
- polysilicon gate
- fin
- ion implantation
- photoresist
- planarization
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a flattening process which comprises the steps of providing insulation between fins; covering a polysilicon gate; performing ion implantation on polysilicon gate parts which project on the fins; and performing chemical and mechanical flattening. Because the crystalline state of each projected polysilicon part is damaged by an ion implantation process, a chemical corrosion function of a polishing fluid in chemical and mechanical flattening is improved, and an eliminating speed for the polysilicon gate at the top is improved, thereby reducing or preventing a difference between polysilicon material eliminating speeds caused by different pattern densities.
Description
Technical field
The present invention relates to field of semiconductor manufacture, the process of particularly a kind of planarization.
Background technology
Along with the size of planar semiconductor device constantly reduces, short-channel effect is more outstanding, raising grid-control ability becomes the emphasis direction in the exploitation of device generations, the multi-gate device of similar FinFet (fin formula field effect transistor), FinFet is the transistor with fin channel structure, it utilizes several surfaces of thin fin (Fin) as raceway groove, can increase operating current, thus can prevent the short-channel effect in conventional transistor.
Be different from planar device, as shown in Figure 1, the isolation structure 104 of FinFet device is formed in the protruding figure on the substrate 100 between fin 102, like this, in the technique forming polysilicon gate, as shown in Figure 2, after deposit polysilicon gate 106, need the planarization carrying out polysilicon gate, as shown in Figure 3, the polysilicon gate 106 after planarization carries out the etching of patterning further.
Because the distribution density of fin is different, what can cause the polysilicon gate of appropriate section removes speed difference, compared to the region that fin density is less, in the region that the density of fin is larger, protruding polysilicon gate partial pressing is lower, corresponding topical to remove speed slower, and owing to removing the difference of speed, the uniformity (WithinInWaferNon-Uniformity, WIWNU) of polycrystalline thickness in sheet can be caused poor.But FinFET is very high to the uniformity requirement of polysilicon gate flatening process, its uniformity determines the consistency of polysilicon gate height in wafer, and this can have an impact to the consistency of the final electrology characteristic of device.
Summary of the invention
Object of the present invention is intended at least solve above-mentioned technological deficiency, provides a kind of process of planarization, improves the uniformity of polysilicon gate planarization.
The invention provides a kind of process of planarization, comprise step:
Isolation between fin and fin is provided;
Cover polysilicon gate;
Ion implantation is carried out to the polysilicon gate part of the projection of fin;
Carry out chemical-mechanical planarization.
Optionally, the step that the polysilicon gate part of the projection of fin carries out ion implantation is specifically comprised:
On polysilicon, form the photoresist of patterning, the light shield when light shield forming this photoresist is the photoresist forming fin, and the polarity of photoresist when the polarity of this photoresist and formation fin is contrary;
Carry out ion implantation;
Remove photoresist.
Optionally, the degree of depth of ion implantation is less than or equal to the height of protruding polysilicon gate part.
Optionally, the ion of injection comprises: C, H, B, BF2, In, P, As, Sb, Ge, Si, F or their combination.
Optionally, the energy range of ion implantation is 1-1000KeV.
Optionally, the dosage range of ion implantation is 1E10-1E16cm
-2.
Optionally, the polishing fluid carrying out employing during chemical-mechanical planarization is SiO
2base polishing fluid or Al
2o
3base polishing fluid.
The process of the planarization that the embodiment of the present invention provides, after deposit polysilicon gate, ion implantation is carried out to the polysilicon gate part of the projection of fin, owing to have passed through ion implantation, protruding polysilicon gate partially crystallizable state is destroyed, this to strengthen in chemical-mechanical planarization polishing fluid greatly to the chemical corrosion effect of the polysilicon gate part of projection, that improves the polysilicon gate at top removes speed, thus reduce or avoid because pattern density is different and cause polycrystalline material to remove the difference of speed, thus improve the uniformity of polysilicon gate flatening process, improve the performance of device.
Accompanying drawing explanation
The present invention above-mentioned and/or additional aspect and advantage will become obvious and easy understand from the following description of the accompanying drawings of embodiments, wherein:
Fig. 1-3 shows the schematic cross-section of FinFet device polysilicon gate planarization process in prior art;
Fig. 4 shows the schematic flow sheet of the process of the planarization according to the embodiment of the present invention;
Fig. 5-8 shows the schematic cross-section forming each manufacture process of semiconductor device according to the technique of the embodiment of the present invention.
Embodiment
Be described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Being exemplary below by the embodiment be described with reference to the drawings, only for explaining the present invention, and can not limitation of the present invention being interpreted as.
As described in background, when FinFet device forms polysilicon gate, need to carry out flatening process, and the difference of distribution density due to fin, the problem of the uniformity of planarization can be caused, thus cause the inconsistency of device grids height, affect the performance of device.
In order to solve the above problems, the present invention proposes a kind of process of planarization, shown in figure 4, comprise:
Isolation between fin and fin is provided;
Cover polysilicon gate;
Ion implantation is carried out to the polysilicon gate part of the projection of fin;
Carry out chemical-mechanical planarization.
In the present invention, after deposit polysilicon gate, ion implantation is carried out to the polysilicon gate part of the projection of fin, owing to have passed through ion implantation, protruding polysilicon gate partially crystallizable state is destroyed, this to strengthen in chemical-mechanical planarization polishing fluid greatly to the chemical corrosion effect of the polysilicon gate part of projection, that improves the polysilicon gate at top removes speed, thus reduce or avoid because pattern density is different and cause polycrystalline material to remove the difference of speed, thus improve the uniformity of polysilicon gate flatening process, improve the performance of device.
For a better understanding of the present invention, be described in detail below with reference to manufacturing process and specific embodiment.
First, in step S01, provide the isolation 204 between fin 202 and fin, as shown in Figure 5.
In the present embodiment, first, substrate 200 is provided.
In the present invention, described substrate can be the Semiconductor substrate such as Si substrate, Ge substrate, SiGe substrate, SOI (silicon-on-insulator, SiliconOnInsulator) or GOI (germanium on insulator, GermaniumOnInsulator).In the present embodiment, described substrate is silicon substrate
Then, in described substrate, fin 202 is formed.
Can by forming hard mask (scheming not shown) on the substrate 200, such as silicon nitride, under the sheltering of hard mask, utilize lithographic technique, the such as method of RIE (reactive ion etching), etched substrate, thus in substrate, form fin 202, then, can further hard mask be removed.
Then, between fin, isolation 204 is formed.
The dielectric material of deposit isolation, such as unadulterated silica (SiO
2), the silica (as Pyrex, boron-phosphorosilicate glass etc.) etc. of doping, and carry out planarization, such as CMP (chemico-mechanical polishing), carry out wet etching afterwards, thus obtain isolation 204.
Then, in step S02, cover polysilicon gate 206, as shown in Figure 6.
Deposit polysilicon gate material on above-mentioned device, such as polycrystalline silicon material, covers upper polysilicon gate by above-mentioned isolation 204 and fin 202.Because fin is the structure protruded, after deposit polysilicon gate material, the polysilicon gate 206-1 on fin exceeds certain altitude H compared to the polysilicon gate 206-2 in isolation.
Then, in step S03, ion implantation is carried out to the polysilicon gate part 206-1 of the projection of fin.
In the present embodiment, the mask layer 208 of photoresist is covered by the part on isolation 204, the polysilicon gate part 206-1 of the projection of fin is carried out ion implantation, more specifically, the light shield when light shield adopted when forming the photoresist of patterning on polysilicon is the photoresist of formation fin, and the polarity of the polarity of this photoresist and photoresist when forming fin is contrary, such as, forming the photoresist of fin is positive photoresist, then, photoresist when carrying out now ion implantation is negativity.That is, now ion implantation is same with light shield when forming fin, adopts the photoresist of opposed polarity simultaneously, like this, can use the light shield of fin when ion implantation, without the need to again developing the light shield of new ion implantation, reduces development cost.
In the particular embodiment, the condition of suitable ion implantation can be selected by simulated experiment in advance, make the degree of depth of ion implantation be less than or equal to the height of protruding polysilicon gate part.Inject the Implantation Energy of the degree of depth mainly through ion implantation, and the annealing temperature after injecting regulates, can first with conventional ion implantation simulation software, as srim, simulate the diurnal concentration variation that different ions is injected, the ion injected can be C, H, B, BF2, In, P, As, Sb, Ge, Si, F or their combination, and the energy range of ion implantation can be 1-1000KeV, and the dosage range of ion implantation can be 1E10-1E16cm
-2.After ion implantation, photoresist is removed.
Then, in step S04, carry out chemical-mechanical planarization, as shown in Figure 8.
The chemical planarization technique of traditional polysilicon gate can be adopted to carry out planarization, until arrive the thickness of predetermined polysilicon gate.
In the present embodiment, the polishing fluid carrying out employing during chemical-mechanical planarization is SiO
2base polishing fluid or Al
2o
3base polishing fluid, polishing pad can adopt hard or soft polishing pad.Because the crystalline state of the polysilicon gate part of projection is destroyed by ion implantation technology, to which enhance in chemical-mechanical planarization polishing fluid to the chemical corrosion effect of the polysilicon gate part of projection, that improves the polysilicon gate at top removes speed, thus reduces or avoid because pattern density is different and cause polycrystalline material to remove the difference of speed.
Then, can according to the concrete subsequent technique having needed device, as the patterning etc. of grid.
The above is only preferred embodiment of the present invention, not does any pro forma restriction to the present invention.
Although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention.Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (7)
1. a process for planarization, is characterized in that, comprises step:
Isolation between fin and fin is provided;
Cover polysilicon gate;
Ion implantation is carried out to the polysilicon gate part of the projection of fin;
Carry out chemical-mechanical planarization.
2. method according to claim 1, is characterized in that, the step of the polysilicon gate part of the projection of fin being carried out to ion implantation specifically comprises:
On polysilicon, form the photoresist of patterning, the light shield when light shield forming this photoresist is the photoresist forming fin, and the polarity of photoresist when the polarity of this photoresist and formation fin is contrary;
Carry out ion implantation;
Remove photoresist.
3. method according to claim 1, is characterized in that, the degree of depth of ion implantation is less than or equal to the height of protruding polysilicon gate part.
4. method according to claim 3, is characterized in that, the ion of injection comprises: C, H, B, BF2, In, P, As, Sb, Ge, Si, F or their combination.
5. method according to claim 4, is characterized in that, the energy range of ion implantation is 1-1000KeV.
6. method according to claim 5, is characterized in that, the dosage range of ion implantation is 1E10-1E16cm
-2.
7. method according to claim 1, is characterized in that, the polishing fluid carrying out employing during chemical-mechanical planarization is SiO
2base polishing fluid or Al
2o
3base polishing fluid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410217176.2A CN105097468A (en) | 2014-05-21 | 2014-05-21 | Flattening process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410217176.2A CN105097468A (en) | 2014-05-21 | 2014-05-21 | Flattening process |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105097468A true CN105097468A (en) | 2015-11-25 |
Family
ID=54577637
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410217176.2A Pending CN105097468A (en) | 2014-05-21 | 2014-05-21 | Flattening process |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105097468A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102789974A (en) * | 2011-05-16 | 2012-11-21 | 中国科学院微电子研究所 | Method for improving uniformity of shallow trench isolation chemical-mechanical planarization |
| US20130102116A1 (en) * | 2010-01-08 | 2013-04-25 | Semiconductor Manufacturing International (Shanghai) Corporation | Hybrid integrated semiconductor tri-gate and split dual-gate finfet devices and method for manufacturing |
| CN103311111A (en) * | 2012-03-16 | 2013-09-18 | 中芯国际集成电路制造(上海)有限公司 | Forming method of fin type transistor |
| CN104282564A (en) * | 2013-07-03 | 2015-01-14 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device and method for forming fin field effect transistor |
-
2014
- 2014-05-21 CN CN201410217176.2A patent/CN105097468A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130102116A1 (en) * | 2010-01-08 | 2013-04-25 | Semiconductor Manufacturing International (Shanghai) Corporation | Hybrid integrated semiconductor tri-gate and split dual-gate finfet devices and method for manufacturing |
| CN102789974A (en) * | 2011-05-16 | 2012-11-21 | 中国科学院微电子研究所 | Method for improving uniformity of shallow trench isolation chemical-mechanical planarization |
| CN103311111A (en) * | 2012-03-16 | 2013-09-18 | 中芯国际集成电路制造(上海)有限公司 | Forming method of fin type transistor |
| CN104282564A (en) * | 2013-07-03 | 2015-01-14 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device and method for forming fin field effect transistor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9023715B2 (en) | Methods of forming bulk FinFET devices so as to reduce punch through leakage currents | |
| US8728885B1 (en) | Methods of forming a three-dimensional semiconductor device with a nanowire channel structure | |
| US9524910B2 (en) | Semiconductor device and method for manufacturing the same | |
| US20150270263A1 (en) | Semiconductor device and method for manufacturing the same | |
| US9627268B2 (en) | Method for fabricating semiconductor device | |
| CN203553173U (en) | Electronic device | |
| CN102446972A (en) | Transistor having notched fin structure and method of making the same | |
| US20150303192A1 (en) | Semiconductor device and method for manufacturing the same | |
| KR20110049806A (en) | Method of forming finned semiconductor devices with trench isolation | |
| US9318372B2 (en) | Method of stressing a semiconductor layer | |
| US10319839B2 (en) | Semiconductor structure and fabrication method thereof | |
| US20150311123A1 (en) | Semiconductor device and method for manufacturing the same | |
| US9478634B2 (en) | Methods of forming replacement gate structures on finFET devices and the resulting devices | |
| SG195453A1 (en) | Methods of forming finfet devices with alternative channel materials | |
| US8877588B2 (en) | Methods of forming a three-dimensional semiconductor device with a dual stress channel and the resulting device | |
| CN106158748B (en) | Semiconductor element and manufacturing method thereof | |
| US20150318349A1 (en) | Semiconductor device and method for manufacturing the same | |
| CN105097434A (en) | Flattening process | |
| TW201601199A (en) | Methods of forming a nanowire device with a gate-all-around-channel configuration and the resulting nanowire device | |
| CN104064469A (en) | Manufacturing method of semiconductor device | |
| US9543214B2 (en) | Method of forming stressed semiconductor layer | |
| US9305828B2 (en) | Method of forming stressed SOI layer | |
| CN106856190A (en) | The forming method of semiconductor structure | |
| TWI624948B (en) | Methods of forming strained channel regions on finfet devices | |
| CN105097468A (en) | Flattening process |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20151125 |
|
| RJ01 | Rejection of invention patent application after publication |