CN105097434A - Planarization process method - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 230000008569 process Effects 0.000 title claims abstract description 23
- 239000000463 material Substances 0.000 claims abstract description 41
- 238000005498 polishing Methods 0.000 claims abstract description 27
- 238000002955 isolation Methods 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 14
- 239000003989 dielectric material Substances 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005429 filling process Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000000265 homogenisation Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
本发明提供了一种平坦化的工艺方法，包括步骤：填充材料层；获得片内材料层的厚度数据；根据抛光头压力区间的划分，获得片内各相应区间的材料层的平均厚度THKn；根据各区间的材料层的平均厚度THKn，调整抛光头各压力区间的压力值参数Pn，进行平坦化。本发明根据各区间填充的材料层的平均厚度来调整抛光头各压力区间的压力值参数，进而进行平坦化，以调整不同区间的移除速率，从而改善多晶栅平坦化工艺的均匀性，提高器件的性能。
The invention provides a flattening process, comprising the steps of: filling the material layer; obtaining the thickness data of the material layer in the chip; according to the division of the pressure interval of the polishing head, obtaining the average thickness THK n of the material layer in each corresponding interval in the chip ; According to the average thickness THK n of the material layer in each interval, adjust the pressure value parameter P n of each pressure interval of the polishing head to perform planarization. The present invention adjusts the pressure parameter of each pressure zone of the polishing head according to the average thickness of the material layer filled in each zone, and then performs planarization to adjust the removal rate of different zones, thereby improving the uniformity of the polycrystalline gate planarization process. improve device performance.
Description
技术领域technical field
本发明涉及半导体制造领域，特别涉及一种平坦化的工艺方法。The invention relates to the field of semiconductor manufacturing, in particular to a planarization process method.
背景技术Background technique
随着平面半导体器件的尺寸不断缩小，短沟道效应愈发突出，提高栅控能力成为下一代器件的开发中的重点方向，类似FinFet(鳍式场效应晶体管)的多栅器件，FinFet是具有鳍型沟道结构的晶体管，它利用薄鳍(Fin)的几个表面作为沟道，可以增大工作电流，从而可以防止传统晶体管中的短沟道效应。As the size of planar semiconductor devices continues to shrink, the short-channel effect becomes more and more prominent. Improving gate control capabilities has become a key direction in the development of next-generation devices. Similar to FinFet (Fin Field Effect Transistor) multi-gate devices, FinFet is a multi-gate device with A transistor with a fin-type channel structure, which uses several surfaces of a thin fin (Fin) as a channel, can increase the operating current, thereby preventing the short-channel effect in traditional transistors.
不同于平面器件，如图1所示，FinFet器件制造工艺中，在形成鳍102沟道之后，进行隔离材料104如二氧化硅的填充，而后，进行平坦化，直至暴露鳍102的顶部，如图2所示，如鳍上的盖层氮化硅，进而，进行进行部分刻蚀，形成隔离结构106，如图3所示。Different from the planar device, as shown in FIG. 1 , in the manufacturing process of the FinFet device, after the channel of the fin 102 is formed, the isolation material 104 such as silicon dioxide is filled, and then planarized until the top of the fin 102 is exposed, such as As shown in FIG. 2 , for example, the cap layer silicon nitride on the fin is partially etched to form an isolation structure 106 , as shown in FIG. 3 .
在目前，隔离材料的化学机械平坦化(CMP)工艺中，由于沟槽深度的差异以及填充工艺的差异，会导致平坦化均匀性的差异，然而，FinFET器件对沟槽平坦化工艺的均匀性要求很高，其均匀性决定了晶圆内多晶栅高度的一致性，这会对器件最终电学特性的一致性产生影响。In the current chemical mechanical planarization (CMP) process of isolation materials, differences in planarization uniformity will result due to differences in trench depth and filling processes. However, the uniformity of FinFET devices for trench planarization processes The requirements are very high, and its uniformity determines the consistency of the polysilicon gate height in the wafer, which will affect the consistency of the final electrical characteristics of the device.
发明内容Contents of the invention
本发明的目的旨在至少解决上述技术缺陷，提供一种平坦化的工艺方法，提高多晶栅平坦化的均匀性。The purpose of the present invention is to at least solve the above-mentioned technical defects, provide a planarization process method, and improve the uniformity of polycrystalline gate planarization.
本发明提供了一种平坦化的工艺方法，包括步骤：The invention provides a flattening process method, comprising the steps of:
填充材料层；layer of filling material;
获得片内材料层的厚度数据；Obtain the thickness data of the material layer in the chip;
根据抛光头压力区间的划分，获得片内各相应区间的材料层的平均厚度THKn；According to the division of the pressure interval of the polishing head, the average thickness THK n of the material layer in each corresponding interval in the sheet is obtained;
根据各区间的材料层的平均厚度THKn，调整抛光头各压力区间的压力值参数Pn，进行平坦化。According to the average thickness THK n of the material layer in each interval, the pressure value parameter P n of each pressure interval of the polishing head is adjusted to perform planarization.
可选的，压力值参数Pn＝(PBLn*THKn)/ThkBLn，其中，PBLn为该材料层的各压力区间的基线移除压力，ThkBLn为该材料层的各区间的基线厚度。Optionally, the pressure value parameter P n =(P BLn *THK n )/Thk BLn , wherein, P BLn is the baseline removal pressure of each pressure interval of the material layer, and Thk BLn is the baseline of each interval of the material layer thickness.
可选的，抛光头压力区间的数量为5。Optionally, the number of pressure intervals of the polishing head is five.
可选的，所述填充材料层的步骤具体为：Optionally, the step of filling the material layer is specifically:
在衬底上形成鳍之后，填充隔离材料的材料层。After the fins are formed on the substrate, a material layer of isolation material is filled.
本发明实施例提供的平坦化的工艺方法，根据各区间填充的材料层的平均厚度来调整抛光头各压力区间的压力值参数，进而进行平坦化，各区间的材料层的厚度可以反映由于刻蚀或填充造成的材料厚度的不同，根据其进行压力的调整，调整不同区间的移除速率，从而改善多晶栅平坦化工艺的均匀性，提高器件的性能。The planarization process method provided by the embodiment of the present invention adjusts the pressure value parameters of each pressure interval of the polishing head according to the average thickness of the material layer filled in each interval, and then performs planarization. The thickness of the material layer in each interval can reflect the According to the difference in material thickness caused by etching or filling, the pressure is adjusted according to it, and the removal rate in different intervals is adjusted, so as to improve the uniformity of the polycrystalline gate planarization process and improve the performance of the device.
附图说明Description of drawings
本发明上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解，其中：The above and/or additional aspects and advantages of the present invention will become apparent and easy to understand from the following description of the embodiments in conjunction with the accompanying drawings, wherein:
图1-3示出了FinFet器件隔离结构平坦化过程的截面示意图；Figure 1-3 shows a schematic cross-sectional view of the planarization process of the isolation structure of the FinFet device;
图4示出了根据本发明实施例的平坦化的工艺方法的流程示意图。FIG. 4 shows a schematic flowchart of a planarization process method according to an embodiment of the present invention.
具体实施方式Detailed ways
下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能解释为对本发明的限制。Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention.
正如背景技术所述，在FinFet器件形成隔离结构时，进行隔离材料填充后进行平坦化工艺，由于在进行鳍刻蚀过程中以及后续填充工艺的过程中，都有可能导致隔离材料厚度上的差异，这会导致平坦化均匀性的差异，导致器件电学特性一致性的差异。As mentioned in the background technology, when the FinFet device forms the isolation structure, the planarization process is performed after the isolation material is filled, because the difference in the thickness of the isolation material may be caused during the fin etching process and the subsequent filling process. , which can lead to differences in planarization uniformity, resulting in differences in the consistency of device electrical characteristics.
为了解决上述的问题，本发明提出了一种平坦化的工艺方法，参考图4所示，包括：In order to solve the above problems, the present invention proposes a planarization process, as shown in Figure 4, including:
填充材料层；layer of filling material;
获得片内材料层的厚度数据；Obtain the thickness data of the material layer in the chip;
根据抛光头压力区间的划分，获得片内各相应区间的材料层的平均厚度THKn；According to the division of the pressure interval of the polishing head, the average thickness THK n of the material layer in each corresponding interval in the sheet is obtained;
根据各区间的材料层的平均厚度，调整抛光头各压力区间的压力值参数Pn，进行平坦化。According to the average thickness of the material layer in each interval, the pressure value parameter P n of each pressure interval of the polishing head is adjusted to perform planarization.
在本发明中，根据各区间填充的材料层的平均厚度来调整抛光头各压力区间的压力值参数，进而进行平坦化，各区间的材料层的厚度可以反映由于刻蚀或填充造成的材料厚度的不同，根据其进行压力的调整，调整不同区间的移除速率，从而改善多晶栅平坦化工艺的均匀性，提高器件的性能。In the present invention, the pressure value parameters of each pressure zone of the polishing head are adjusted according to the average thickness of the material layer filled in each zone, and then planarized, and the thickness of the material layer in each zone can reflect the material thickness caused by etching or filling According to the pressure adjustment, the removal rate in different intervals is adjusted, so as to improve the uniformity of the polycrystalline gate planarization process and improve the performance of the device.
为了更好的理解本发明，以下将结合制造流程以及具体的实施例进行详细的描述。在本实施例中，是在FinFet器件形成隔离结构时，利用上述方法进行平坦化，可以理解的是，在其他器件或结构的平坦化时，也可以采用上述方法进行。In order to better understand the present invention, the following will be described in detail in conjunction with the manufacturing process and specific embodiments. In this embodiment, the above-mentioned method is used for planarization when forming the isolation structure of the FinFET device. It can be understood that the above-mentioned method can also be used for planarization of other devices or structures.
首先，提供衬底100，参考图1。First, a substrate 100 is provided, refer to FIG. 1 .
在本发明中，所述衬底可以为Si衬底、Ge衬底、SiGe衬底、SOI(绝缘体上硅，SiliconOnInsulator)或GOI(绝缘体上锗，GermaniumOnInsulator)等半导体衬底。在本实施例中，所述衬底为硅衬底。In the present invention, the substrate may be a semiconductor substrate such as Si substrate, Ge substrate, SiGe substrate, SOI (Silicon On Insulator, Silicon On Insulator) or GOI (Germanium On Insulator, Germanium On Insulator). In this embodiment, the substrate is a silicon substrate.
接着，在衬底内形成鳍102，参考图1所示。Next, fins 102 are formed in the substrate, as shown in FIG. 1 .
可以通过在衬底100上形成硬掩膜(图未示出)，例如氮化硅，在硬掩膜的掩蔽下，利用刻蚀技术，例如RIE(反应离子刻蚀)的方法，刻蚀衬底，从而在衬底内形成鳍102，而后，可以进一步将硬掩膜去除。A hard mask (not shown), such as silicon nitride, may be formed on the substrate 100. Under the cover of the hard mask, an etching technique, such as RIE (Reactive Ion Etching), is used to etch the substrate 100. bottom, thereby forming fins 102 in the substrate, and then, the hard mask can be further removed.
而后，进行隔离材料104的填充，如图1所示。Then, filling of the isolation material 104 is performed, as shown in FIG. 1 .
可以淀积隔离的介质材料，例如未掺杂的氧化硅(SiO2)、掺杂的氧化硅(如硼硅玻璃、硼磷硅玻璃等)等。Isolation dielectric materials can be deposited, such as undoped silicon oxide (SiO 2 ), doped silicon oxide (such as borosilicate glass, borophosphosilicate glass, etc.), and the like.
接着，获得片内隔离材料的厚度数据。Next, the thickness data of the isolation material in the chip is obtained.
可以通过传统的膜厚测量来获得晶片内介质材料厚度分布数据，通常的，可以根据需要来选取分布的测试点，通常遍布晶片的不同区域，例如可以为不同区域的49点测试数据。The thickness distribution data of the dielectric material in the wafer can be obtained by traditional film thickness measurement. Generally, distributed test points can be selected according to needs, usually all over different areas of the wafer, for example, 49 points of test data in different areas can be obtained.
而后，根据抛光头压力区间的划分，获得片内各相应区间的介质材料的平均厚度。Then, according to the division of the pressure interval of the polishing head, the average thickness of the dielectric material in each corresponding interval in the chip is obtained.
通常的CMP的抛光设备，为了更好的保证抛光的均匀性，通常地，CMP的抛光设备抛光头有根据可控压力进行区间的分配，例如对于12英寸(300mm)的抛光头，其被划分为按圆心分布的5个区间，按半径从中心至边缘分别是，zone1:0-40mm；zone2:40-70mm；zone3:70-100mm；zone4:100-130mm；zone5:130-150mm。Common CMP polishing equipment, in order to better ensure the uniformity of polishing, usually, the polishing head of CMP polishing equipment has interval distribution according to the controllable pressure, for example, for a 12-inch (300mm) polishing head, it is divided There are 5 zones distributed according to the center of the circle, from the center to the edge according to the radius, zone1: 0-40mm; zone2: 40-70mm; zone3: 70-100mm; zone4: 100-130mm; zone5: 130-150mm.
相应地，晶片根据抛光头压力区间的划分，也划分为按圆心分布的5个区间，并将相应区间内的介质材料的厚度进行计算，获得各相应区间的介质材料的平均厚度THKn，n＝1,2,3,4,5。Correspondingly, according to the division of the pressure range of the polishing head, the wafer is also divided into 5 intervals distributed according to the center of the circle, and the thickness of the dielectric material in the corresponding interval is calculated to obtain the average thickness THK n of the dielectric material in each corresponding interval, n =1,2,3,4,5.
接着，根据各区间的介质材料的平均厚度THKn，调整抛光头各压力区间的压力值参数Pn，进行平坦化。Next, according to the average thickness THK n of the dielectric material in each zone, the pressure value parameter P n of each pressure zone of the polishing head is adjusted to perform planarization.
也就是说，依据基线(baseline)工艺的介质材料的厚度对应的基线抛光头的压力，对各区间的抛光头压力进行压力补偿，高于baseline的进行压力增加，低于baseline的进行压力减小。That is to say, according to the pressure of the baseline polishing head corresponding to the thickness of the dielectric material of the baseline process, the pressure of the polishing head in each interval is pressure compensated. The pressure higher than the baseline increases, and the pressure lower than the baseline decreases. .
在本实施例中，根据材料移除速率公式R＝K*P*V＝THK/t，其中R为移除速率，K为材料移除系数，P是抛光头压力，V是抛光头转速，THK为移除厚度，t为移除时间。其中，抛光头转速对每个区间是一致的，可计算出相对于各压力区间需要调整的压力参数，即Pn＝(PBLn*THKn)/THKBLn，(n＝1,2,3,4,5)，其中，PBLn为该介质材料的各压力区间的基线移除压力，THKBLn为该介质材料的各区间的基线厚度。In this embodiment, according to the material removal rate formula R=K*P*V=THK/t, wherein R is the removal rate, K is the material removal coefficient, P is the pressure of the polishing head, and V is the rotational speed of the polishing head, THK is the removal thickness, and t is the removal time. Wherein, the rotational speed of the polishing head is consistent for each interval, and the pressure parameters that need to be adjusted relative to each pressure interval can be calculated, that is, P n =(P BLn *THK n )/THK BLn , (n=1,2,3 ,4,5), wherein, P BLn is the baseline removal pressure of each pressure interval of the dielectric material, and THK BLn is the baseline thickness of each interval of the dielectric material.
在一个具体的实施例中，CMP工艺中zone1～zone5基准压力PBL1，PBL2，PBL3，PBL4，PBL5分别为1.72psi，1.58psi，1.63psi，1.84psi，2.3psi，基线厚度为6000A，晶片的各区间的平均厚度为THK1:6340A；THK2:6070A；THK3:5910A；THK4:5850A；THK5:6270A；这样，得到进行平坦化的抛光头各压力区间的压力值参数，P1，P2，P3，P4，P5分别为1.82psi，1.60psi，1.61psi，1.79psi，2.4psi，可以根据此压力值更改抛光头各区间的压力值，以保证平坦化的均匀性。In a specific embodiment, in the CMP process, the reference pressures P BL1 , P BL2 , P BL3 , P BL4 , and P BL5 in zone1- zone5 are 1.72psi, 1.58psi, 1.63psi, 1.84psi, 2.3psi respectively, and the baseline thickness is 6000A, the average thickness of each section of wafer is THK 1 :6340A; THK 2 :6070A; THK 3 :5910A; THK 4 :5850A; THK 5 :6270A; Parameters, P 1 , P 2 , P 3 , P 4 , P 5 are 1.82psi, 1.60psi, 1.61psi, 1.79psi, 2.4psi respectively, you can change the pressure value of each section of the polishing head according to this pressure value to ensure flatness Uniformity of homogenization.
在平坦化后，进行湿法腐蚀，得到隔离器件106，参考图3所示。After planarization, wet etching is performed to obtain the isolation device 106 , as shown in FIG. 3 .
而后，可以根据具体的需要完成器件的后续工艺，如栅极结构的形成等。Then, the subsequent process of the device, such as the formation of the gate structure, can be completed according to specific needs.
以上所述，仅是本发明的较佳实施例而已，并非对本发明作任何形式上的限制。The above descriptions are only preferred embodiments of the present invention, and do not limit the present invention in any form.
虽然本发明已以较佳实施例披露如上，然而并非用以限定本发明。任何熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭示的方法和技术内容对本发明技术方案作出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person familiar with the art, without departing from the scope of the technical solution of the present invention, can use the methods and technical content disclosed above to make many possible changes and modifications to the technical solution of the present invention, or modify it into an equivalent implementation of equivalent changes example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the technical solution of the present invention, still fall within the protection scope of the technical solution of the present invention.
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| CN106384725A (en) * | 2016-10-11 | 2017-02-08 | 天津华海清科机电科技有限公司 | Silicon through hole wafer flattening method |
| CN107919296A (en) * | 2017-11-16 | 2018-04-17 | 德淮半导体有限公司 | The forming method and its processing unit (plant) of semiconductor structure |
| CN111975469A (en) * | 2020-08-28 | 2020-11-24 | 上海华力微电子有限公司 | Chemical mechanical polishing method and polishing system |
| CN114952600A (en) * | 2022-07-11 | 2022-08-30 | 赛莱克斯微系统科技（北京）有限公司 | Flattening method and device for high-frequency transmission microstructure and electronic equipment |
| CN115101471A (en) * | 2022-03-21 | 2022-09-23 | 康劲 | Process control method for multilayer copper interconnection CMP |
| CN115385295A (en) * | 2022-04-19 | 2022-11-25 | 赛莱克斯微系统科技（北京）有限公司 | Micro-system film planarization method |
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