CN105097434A - Planarization process method - Google Patents
Planarization process method Download PDFInfo
- Publication number
- CN105097434A CN105097434A CN201410217592.2A CN201410217592A CN105097434A CN 105097434 A CN105097434 A CN 105097434A CN 201410217592 A CN201410217592 A CN 201410217592A CN 105097434 A CN105097434 A CN 105097434A
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- China
- Prior art keywords
- material layer
- interval
- thk
- planarization
- rubbing head
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Links
- 238000000034 method Methods 0.000 title claims abstract description 33
- 230000008569 process Effects 0.000 title claims abstract description 23
- 239000000463 material Substances 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims description 14
- 239000008393 encapsulating agent Substances 0.000 claims description 5
- 238000005498 polishing Methods 0.000 abstract description 4
- 239000000945 filler Substances 0.000 abstract 1
- 239000003989 dielectric material Substances 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 1
- 241001269238 Data Species 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000005297 pyrex Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000011435 rock Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a planarization process method, which comprises the following steps: a layer of filler material; obtaining thickness data of the material layer in the sheet; according to the division of the pressure interval of the polishing head, the average thickness THK of the material layer in each corresponding interval in the sheet is obtainedn(ii) a According to the average thickness THK of the material layer in each intervalnAdjusting pressure value parameter P of each pressure interval of polishing headnAnd carrying out planarization. The pressure value parameters of each pressure interval of the polishing head are adjusted according to the average thickness of the material layer filled in each interval, so that planarization is performed, the removal rate of different intervals is adjusted, the uniformity of the polycrystalline grid planarization process is improved, and the performance of a device is improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, the process of particularly a kind of planarization.
Background technology
Along with the size of planar semiconductor device constantly reduces, short-channel effect is more outstanding, raising grid-control ability becomes the emphasis direction in the exploitation of device generations, the multi-gate device of similar FinFet (fin formula field effect transistor), FinFet is the transistor with fin channel structure, it utilizes several surfaces of thin fin (Fin) as raceway groove, can increase operating current, thus can prevent the short-channel effect in conventional transistor.
Be different from planar device, as shown in Figure 1, in FinFet device fabrication, after formation fin 102 raceway groove, carry out the filling of isolated material 104 as silicon dioxide, then, carry out planarization, until expose the top of fin 102, as shown in Figure 2, as the cap rock silicon nitride on fin, and then, carry out partial etching, form isolation structure 106, as shown in Figure 3.
At present, in chemical-mechanical planarization (CMP) technique of isolated material, due to the difference of gash depth and the difference of fill process, the difference of planarization uniformity can be caused, but, FinFET is very high to the uniformity requirement of trench flat metallization processes, and its uniformity determines the consistency of polysilicon gate height in wafer, and this can have an impact to the consistency of the final electrology characteristic of device.
Summary of the invention
Object of the present invention is intended at least solve above-mentioned technological deficiency, provides a kind of process of planarization, improves the uniformity of polysilicon gate planarization.
The invention provides a kind of process of planarization, comprise step:
Encapsulant layer;
Obtain the thickness data of material layer in sheet;
According to the division of rubbing head pressure range, obtain the average thickness THK of the material layer of each respective bins in sheet
n;
According to the average thickness THK of the material layer in each interval
n, the force value parameter P of each pressure range of adjustment rubbing head
n, carry out planarization.
Optionally, force value parameter P
n=(P
bLn* THK
n)/Thk
bLn, wherein, P
bLnfor the baseline of each pressure range of this material layer removes pressure, Thk
bLnfor the thickness of baseline in each interval of this material layer.
Optionally, the quantity of rubbing head pressure range is 5.
Optionally, the step of described encapsulant layer is specially:
After substrate forms fin, fill the material layer of isolated material.
The process of the planarization that the embodiment of the present invention provides, the force value parameter of each pressure range of rubbing head is adjusted according to the average thickness of the material layer of each interval filling, and then carry out planarization, the thickness of the material layer in each interval can reflect due to etching or the difference of filling the material thickness caused, the adjustment of pressure is carried out according to it, what adjustment difference was interval removes speed, thus improves the uniformity of polysilicon gate flatening process, improves the performance of device.
Accompanying drawing explanation
The present invention above-mentioned and/or additional aspect and advantage will become obvious and easy understand from the following description of the accompanying drawings of embodiments, wherein:
Fig. 1-3 shows the schematic cross-section of FinFet device isolation structure planarization process;
Fig. 4 shows the schematic flow sheet of the process of the planarization according to the embodiment of the present invention.
Embodiment
Be described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Being exemplary below by the embodiment be described with reference to the drawings, only for explaining the present invention, and can not limitation of the present invention being interpreted as.
As described in background, when FinFet device forms isolation structure, flatening process is carried out after carrying out isolated material filling, owing to carrying out in fin etching process and in the process of follow-up fill process, all likely cause the difference on isolated material thickness, this can cause the difference of planarization uniformity, causes the conforming difference of device electrology characteristic.
In order to solve the above problems, the present invention proposes a kind of process of planarization, shown in figure 4, comprise:
Encapsulant layer;
Obtain the thickness data of material layer in sheet;
According to the division of rubbing head pressure range, obtain the average thickness THK of the material layer of each respective bins in sheet
n;
According to the average thickness of the material layer in each interval, the force value parameter P of each pressure range of adjustment rubbing head
n, carry out planarization.
In the present invention, the force value parameter of each pressure range of rubbing head is adjusted according to the average thickness of the material layer of each interval filling, and then carry out planarization, the thickness of the material layer in each interval can reflect due to etching or the difference of filling the material thickness caused, the adjustment of pressure is carried out according to it, what adjustment difference was interval removes speed, thus improves the uniformity of polysilicon gate flatening process, improves the performance of device.
For a better understanding of the present invention, be described in detail below with reference to manufacturing process and specific embodiment.In the present embodiment, be when FinFet device forms isolation structure, utilize said method to carry out planarization, be understandable that, when the planarization of other devices or structure, said method also can be adopted to carry out.
First, provide substrate 100, with reference to figure 1.
In the present invention, described substrate can be the Semiconductor substrate such as Si substrate, Ge substrate, SiGe substrate, SOI (silicon-on-insulator, SiliconOnInsulator) or GOI (germanium on insulator, GermaniumOnInsulator).In the present embodiment, described substrate is silicon substrate.
Then, in substrate, fin 102 is formed, shown in figure 1.
Can by forming hard mask (scheming not shown) on the substrate 100, such as silicon nitride, under the sheltering of hard mask, utilize lithographic technique, the such as method of RIE (reactive ion etching), etched substrate, thus in substrate, form fin 102, then, can further hard mask be removed.
Then, the filling of isolated material 104 is carried out, as shown in Figure 1.
Can deposit isolation dielectric material, such as unadulterated silica (SiO
2), doping silica (as Pyrex, boron-phosphorosilicate glass etc.) etc.
Then, the thickness data of isolated material in sheet is obtained.
Can be obtained dielectric material thickness profile data in wafer by traditional film thickness measuring, common, can choose the test point of distribution as required, usually spread all over the zones of different of wafer, such as, can be 49 test datas of zones of different.
Then, according to the division of rubbing head pressure range, obtain the average thickness of the dielectric material of each respective bins in sheet.
The polissoir of common CMP, in order to better ensure the uniformity of polishing, normally, the with good grounds controllable pressure of polissoir rubbing head of CMP carries out interval distribution, such as the rubbing head of 12 inches (300mm), it is divided into 5 intervals by center of circle distribution, by radius from the center to edge respectively, and zone1:0-40mm; Zone2:40-70mm; Zone3:70-100mm; Zone4:100-130mm; Zone5:130-150mm.
Correspondingly, wafer, according to the division of rubbing head pressure range, is also divided into 5 intervals by center of circle distribution, and is calculated by the thickness of the dielectric material in respective bins, obtain the average thickness THK of the dielectric material of each respective bins
n, n=1,2,3,4,5.
Then, according to the average thickness THK of the dielectric material in each interval
n, the force value parameter P of each pressure range of adjustment rubbing head
n, carry out planarization.
That is, according to the pressure of baseline rubbing head corresponding to the thickness of dielectric material of baseline (baseline) technique, pressure compensation is carried out to the rubbing head pressure in each interval, carries out pressure increase higher than baseline, carry out pressure reduction lower than baseline.
In the present embodiment, according to material removal rate formula R=K*P*V=THK/t, wherein R is for removing speed, and K is that material removes coefficient, and P is rubbing head pressure, and V is rubbing head rotating speed, and THK is for removing thickness, and t is for removing the time.Wherein, rubbing head rotating speed is consistent to each interval, can calculate the pressure parameter needing adjustment relative to each pressure range, i.e. P
n=(P
bLn* THK
n)/THK
bLn, (n=1,2,3,4,5), wherein, P
bLnfor the baseline of each pressure range of this dielectric material removes pressure, THK
bLnfor the thickness of baseline in each interval of this dielectric material.
In a specific embodiment, zone1 ~ zone5 reference pressure P in CMP
bL1, P
bL2, P
bL3, P
bL4, P
bL5be respectively 1.72psi, 1.58psi, 1.63psi, 1.84psi, 2.3psi, thickness of baseline is 6000A, and the average thickness in each interval of wafer is THK
1: 6340A; THK
2: 6070A; THK
3: 5910A; THK
4: 5850A; THK
5: 6270A; Like this, the force value parameter of each pressure range of rubbing head carrying out planarization is obtained, P
1, P
2, P
3, P
4, P
5be respectively 1.82psi, 1.60psi, 1.61psi, 1.79psi, 2.4psi, the force value in each interval of rubbing head can be changed according to this force value, to ensure the uniformity of planarization.
After planarization, carry out wet etching, obtain isolating device 106, shown in figure 3.
Then, can according to the concrete subsequent technique having needed device, as the formation etc. of grid structure.
The above is only preferred embodiment of the present invention, not does any pro forma restriction to the present invention.
Although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention.Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (4)
1. a process for planarization, is characterized in that, comprises step:
Encapsulant layer;
Obtain the thickness data of material layer in sheet;
According to the division of rubbing head pressure range, obtain the average thickness THK of the material layer of each respective bins in sheet
n;
According to the average thickness THK of the material layer in each interval
n, the force value parameter P of each pressure range of adjustment rubbing head
n, carry out planarization.
2. process according to claim 1, is characterized in that, force value parameter P
n=(P
bLn* THK
n)/THK
bLn, wherein, P
bLnfor the baseline of each pressure range of this material layer removes pressure, THK
bLnfor the thickness of baseline in each interval of this material layer.
3. process according to claim 2, is characterized in that, the quantity of rubbing head pressure range is 5.
4. process according to claim 1, is characterized in that, the step of described encapsulant layer is specially:
After substrate forms fin, fill the material layer of isolated material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410217592.2A CN105097434B (en) | 2014-05-21 | 2014-05-21 | Planarization process method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410217592.2A CN105097434B (en) | 2014-05-21 | 2014-05-21 | Planarization process method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105097434A true CN105097434A (en) | 2015-11-25 |
| CN105097434B CN105097434B (en) | 2018-06-01 |
Family
ID=54577612
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410217592.2A Active CN105097434B (en) | 2014-05-21 | 2014-05-21 | Planarization process method |
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| Country | Link |
|---|---|
| CN (1) | CN105097434B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106384725A (en) * | 2016-10-11 | 2017-02-08 | 天津华海清科机电科技有限公司 | Silicon through hole wafer flattening method |
| CN107919296A (en) * | 2017-11-16 | 2018-04-17 | 德淮半导体有限公司 | The forming method and its processing unit (plant) of semiconductor structure |
| CN111975469A (en) * | 2020-08-28 | 2020-11-24 | 上海华力微电子有限公司 | Chemical mechanical polishing method and polishing system |
| CN114952600A (en) * | 2022-07-11 | 2022-08-30 | 赛莱克斯微系统科技（北京）有限公司 | Flattening method and device for high-frequency transmission microstructure and electronic equipment |
| CN115101471A (en) * | 2022-03-21 | 2022-09-23 | 康劲 | Process control method for multilayer copper interconnection CMP |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106384725A (en) * | 2016-10-11 | 2017-02-08 | 天津华海清科机电科技有限公司 | Silicon through hole wafer flattening method |
| CN107919296A (en) * | 2017-11-16 | 2018-04-17 | 德淮半导体有限公司 | The forming method and its processing unit (plant) of semiconductor structure |
| CN111975469A (en) * | 2020-08-28 | 2020-11-24 | 上海华力微电子有限公司 | Chemical mechanical polishing method and polishing system |
| CN115101471A (en) * | 2022-03-21 | 2022-09-23 | 康劲 | Process control method for multilayer copper interconnection CMP |
| CN114952600A (en) * | 2022-07-11 | 2022-08-30 | 赛莱克斯微系统科技（北京）有限公司 | Flattening method and device for high-frequency transmission microstructure and electronic equipment |
| CN114952600B (en) * | 2022-07-11 | 2023-09-19 | 赛莱克斯微系统科技（北京）有限公司 | Planarization method and device for high-frequency transmission microstructure and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105097434B (en) | 2018-06-01 |
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