CN104078349B - Method, semi-conductor device manufacturing method - Google Patents
Method, semi-conductor device manufacturing method Download PDFInfo
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- CN104078349B CN104078349B CN201310110206.5A CN201310110206A CN104078349B CN 104078349 B CN104078349 B CN 104078349B CN 201310110206 A CN201310110206 A CN 201310110206A CN 104078349 B CN104078349 B CN 104078349B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
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- 238000001020 plasma etching Methods 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000007789 gas Substances 0.000 claims description 56
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 16
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- 239000011261 inert gas Substances 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 229910052731 fluorine Inorganic materials 0.000 claims description 7
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 239000011737 fluorine Substances 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910052799 carbon Inorganic materials 0.000 claims description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 4
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- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 3
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 claims description 3
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
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- -1 oxygen alkane Chemical class 0.000 description 3
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
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- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 2
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- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
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- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910005872 GeSb Inorganic materials 0.000 description 1
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- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 description 1
- 229910052794 bromium Inorganic materials 0.000 description 1
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- 238000005229 chemical vapour deposition Methods 0.000 description 1
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- 229910003460 diamond Inorganic materials 0.000 description 1
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- 230000002708 enhancing effect Effects 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
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- 239000007788 liquid Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
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- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
- SOQBVABWOPYFQZ-UHFFFAOYSA-N oxygen(2-);titanium(4+) Chemical class [O-2].[O-2].[Ti+4] SOQBVABWOPYFQZ-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
Abstract
The invention discloses a kind of method, semi-conductor device manufacturing method, including：The multiple grooves formed on substrate between multiple fins and fin；Dielectric is filled in the trench and on fin, and dielectric has projection at the top of fin；Using the first etching gas, the first plasma etching is carried out to dielectric, reduces the height of projection；Using the second etching gas, the second plasma etching is carried out to dielectric, further reduces the height of projection.According to the method, semi-conductor device manufacturing method of the present invention, dielectric is sequentially etched using different etching gas, avoids and is sustained damage at the top of fin, improves the precision and reliability of small size device processing.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing field, more particularly, to a kind of 3 D stereo device FinFET
Middle fin（Fin）Film filler plasma return carve planarization.
Background technology
As semiconductor technology continues to develop, cmos circuit size constantly reduces, ever-increasing subthreshold current and grid
Medium Leakage Current becomes the principal element for hindering CMOS technology further to develop.Since 22nm nodes, people are gradual
The visual field is turned into non-planar mos FET（Vertical transistor, FinFET（FinFET）, double grids MOSFET etc.）, with gram
Take the limitation that plane body silicon ribbon comes.
FinFET has absolutely in terms of subthreshold current and gate leak current is suppressed compared with traditional bulk silicon MOSFETs
To advantage.FinFET double grid or semi-ring grid and thin body silicon can suppress short channel effect, so as to reduce sub-threshold current leakage.It is short
The suppression of ditch effect and the enhancing of grid-control ability so that FinFET can use the gate oxide thicker than tradition, so
The gate leak current of FinFET can also reduce.Therefore FinFET substitution conventional bulk silicon device will be inevitable.
However, the representative as new device new construction, FinFET techniques are also increasingly complex.After Fin is formed, in filling
After dielectrics silicon dioxide material, its planarization can face a severe challenge.Due to no stop-layer, it is difficult to control filled media
Uniformity and final loss.And final uniformity is most important to device performance.In view of CMP is to device architecture and pattern density
More rely on, and it is with high costs, therefore need one kind badly and return carving technology without CMP plasmas, it disclosure satisfy that to three-dimensional FinFET's
It is required that.
The content of the invention
In view of this, it is an object of the invention to provide fin in a kind of innovative 3 D stereo device FinFET
（Fin）Film filler plasma return carve planarization, without cmp planarization film filler, so as to improve
The reliability of device.
Realize the above-mentioned purpose of the present invention, be by providing a kind of method, semi-conductor device manufacturing method, including：The shape on substrate
Into multiple grooves between multiple fins and fin；Dielectric is filled in the trench and on fin, and dielectric is in fin
There is projection at the top of piece；Using the first etching gas, the first plasma etching is carried out to dielectric, reduces the height of projection
Degree；Using the second etching gas, the second plasma etching is carried out to dielectric, further reduces the height of projection.
Wherein, the plasma etching of repetitive cycling first and the second plasma etching.
Wherein, the first plasma etching and the second plasma etching one of them be anisotropic etching, another
For isotropic etching.
Wherein, the first etching gas and the second etching gas one of them be inert gas, another includes the fluorine-based gas of carbon
Body.
Wherein, inert gas He, Ar and combinations thereof.
Wherein, carbon fluorine base gas is CF4、CHF3、CH3F、CH2F2、C4F6、C4F8And combinations thereof.
Wherein, the first etching gas or the second etching gas for containing carbon fluorine base gas also include oxidizing gas.
Wherein, oxidizing gas O2。
Wherein, dielectric includes silica based materials or silicon nitride-based material.
Wherein, further comprise that three plasma body etches：Using the etching gas for including carbon fluorine base gas, plasma
Dry etching dielectric is to predetermined thickness, to expose the partial sidewall of fin.
Wherein, forming the method for dielectric includes LPCVD, PECVD, SACVD, HDPCVD, UHVCVD, rapid thermal oxidation
（RTO）, evaporation, sputtering, chemical oxidation, spin coating, spraying, silk-screen printing and combinations thereof.
According to the method, semi-conductor device manufacturing method of the present invention, dielectric is sequentially etched using different etching gas, is kept away
Exempt to sustain damage at the top of fin, improved the precision and reliability of small size device processing.
Brief description of the drawings
Describe technical scheme in detail referring to the drawings, wherein：
Fig. 1 to Fig. 6 is the diagrammatic cross-section according to each step of method, semi-conductor device manufacturing method of the present invention；And
Fig. 7 is the flow chart according to the method, semi-conductor device manufacturing method of the present invention.
Embodiment
Referring to the drawings and schematical embodiment is combined to describe the feature of technical solution of the present invention and its skill in detail
Art effect.It is pointed out that the structure that similar reference expression is similar, term use herein " first ", " the
Two ", " on ", " under ", " thickness ", " thin " etc. can be used for modifying various device architectures.These modifications are not dark unless stated otherwise
Show space, order or the hierarchical relationship of modified device architecture.
Reference picture 7 and Fig. 1, multiple fin 1F are formed on substrate 1.
There is provided substrate 1, its can be body Si, SOI, body Ge, GeOI, SiGe, GeSb or III--V races or
II--VI compound semiconductor substrates, such as GaAs, GaN, InP, InSb etc..In order to it is compatible with existing CMOS technology with
Manufactured applied to large-scale digital ic, substrate 1 is preferably body Si or SOI, most preferably monocrystalline body Si（Such as have
Have（100）Crystal face）.
Preferably, surface passes through the common process deposited hard mask material layer such as LPCVD, PECVD, HDPCVD on substrate 1
And photoetching/etching forms hard mask（It is not shown）.In an embodiment of the invention, hard mask material can be silicon nitride.And
In an alternative embodiment of the invention, hard mask material can be silica.In addition it is also possible to hard mask is not formed, but directly
Coating photoresist is simultaneously lithographically formed photoetching offset plate figure, using the photoetching offset plate figure as soft mask（It is not shown）.
The soft mask formed using hard mask or above-mentioned photoresist, etched substrate 1, forms fin 1F.Etching to be
Plasma etching（Etching gas are, for example, the inert gases such as Ar）, reactive ion etching（RIE, reacting gas is for example including fluorine
The halogen gas such as base gas, chlorine-based gas or bromine-based gas and oxidizing gas）, by control reaction speed and time come
Adjust etching depth.Can also be according to the chemico-physical properties of silicon from various suitable wet etching liquid, for example with tetramethyl
Base ammonium hydroxide（TMAH）To carry out wet etching, and because Si (111) crystal face etching speed is significantly less than (100) face, therefore
The fin sidewall generally yielded is（111）Face.The multiple fin 1F formed are usually that depth-width ratio is larger（It is greater than 5:1, even
10:1）Lines, therefore multiple fin structures being parallel to each other have been stood vertically from substrate 1, fin will be used to be formed
FinFET source-drain area and channel region, and the deep trench 1G futures obtained between fin by etched substrate 1 will be used to isolate
Different transistors.
Due to different crystal faces, speed is different under etching condition, therefore multiple fin 1F that the material etch of substrate 1 obtains
The side of structure is simultaneously non-fully vertical.Although can be as straight as possible by adjusting etching condition side wall, but fin
Angle [alpha] is still had between 1F and the bottom surface of substrate 1, such as in the range of 85 ± 0.5~1.5 degree.Therefore, in follow-up backfill and
Return during carving, fin 1F sidewall sections, so as to trigger fin 1F to bend or be broken, will be influenceed by lateral corrasion
The reliability of fine lines.
Reference picture 7 and Fig. 2, dielectric 2 is filled between the groove 1G between fin 1F.Such as by LPCVD,
PECVD, SACVD, HDPCVD, UHVCVD, sputtering, evaporation, rapid thermal oxidation（RTO）, chemical oxidation, spin coating, spraying, screen printing
The modes such as brush deposit, form dielectric 2.The top of dielectric 2 is preferably higher than, more than the top of fin 1F or hard mask
Portion, such as its thickness（From the surface of substrate 1, fin 1F basal surface to the air line distance between the peak of dielectric 2）For fin
1.5~10 times of piece 1F height.The material of dielectric 2 is different, and preferably with hard mask（When it is present）And/or substrate
1/ fin 1F has higher Etch selectivity.For example, in an embodiment of the invention, insulated when hard mask is silicon nitride
Medium 2 is silica, silicon oxynitride（The wherein content ratio preferably greater than 2 of oxygen and nitrogen:1）, the silica such as BSG, PSG, BPSG
Sill, further, it is also possible to be low-k materials, including but not limited to organic low-k materials（Such as having containing aryl or more yuan of rings
Machine polymer）, inorganic low-k material（Such as amorphous carbon nitrogen film, polycrystalline boron nitrogen film, fluorine silica glass, BSG, PSG, BPSG）、
Porous low k material（Such as the oxygen alkane of two silicon three（SSQ）Quito hole low-k materials, porous silica, porous SiOCH, mix C titanium dioxides
Silicon, mix the porous amorphous carbon of F, porous diamond, porous organic polymer）；And in another embodiment, when hard mask is oxygen
SiClx（Or above-mentioned silica based materials）When dielectric 2 be silicon nitride or doped silicon nitride（Such as mixed with C, O, F, P etc.）.
Preferably, using chemical vapor deposition（It is not limited to above-mentioned various CVD techniques）To form dielectric 2.As shown in Fig. 2 insulation
Medium 2 has substantially conformal jut 2F at the top of fin 1F, and the jut forms device dielectric isolation layer in future etching
When will influence the precision and shape of lines, it is serious to cause lines distortion so that taking exercise or crooked so that whole device
Part fails.If conventional CMP is used, due to there is no protective layer, stop-layer between dielectric 2 and fin 1F, therefore
CMP often part over etching, cross polishing fin 1F top so that device channel region surface defect is larger, so as to reduce device
Part performance.Therefore, the innovative important technology processing step of the present invention is described in detail referring below to Fig. 3 to Fig. 6.
Reference picture 7 and Fig. 3, using the first etching gas, the first plasma etching is carried out, etching dielectric 2 is with drop
Low its jut 2F height.In one embodiment of the invention, etching apparatus is, for example, micro semiconductor Primo DRIE in using
Cavity, using dijection display system, high frequency power is that 60MHz is mainly used to produce plasma, for adjusting plasma density；
Low frequency system is that 2MHz is used to strengthen ion energy and bombardment intensity, lifting etching directionality.It is uncoupling between the two, with
Exempt to influence each other.This allows to carry out different optimization according to the specific feature of etching, without changing institute's etching structure at it
Shape characteristic in terms of him.The etching apparatus of other manufacturers can be carried out similar regulation, be also belonged to this based on same principle
The protection domain of patent.First etching gas are the inert gas not reacted substantially with dielectric 2 and fin 1F, such as
He, Ar and combinations thereof, and preferably Ar.Using the plasma of inert gas come the vertical top for bombarding dielectric 2, namely
First plasma etching is anisotropic so that the jut 2F of dielectric 2 at the top of fin 1F is thinned, namely jut
The shoulder height in other regions of 2F Yu dielectric 2 will reduce, and the integral thickness of the flat portion of dielectric 2 also declines in addition.
For example, the jut 2F height reductions of dielectric 2 1/5~1/3, the thickness of flat portion reduces 1/8~1/4.Can be with
Energy and the time of Reasonable adjustment bombardment are needed according to technique so that the Reducing thickness of dielectric 2 meets needs.It is worth noting
, because the inert gas plasmas such as Ar also can be thinned it when bombarding the fin 1F of silicon material, it is therefore necessary to complete
Full etching changes etching gas before removing top boss 2F, to avoid at the top of fin 1F by improper etching.
Reference picture 7 and Fig. 4, change etching gas in identical processing chamber, to adjust etch rate.Using the second etching
Gas, the second plasma etching is carried out, continue to etch dielectric 2 further to reduce its jut 2F height.Second
Plasma etching is preferably isotropic, therefore the second etching gas can preferably be reacted with dielectric 2 and best base
This etching gas not reacted with the fin 1F of substrate 1/.Second etching gas preferably include carbon fluorine base gas, such as CF4、CHF3、
CH2F2、CH3F、C4F6、C4F8Deng and combinations thereof so that silica has to Si or polysilicon 20:More than 1 high selectivity（
Even if the i.e. now top boss 2F of dielectric 2 is removed by complete etching, also it is substantially unaffected at the top of fin 1F, or
Influence smaller）, so that progressively mellow and fullization, shoulder height further reduce dielectric top boss 2F, for example, 1/4~
1/3.Preferably, the second etching gas also include oxidizing gas O2, it is caused for complementary removal and etching
During caused polymer so that etching be unlikely to stop.
Hereafter, reference picture 7 and Fig. 5, Fig. 6, on the basis of the two steps etching shown in Fig. 3, Fig. 4, repeatedly circulate, in repetition
Step is stated, namely carries out the first plasma etching of the first etching gas and the second plasma of the second etching gas successively
Etching, until the projection 2F at the top of dielectric 2 height（It is dielectric 2 above shoulder height, namely fin 1F herein
The distance between peak top planes of dielectric 2 corresponding with groove 1G）Be reduced to required scope, such as 5~10nm with
It is interior.Above-mentioned circulation, the number repeated are, for example, 2~10 times, can also be more, next according to thinned thickness is etched in each circulation
Determine.Before degree needed for reaching in etching, there are gradually thinned projection 2F protections at the top of fin 1F all the time, therefore will not be by mistake
Degree etching causes device surface hydraulic performance decline, and this substep simultaneously of the invention, the process and can that gradually etches gradually are forced
Thickness needed near, is easy to technology controlling and process.For backward, even if finding local over etching through examining in some batch products,
Cycle-index can be reduced in next batch, is reduced by finely tuning for the damage at the top of fin 1F.
It is worth noting that, although the above embodiment of the present invention lists specific first, second etching gas and
First, the second plasma etching, but actually the present invention can also use any other sequence of steps.For example, first carry out
Isotropic carbon fluorine base gas etching（Above-mentioned second etching）, then carry out anisotropic inert gas etching（Above-mentioned
One etching）, isotropic carbon fluorine base gas etching is finally carried out to ensure that fin 1F is not etched；Can also first it carry out longer
The single of time or multiple anisotropic etching, finally carry out the carbon fluorine base gas isotropic etching of short period.Simply
For the consideration for being easy to finely tune technique, highly preferred embodiment of the present invention is fluorine-based for the first plasma etching and carbon of inert gas
The circulation successively of second plasma etching of gas.
Hereafter, can further handle to form FinFET.Carried out for example with the etching gas comprising carbon fluorine base gas
Three plasma body dry etching dielectric is to predetermined thickness, to expose the partial sidewall of fin；Hard mask is removed, in fin
Deposition forms the gate stack of high-k gate dielectric/metal gates on 1F orthogonal direction, and on fin 1F length directions
To source-drain area doping etc..
According to the method, semi-conductor device manufacturing method of the present invention, dielectric is sequentially etched using different etching gas, is kept away
Exempt to sustain damage at the top of fin, improved the precision and reliability of small size device processing.
Although illustrating the present invention with reference to one or more exemplary embodiments, those skilled in the art could be aware that need not
Depart from the scope of the invention and various suitable changes and equivalents are made to the method for formation device architecture.It is in addition, public by institute
The teaching opened, which can make many, can be adapted to the modification of particular condition or material without departing from the scope of the invention.Therefore, it is of the invention
Purpose do not lie in and be limited to as realizing the preferred forms of the present invention and disclosed specific embodiment, it is and disclosed
Device architecture and its manufacture method by all embodiments including falling within the scope of the present invention.
Claims (9)
1. a kind of method, semi-conductor device manufacturing method, including：
The multiple grooves formed on substrate between multiple fins and fin；
Dielectric is filled in the trench and on fin, and dielectric has projection at the top of fin；
Using the first etching gas, the first plasma etching is carried out to dielectric, reduces the height of projection；
Using the second etching gas, the second plasma etching is carried out to dielectric, further reduces the height of projection,
Wherein, the plasma etching of repetitive cycling first and the second plasma etching, last etching process are the fluorine-based gas of carbon
Bulk plasmon etches.
2. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, the first plasma etching and the second plasma etching
One of them is anisotropic etching, and another is isotropic etching.
3. method, semi-conductor device manufacturing method as claimed in claim 2, wherein, the first etching gas and the second etching gas one of them
For inert gas, another includes carbon fluorine base gas.
4. method, semi-conductor device manufacturing method as claimed in claim 3, wherein, inert gas He, Ar and combinations thereof.
5. method, semi-conductor device manufacturing method as claimed in claim 3, wherein, carbon fluorine base gas is CF4、CHF3、CH3F、CH2F2、C4F6、
C4F8And combinations thereof.
6. method, semi-conductor device manufacturing method as claimed in claim 3 comprising the first etching gas of carbon fluorine base gas or
Second etching gas also include oxidizing gas.
7. method, semi-conductor device manufacturing method as claimed in claim 6, wherein, oxidizing gas O2。
8. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, dielectric includes silica based materials or silicon nitride
Sill.
9. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, further comprise that three plasma body etches：Using bag
The etching gas of carbon containing fluorine base gas, plasma dry etch dielectric to predetermined thickness, to expose the part side of fin
Wall.
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| CN101459125A (en) * | 2007-12-13 | 2009-06-17 | 中芯国际集成电路制造(上海)有限公司 | Connection pore forming method |
| CN101789395A (en) * | 2009-01-26 | 2010-07-28 | 台湾积体电路制造股份有限公司 | Method of manufacturing semiconductor device |
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| CN102856181A (en) * | 2011-06-30 | 2013-01-02 | 中国科学院微电子研究所 | Method for forming multi-gate device |
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| CN101459125A (en) * | 2007-12-13 | 2009-06-17 | 中芯国际集成电路制造(上海)有限公司 | Connection pore forming method |
| CN101789395A (en) * | 2009-01-26 | 2010-07-28 | 台湾积体电路制造股份有限公司 | Method of manufacturing semiconductor device |
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