CN105097433A - Semiconductor device, preparation method thereof and electronic device - Google Patents
Semiconductor device, preparation method thereof and electronic device Download PDFInfo
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- CN105097433A CN105097433A CN201410203092.3A CN201410203092A CN105097433A CN 105097433 A CN105097433 A CN 105097433A CN 201410203092 A CN201410203092 A CN 201410203092A CN 105097433 A CN105097433 A CN 105097433A
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Abstract
The invention relates to a semiconductor device, a preparation method thereof and an electronic device. The method comprises the steps of providing a substrate and forming a projection of a first oblique plane on the substrate, the first oblique plane forming an included angle of 50-60 degrees with a horizontal plane; and depositing a thin film layer on the projection to form a second oblique plane on the first oblique plane, the second oblique plane forming an included angle of 30-40 degrees with the horizontal plane. The invention is advantageous in that firstly, the limitation of an oblique plane of 50-60 degrees in the prior art is overcome, and the oblique plane with a lower pitch is prepared; and secondly, the surface roughness of the oblique plane prepared by deposition is greatly improved as compared with that of an oblique plane prepared by etching, the subsequent process is facilitated, and the performance of the semiconductor device is further improved.
Description
Technical field
The present invention relates to semiconductor applications, particularly, the present invention relates to a kind of semiconductor device and preparation method thereof, electronic installation.
Background technology
At semiconductor applications, multifunctional equipment is more and more subject to liking of consumer, compared to the simple equipment of function, multifunctional equipment manufacturing process will be more complicated, such as need the chip of integrated multiple difference in functionality in circuit version, thus there is 3D integrated circuit (integratedcircuit, IC) technology, 3D integrated circuit (integratedcircuit, IC) a kind of system-level integrated morphology is defined as, multiple chip is stacking in the vertical direction, thus save space.
Usually patterning can be carried out on inclined-plane in 3D integrated circuit, to form various pattern, usually the inclined-plane of gradient comparatively slow (mildgradient) is selected in this patterning step, the acute angle that such as described inclined-plane and horizontal plane are formed is 30-40 °, but mostly there is the not accurate enough problem of angle in the method preparing inclined-plane at present, be difficult to obtain 30-40 ° of inclined-plane by the engraving method of routine, the acute angle that the inclined-plane such as prepared by conventional dry etching method and horizontal plane are formed is about 50 °, and the beveled profile prepared is coarse, be unfavorable for subsequent technique.
Therefore, need to be improved further the preparation method on inclined-plane, to eliminate above-mentioned multiple drawback.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
The invention provides a kind of preparation method of semiconductor device, comprising:
There is provided substrate, form the projection with the first inclined-plane on the substrate, the acute angle that described first inclined-plane and horizontal plane are formed is 50-60 °;
Deposit thin film layers in described projection, to form the second inclined-plane on described first inclined-plane, the acute angle that described second inclined-plane and horizontal plane are formed is 30-40 °.
Alternatively, described substrate comprises the Semiconductor substrate and oxide skin(coating) that are formed successively;
Oxide skin(coating) described in patterning, to form the described projection with described first inclined-plane in described oxide skin(coating), described projection is up-narrow and down-wide taper;
Described oxide skin(coating) deposits described thin layer, to form described second inclined-plane of grading on described first inclined-plane.
Alternatively, described in patterning, the method for oxide skin(coating) comprises:
Described oxide skin(coating) is formed the mask layer of patterning, in described mask layer, is formed with strip pattern;
With described mask layer for oxide skin(coating) described in mask dry etching, form described projection;
Remove described mask layer.
Alternatively, described substrate comprises the Semiconductor substrate and oxide skin(coating) that are formed successively;
Described oxide skin(coating) forms strip pattern;
With described oxide skin(coating) for Semiconductor substrate described in mask wet etching, to form the described projection with the first inclined-plane in described Semiconductor substrate, described projection is up-narrow and down-wide taper;
Remove described oxide skin(coating), to expose described Semiconductor substrate;
Deposit described thin layer on the semiconductor substrate, to form described second inclined-plane of grading on described first inclined-plane.
Alternatively, TAMH is selected to etch described Semiconductor substrate, to form described projection.
Alternatively, the method described oxide skin(coating) forming strip pattern comprises:
Described oxide skin(coating) is formed the mask layer of patterning, in described mask layer, is formed with strip pattern;
With described mask layer for oxide skin(coating) described in mask etch, so that described strip pattern is transferred in described oxide skin(coating);
Remove described mask layer.
Alternatively, described method is also included in the step described second inclined-plane being formed patterning function material layer further.
Alternatively, the method forming described patterning function material layer comprises:
Described thin layer deposits the second mask layer, to cover described second inclined-plane;
Second mask layer described in patterning, to form opening, exposes described second inclined-plane;
Deposition function material layer, to fill described opening;
Remove described second mask layer.
Alternatively, described function material layer comprises the NiFe layer and Ti layer that deposit successively.
Present invention also offers the semiconductor device that a kind of above-mentioned method prepares.
Present invention also offers a kind of electronic installation, comprise above-mentioned semiconductor device.
The present invention is in order to obtain the more slow inclined-plane of the gradient, eliminate the restriction that can only form 50-60 ° of inclined-plane in prior art, provide a kind of preparation method of new semiconductor device, first 50-60 ° of inclined-plane is prepared by a conventional method to obtain in the process, then deposit thin film layers on described inclined-plane, to relax the gradient on described inclined-plane, thus obtain the more slow inclined-plane of the gradient, the such as inclined-plane of the 30-40 ° of gradient.
The invention has the advantages that:
(1) the present invention breaches the restriction on 50-60 ° of inclined-plane in prior art, prepares the inclined-plane that the gradient is more slow.
(2) the method for the invention prepares inclined-plane by deposition process, being greatly improved, being conducive to subsequent technique, improving the performance of semiconductor device further relative to etching its rough surface performance of inclined-plane obtained.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining device of the present invention and principle.In the accompanying drawings,
Fig. 1 is that in prior art, inclined-plane and horizontal plane form angle schematic diagram;
Fig. 2 a-2e is the cutaway view preparing inclined-plane process in the embodiment of the invention;
Fig. 3 a-3f is the cutaway view preparing inclined-plane process in the embodiment of the invention;
Fig. 4 is the process chart preparing inclined-plane in the embodiment of the invention;
Fig. 5 is the process chart preparing inclined-plane in the embodiment of the invention.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
Should be understood that, the present invention can implement in different forms, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiments will expose thoroughly with complete, and scope of the present invention is fully passed to those skilled in the art.In the accompanying drawings, in order to clear, the size in Ceng He district and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.
Be understood that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or layer time, its can directly on other element or layer, with it adjacent, connect or be coupled to other element or layer, or the element that can exist between two parties or layer.On the contrary, when element be called as " directly exist ... on ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or layer time, then there is not element between two parties or layer.Although it should be understood that and term first, second, third, etc. can be used to describe various element, parts, district, floor and/or part, these elements, parts, district, floor and/or part should not limited by these terms.These terms be only used for differentiation element, parts, district, floor or part and another element, parts, district, floor or part.Therefore, do not departing under the present invention's instruction, the first element discussed below, parts, district, floor or part can be expressed as the second element, parts, district, floor or part.
Spatial relationship term such as " ... under ", " ... below ", " below ", " ... under ", " ... on ", " above " etc., here can be used thus the relation of the element of shown in description figure or feature and other element or feature for convenience of description.It should be understood that except the orientation shown in figure, spatial relationship term intention also comprises the different orientation of the device in using and operating.Such as, if the device upset in accompanying drawing, then, be described as " below other element " or " under it " or " under it " element or feature will be oriented to other element or feature " on ".Therefore, exemplary term " ... below " and " ... under " upper and lower two orientations can be comprised.Device can additionally orientation (90-degree rotation or other orientation) and as used herein spatial description language correspondingly explained.
The object of term is only to describe specific embodiment and not as restriction of the present invention as used herein.When this uses, " one ", " one " and " described/to be somebody's turn to do " of singulative is also intended to comprise plural form, unless context is known point out other mode.It is also to be understood that term " composition " and/or " comprising ", when using in this specification, determine the existence of described feature, integer, step, operation, element and/or parts, but do not get rid of one or more other feature, integer, step, operation, element, the existence of parts and/or group or interpolation.When this uses, term "and/or" comprises any of relevant Listed Items and all combinations.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, to explain technical scheme of the present invention.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
In current semiconductor device, the preparation method on inclined-plane comprises two kinds: the first is for providing substrate 102, then the photoresist 101 of patterning is formed on the substrate, the tapered profile of described photoresist layer, then by described design transfer to described substrate 102, in second, method is for providing substrate, then dry etching is selected, and regulate each parameter in dry etch process thus obtain target inclined-plane, but all there is drawback in above-mentioned two kinds of methods, the acute angle that such as target inclined-plane and horizontal plane are formed is 30-40 °, but the inclined-plane that above-mentioned two kinds of methods prepare and the acute angle that horizontal plane is formed are about 50 °, as shown in Figure 1, be difficult to reach angle on target, this process difficult controls, and the beveled profile prepared is coarse, be unfavorable for subsequent technique.
The present invention is in order to obtain the more slow inclined-plane of the gradient, eliminate the restriction that can only form 50-60 ° of inclined-plane in prior art, provide a kind of new inclined-plane preparation method, described method comprises: provide substrate, form the projection with the first inclined-plane on the substrate, the acute angle that described first inclined-plane and horizontal plane are formed is 50-60 °; Deposit thin film layers in described projection, described first inclined-plane to be formed the second inclined-plane of grading, the acute angle that described second inclined-plane and horizontal plane are formed is 30-40 °.
First be prepared by a conventional method to obtain 50-60 ° of inclined-plane in the process, then deposit thin film layers on described inclined-plane, to relax the gradient on described inclined-plane, thus obtain the more slow inclined-plane of the gradient (inclined-plane of the 30-40 ° of gradient).
Below in conjunction with accompanying drawing, the method for the invention is further described.
Embodiment 1
Below in conjunction with accompanying drawing 2a-2e, described method is further described.
First, perform step 201, Semiconductor substrate 201 is provided, described Semiconductor substrate 201 is formed with oxide skin(coating) 202.
Particularly, as shown in Figure 2 a, described Semiconductor substrate 201 can be at least one in following mentioned material: stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.
Described Semiconductor substrate 201 selects silicon in this embodiment.
Described oxide skin(coating) 202 is silica, but is not only confined to silica, and this oxide mask layer also can be ZnO, CdO, TiO
2, Al
2o
3, SnO, Cu
2o, NiO, CoO, FeO and Cr
2o
3in one.
Perform step 202, described oxide skin(coating) 202 is formed the mask layer 203 of patterning, in described mask layer 203, is formed with strip pattern.
Particularly, the mask layer that described mask layer 203 can select this area conventional, alternatively, described mask layer 203 selects photoresist, and to reduce process costs, convenient removal simultaneously, with process simplification.
Wherein, be formed with strip pattern in described mask layer 203, the critical size of described strip pattern is determined by the projection in subsequent technique, and be not limited to a certain size, its effect is as mask in subsequent process, is formed protruding by etching.
Perform step 203, with described mask layer 203 for oxide skin(coating) 202 described in mask dry etching, form the projection with the first inclined-plane 20, the acute angle that described first inclined-plane 20 and horizontal plane are formed is 50-60 °.
Particularly, in this step, with described mask layer 203 for oxide skin(coating) 202 described in mask dry etching, to form described projection in described oxide skin(coating) 202, described projection is up-narrow and down-wide pyramidal structure, its cross section is trapezoidal, and as shown in Figure 2 b, the angle between described first inclined-plane 20 and horizontal plane is about 50 °.
Further, the height of described projection is 3.8-4.2um, but is not limited to this number range, can arrange as required.
Alternatively, selecting oxide skin(coating) 202 described in dry etching, and constantly regulate etching condition in this step, is about 50 ° with the angle controlled between described first inclined-plane 20 and horizontal plane.
Exemplarily, described dry etch step can select CF
4, CHF
3add N in addition
2, CO
2, O
2in one as etching atmosphere, wherein gas flow is CF
410-200sccm, CHF
310-200sccm, N
2or CO
2or O
210-400sccm, described etching pressure is 30-150mTorr, and etching period is 5-120s, is chosen as 5-60s.
Then remove described mask layer 203, such as, ashing method can be selected to remove described mask layer 203, but be not limited to the method.
Perform step 204, described oxide skin(coating) 202 deposits described thin layer 204, to form described second inclined-plane 21 of grading on described first inclined-plane 20, the acute angle that described second inclined-plane 21 and horizontal plane are formed is 30-40 °.
Particularly, in this step after preparing described projection, deposit thin film layers 204 on described oxide skin(coating) 202, to cover described first inclined-plane 20, on described first inclined-plane 20, form the second inclined-plane 21 that the gradient more relaxes simultaneously, the acute angle that described second inclined-plane 21 and horizontal plane are formed is 30-40 °, as shown in Figure 2 c.
In this step, the kind of described thin layer 204 is not limited to a certain, can select oxide, such as SiO
2deng, but be not limited to described material.
One in low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and selective epitaxy growth (SEG) that the deposition process of described thin layer 204 can select chemical vapour deposition (CVD) (CVD) method, physical vapour deposition (PVD) (PVD) method or ald (ALD) method etc. to be formed.
In this step by the described thin layer of deposition, to relax the gradient of described projection, the second inclined-plane 21 more relaxed, thus give security for forming pattern in subsequent technique on described second inclined-plane 21, further, described second inclined-plane 21, by deposition process, being greatly improved relative to etching its rough surface performance of inclined-plane obtained, improving the performance of semiconductor device further.
Perform step 205, described thin layer 204 deposits the second mask layer 205, and to cover described second inclined-plane 21, the second mask layer 205 described in patterning, to form opening, exposes described second inclined-plane 21.
Particularly, the mask material that described second mask layer 205 can select this area conventional, do not repeat them here, alternatively, the second mask layer 205 selects photoresist layer.
After described thin layer 204 deposits photoresist layer, photoetching development, forms opening in described photoresist layer, exposes described second inclined-plane 21.
Wherein, the number of described opening and size are not limited to a certain number range.
Perform step 206, deposition function material layer, to fill described opening.
Particularly, as shown in Figure 2 d, deposition function material layer, to cover described second mask layer 205, fills described opening, to form function material layer above described second inclined-plane 21 simultaneously.
Further, described function material layer comprises the NiFe layer 206 and Ti layer 207 that deposit successively, the one in low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and selective epitaxy growth (SEG) that chemical vapour deposition (CVD) (CVD) method, physical vapour deposition (PVD) (PVD) method or ald (ALD) method etc. can be selected to be formed.Described function material layer is not limited to above-mentioned example.
Wherein, in described function material layer, NiFe layer 306 is magnetic material film, and for the formation of magnetic material element, magnetic material element comprises the element in three dimensions (X, Y and Z tri-directions), for realizing three-dimensional magnetoresistive transducer.
Further, described three-dimensional magnetoresistive transducer can also be used for preparing three-dimensional electronic compass further, and described three-dimensional electronic compass is made up of three-dimensional magnetoresistive transducer, double-shaft tilt angle sensor and MCU, does not repeat them here.
Perform step 207, remove described second mask layer 205.
Particularly, remove the function material layer above described second mask layer 205 and described second mask layer 205, only retain the described function material layer be positioned on the second inclined-plane 21, as shown in Figure 2 e.
Alternatively, ashing method such as can be selected to remove described mask layer 203, but be not limited to the method.
So far, the introduction inclined-plane of the embodiment of the present invention and inclined-plane being formed the correlation step of pattern is completed.After the above step, other correlation step can also be comprised, repeat no more herein.Further, in addition to the foregoing steps, the preparation method of the present embodiment can also comprise other steps among each step above-mentioned or between different steps, and these steps all can be realized by various technique of the prior art, repeat no more herein.
The present invention is in order to obtain the more slow inclined-plane of the gradient, eliminate the restriction that can only form 50 ° of inclined-planes in prior art, provide a kind of new inclined-plane preparation method, first 50 ° of inclined-planes are prepared by a conventional method to obtain in the process, then deposit thin film layers on described inclined-plane, to relax the gradient on described inclined-plane, thus obtain the more slow inclined-plane of the gradient, the such as inclined-plane of the 30-40 ° of gradient.
The invention has the advantages that:
(1) the present invention breaches dry etching in prior art and can only obtain the restriction on 50 ° of inclined-planes, prepares the inclined-plane that the gradient is more slow.
(2) the method for the invention prepares inclined-plane by deposition process, being greatly improved, being conducive to subsequent technique, improving the performance of semiconductor device further relative to etching its rough surface performance of inclined-plane obtained.
Fig. 4 is the process chart preparing inclined-plane in this embodiment of the present invention, comprising:
Step 201, provides Semiconductor substrate, and described Semiconductor substrate is formed with oxide skin(coating);
Step 202, described oxide skin(coating) is formed the mask layer of patterning, is formed with strip pattern in described mask layer;
Step 203, with described mask layer for oxide skin(coating) described in mask dry etching, form the projection with the first inclined-plane, the acute angle that described first inclined-plane and horizontal plane are formed is 50-60 °;
Step 204, described oxide skin(coating) deposits described thin layer, and to form described second inclined-plane of grading on described first inclined-plane, the acute angle that described second inclined-plane and horizontal plane are formed is 30-40 °;
Step 205, described thin layer deposits the second mask layer, and to cover described second inclined-plane, the second mask layer described in patterning, to form opening, exposes described second inclined-plane;
Step 206, deposition function material layer, to fill described opening;
Step 207, removes described second mask layer.
Embodiment 2
Below in conjunction with accompanying drawing 3a-3f, described method is further described.
First, perform step 301, Semiconductor substrate 301 is provided, described Semiconductor substrate 301 is formed with oxide skin(coating) 302.
Particularly, as shown in Figure 3 a, described Semiconductor substrate 301 can be at least one in following mentioned material: stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.
Described Semiconductor substrate 301 selects silicon in this embodiment.
Described oxide skin(coating) 302 is silica, but is not only confined to silica, and this oxide mask layer also can be ZnO, CdO, TiO
2, Al
2o
3, SnO, Cu
2o, NiO, CoO, FeO and Cr
2o
3in one.
Perform step 302, described oxide skin(coating) 302 is formed the mask layer 303 of patterning, in described mask layer 303, is formed with strip pattern.
Particularly, the mask layer that described mask layer 303 can select this area conventional, alternatively, described mask layer 303 selects photoresist, and to reduce process costs, convenient removal simultaneously, with process simplification.
Wherein, be formed with strip pattern in described mask layer 303, the critical size of described strip pattern is determined by the projection in subsequent technique, and be not limited to a certain size, its effect is as mask in subsequent process, is formed protruding by etching.
Perform step 303, with described mask layer 303 for oxide skin(coating) described in mask etch 302, to be transferred in described oxide skin(coating) 302 by described strip pattern.
Particularly, in this step, with described mask layer 303 for mask, oxide skin(coating) 302 described in dry etching is selected, to form described strip pattern in described oxide skin(coating) 302, as shown in Figure 3 b.
Further, described oxide skin(coating) 302 in this embodiment act as hard mask layer, form described projection in described Semiconductor substrate 301, therefore the thickness of described oxide skin(coating) 302 can be thinner, is not limited to a certain number range.
Then remove described mask layer 303, such as, ashing method can be selected to remove described mask layer 303, but be not limited to the method.
Perform step 304, with described oxide skin(coating) 302 for Semiconductor substrate described in mask etch 301, to form the described projection with the first inclined-plane 30 in described Semiconductor substrate 301, described projection is up-narrow and down-wide taper.
Particularly, in this step, with described oxide skin(coating) 302 for Semiconductor substrate described in mask etch 301, to form described projection in described Semiconductor substrate 301, described projection is up-narrow and down-wide pyramidal structure, and its cross section is trapezoidal, as shown in Figure 3 c.
Angle between wherein said first inclined-plane 30 and horizontal plane is 54.74 °, determines that the angle of 100 crystal faces and 111 crystal faces is 54.74 ° by the crystal face character of Si, therefore can obtain by etching the projection that angle is 54.74 ° in this step; Due to the various state-variables in etching process, cause the error of the angle on inclined-plane in described first groove at+2 ° and about-2 °, the angle on the first therefore obtained inclined-plane 30 is 52.74 °-56.74 °.
Alternatively, selecting Semiconductor substrate 301 described in wet etching in this step, such as, select Semiconductor substrate 301 described in TMAH (Tetramethylammonium hydroxide) solution etches, is 54.74 ° to make the angle in silicon substrate between crystal face 111 and crystal face 100.
Further, in described TMAH solution, the mass fraction of TMAH is 0.1%-10%, and described wet etching temperature is 25-90 DEG C, and described wet etch time is 10s-1000s.
Then remove described oxide 302, select the engraving method with larger etching selectivity to remove described oxide 302 in this step, to avoid causing damage to described Semiconductor substrate and described projection.
Further, the height of described projection is 3.8-4.2um, but is not limited to this number range, can arrange as required.
Perform step 305, described Semiconductor substrate 301 deposits described thin layer 304, to form described second inclined-plane 31 of grading on described first inclined-plane 30, the acute angle that described second inclined-plane 31 and horizontal plane are formed is 30-40 °.
Particularly, in this step after preparing described projection, deposit thin film layers 304 in described Semiconductor substrate 301, to cover described first inclined-plane 30, on described first inclined-plane 30, form the second inclined-plane 31 that the gradient more relaxes simultaneously, the acute angle that described second inclined-plane 31 and horizontal plane are formed is 30-40 °, as shown in Figure 3 d.
In this step, the kind of described thin layer 304 is not limited to a certain, can select oxide, such as SiO
2deng, but be not limited to described material.
One in low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and selective epitaxy growth (SEG) that the deposition process of described thin layer 304 can select chemical vapour deposition (CVD) (CVD) method, physical vapour deposition (PVD) (PVD) method or ald (ALD) method etc. to be formed.
In this step by the described thin layer of deposition, to relax the gradient of described projection, the second inclined-plane 31 more relaxed, thus give security for forming pattern in subsequent technique on described second inclined-plane 31, further, described second inclined-plane 31, by deposition process, being greatly improved relative to etching its rough surface performance of inclined-plane obtained, improving the performance of semiconductor device further.
Perform step 306, described thin layer 304 deposits the second mask layer 305, and to cover described second inclined-plane 31, the second mask layer 305 described in patterning, to form opening, exposes described second inclined-plane 31.
Particularly, the mask material that described second mask layer 305 can select this area conventional, do not repeat them here, the second mask layer 305 selects photoresist layer alternatively.
After described thin layer 304 deposits photoresist layer, photoetching development, forms opening in described photoresist layer, exposes described second inclined-plane 31.
Wherein, the number of described opening and size are not limited to a certain number range.
Perform step 307, deposition function material layer, to fill described opening.
Particularly, as shown in Figure 3 e, deposition function material layer, to cover described second mask layer 305, fills described opening, to form function material layer above described second inclined-plane 31 simultaneously.
Further, described function material layer comprises the NiFe layer 306 and Ti layer 307 that deposit successively, the one in low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and selective epitaxy growth (SEG) that chemical vapour deposition (CVD) (CVD) method, physical vapour deposition (PVD) (PVD) method or ald (ALD) method etc. can be selected to be formed.Described function material layer is not limited to above-mentioned example.
Wherein, in described function material layer, NiFe layer 306 is magnetic material film, and for the formation of magnetic material element, magnetic material element comprises the element in three dimensions (X, Y and Z tri-directions), for realizing three-dimensional magnetoresistive transducer.
Further, described three-dimensional magnetoresistive transducer can also be used for preparing three-dimensional electronic compass further, and described three-dimensional electronic compass is made up of three-dimensional magnetoresistive transducer, double-shaft tilt angle sensor and MCU, does not repeat them here.
Perform step 308, remove described second mask layer 305.
Particularly, remove the function material layer above described second mask layer 305 and described second mask layer 305, only retain the described function material layer be positioned on the second inclined-plane 31, as illustrated in figure 3f.
Alternatively, ashing method such as can be selected to remove described mask layer 303, but be not limited to the method.
So far, the introduction inclined-plane of the embodiment of the present invention and inclined-plane being formed the correlation step of pattern is completed.After the above step, other correlation step can also be comprised, repeat no more herein.Further, in addition to the foregoing steps, the preparation method of the present embodiment can also comprise other steps among each step above-mentioned or between different steps, and these steps all can be realized by various technique of the prior art, repeat no more herein.
The present invention is in order to obtain the more slow inclined-plane of the gradient, eliminate in prior art and select the restriction that can only form 54.74 ° of inclined-planes during TMAH etching silicon, provide a kind of new inclined-plane preparation method, first 54.74 inclined-planes are prepared by a conventional method to obtain in the process, then deposit thin film layers on described inclined-plane, to relax the gradient on described inclined-plane, thus obtain the more slow inclined-plane of the gradient, the such as inclined-plane of the 30-40 ° of gradient.
The invention has the advantages that:
(1) the present invention breaches in prior art the restriction that can only obtain 54.74 inclined-planes when selecting TMAH etching silicon, prepares the inclined-plane that the gradient is more slow.
(2) the method for the invention prepares inclined-plane by deposition process, being greatly improved, being conducive to subsequent technique, improving the performance of semiconductor device further relative to etching its rough surface performance of inclined-plane obtained.
Fig. 5 is the process chart preparing inclined-plane in this embodiment of the present invention, comprising:
Step 301, provides Semiconductor substrate, and described Semiconductor substrate is formed with oxide skin(coating);
Step 302, described oxide skin(coating) is formed the mask layer of patterning, is formed with strip pattern in described mask layer;
Step 303, with described mask layer for oxide skin(coating) described in mask etch, to be transferred in described oxide skin(coating) by described strip pattern;
Step 304, with described oxide skin(coating) for Semiconductor substrate described in mask etch, to form the described projection with the first inclined-plane in described Semiconductor substrate, described projection is up-narrow and down-wide taper;
Step 305, deposits described thin layer on the semiconductor substrate, and to form described second inclined-plane of grading on described first inclined-plane, the acute angle that described second inclined-plane and horizontal plane are formed is 30-40 °;
Step 306, described thin layer deposits the second mask layer, and to cover described second inclined-plane, the second mask layer described in patterning, to form opening, exposes described second inclined-plane;
Step 307, deposition function material layer, to fill described opening;
Step 308, removes described second mask layer.
Embodiment 3
Present invention also offers a kind of semiconductor device, described semiconductor device selects the method described in embodiment 1 or 2 to prepare.Described in the semiconductor device prepared by the method for the invention, the gradient on the second inclined-plane is less, be conducive to carrying out patterning, and the roughness on the second inclined-plane formed by described method is little, surface property improves, and improves the yield of described semiconductor device.
Embodiment 4
Present invention also offers a kind of electronic installation, comprise the semiconductor device described in embodiment 3.Wherein, semiconductor device is the semiconductor device described in embodiment 3, or the semiconductor device that the preparation method according to embodiment 1 or 2 obtains.
The electronic installation of the present embodiment, can be mobile phone, panel computer, notebook computer, net book, game machine, television set, VCD, DVD, navigator, camera, video camera, recording pen, any electronic product such as MP3, MP4, PSP or equipment, also can be any intermediate products comprising described semiconductor device.The electronic installation of the embodiment of the present invention, owing to employing above-mentioned semiconductor device, thus has better performance.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (11)
1. a preparation method for semiconductor device, comprising:
There is provided substrate, form the projection with the first inclined-plane on the substrate, the acute angle that described first inclined-plane and horizontal plane are formed is 50-60 °;
Deposit thin film layers in described projection, to form the second inclined-plane on described first inclined-plane, the acute angle that described second inclined-plane and horizontal plane are formed is 30-40 °.
2. method according to claim 1, is characterized in that, described substrate comprises the Semiconductor substrate and oxide skin(coating) that are formed successively;
Oxide skin(coating) described in patterning, to form the described projection with described first inclined-plane in described oxide skin(coating), described projection is up-narrow and down-wide taper;
Described oxide skin(coating) deposits described thin layer, to form described second inclined-plane of grading on described first inclined-plane.
3. method according to claim 2, is characterized in that, described in patterning, the method for oxide skin(coating) comprises:
Described oxide skin(coating) is formed the mask layer of patterning, in described mask layer, is formed with strip pattern;
With described mask layer for oxide skin(coating) described in mask dry etching, form described projection;
Remove described mask layer.
4. method according to claim 1, is characterized in that, described substrate comprises the Semiconductor substrate and oxide skin(coating) that are formed successively;
Described oxide skin(coating) forms strip pattern;
With described oxide skin(coating) for Semiconductor substrate described in mask wet etching, to form the described projection with the first inclined-plane in described Semiconductor substrate, described projection is up-narrow and down-wide taper;
Remove described oxide skin(coating), to expose described Semiconductor substrate;
Deposit described thin layer on the semiconductor substrate, to form described second inclined-plane of grading on described first inclined-plane.
5. method according to claim 4, is characterized in that, selects TAMH to etch described Semiconductor substrate, to form described projection.
6. method according to claim 4, is characterized in that, the method that described oxide skin(coating) is formed strip pattern comprises:
Described oxide skin(coating) is formed the mask layer of patterning, in described mask layer, is formed with strip pattern;
With described mask layer for oxide skin(coating) described in mask etch, so that described strip pattern is transferred in described oxide skin(coating);
Remove described mask layer.
7. method according to claim 1, is characterized in that, described method is also included in the step described second inclined-plane being formed patterning function material layer further.
8. method according to claim 7, is characterized in that, the method forming described patterning function material layer comprises:
Described thin layer deposits the second mask layer, to cover described second inclined-plane;
Second mask layer described in patterning, to form opening, exposes described second inclined-plane;
Deposition function material layer, to fill described opening;
Remove described second mask layer.
9. method according to claim 7, is characterized in that, described function material layer comprises the NiFe layer and Ti layer that deposit successively.
10. the semiconductor device prepared based on the method one of claim 1 to 9 Suo Shu.
11. 1 kinds of electronic installations, comprise semiconductor device according to claim 10.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4090006A (en) * | 1976-04-29 | 1978-05-16 | International Business Machines Corporation | Structure for making coplanar layers of thin films |
| EP0624660A1 (en) * | 1993-05-14 | 1994-11-17 | International Business Machines Corporation | Plasma Enhanced Chemical Vapour Deposition (PECVD) Process for forming Borophosphosilicate Glass (BPSG) with low flow temperature |
| CN1534738A (en) * | 2003-02-10 | 2004-10-06 | ������������ʽ���� | Wet-anisotropic etching of silicon |
| CN103632953A (en) * | 2012-08-20 | 2014-03-12 | 上海华虹宏力半导体制造有限公司 | A manufacturing method for a V-type groove structure based on a silicon oxide substrate |
-
2014
- 2014-05-14 CN CN201410203092.3A patent/CN105097433B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4090006A (en) * | 1976-04-29 | 1978-05-16 | International Business Machines Corporation | Structure for making coplanar layers of thin films |
| EP0624660A1 (en) * | 1993-05-14 | 1994-11-17 | International Business Machines Corporation | Plasma Enhanced Chemical Vapour Deposition (PECVD) Process for forming Borophosphosilicate Glass (BPSG) with low flow temperature |
| CN1534738A (en) * | 2003-02-10 | 2004-10-06 | ������������ʽ���� | Wet-anisotropic etching of silicon |
| CN103632953A (en) * | 2012-08-20 | 2014-03-12 | 上海华虹宏力半导体制造有限公司 | A manufacturing method for a V-type groove structure based on a silicon oxide substrate |
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