CN105094827B - A kind of method that processor starts - Google Patents
A kind of method that processor starts Download PDFInfo
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Abstract
The present invention relates to technical field of integrated circuits, more particularly to a kind of method that processor starts, in this method directly data are read from being cached outside nonvolatile memory and/or on piece caching and/or piece using the processor in server, it is not required to carry data from chip external memory to memory, it is transported in caching by memory again, to allow the processor in server to start immediately.When server is in low-power consumption mode, the speed of the fan being stacked in processor chips in server can be lowered or close, reduce the power consumption of server, simultaneously when the temperature of nonvolatile memory is more than the warning temperature standard being arranged in temperature sensor, the nonvolatile memory will be closed the normal work for ensureing the server and entire data center, prevent when fan work is abnormal, the temperature of nonvolatile memory is excessively high and the case where lead to server and entire data center's delay machine.
Description
Technical field
The present invention relates to a kind of methods that technical field of integrated circuits more particularly to processor start.
Background technology
With the development of integrated circuit technique, current chip has been carried out on increasingly advanced process node, i.e. core
The performance of piece is higher and higher, while the working frequency of chip is also relatively high, therefore the power consumption of chip is also bigger, but is not
All application programs are required for chip operation in a maximum performance mode, while also not all time is required for most chip
High-performance.Therefore in order to reduce the power consumption of chip, dynamic voltage frequency is adjusted
(DynamicVoltageandFrequencyScaling, abbreviation DVFS) technology is just come into being.DVFS technologies are according to chip
The application program of operation needs the difference of computing capability, the dynamic operating voltage and running frequency for adjusting chip, to drop
The power consumption method of low chip.The processing unit structure of server is as shown in Fig. 1 at present, and the processor chips 1 of server are by N number of
Processor forms, respectively processor 111, processor 112 ... ... processor 11N, wherein N ＞ 0.The processor chips have N number of
Local on piece caching, respectively local on piece caching 121, local on piece caches 12N to local on piece caching 122 ... ..., this is N number of
Local cache corresponds respectively to processor 111, processor 112 ... ... processor 11N.131 be on piece shared buffer memory in figure, N number of
Processor carries out the interaction of data by piece shared buffer memory 131, and N number of local on piece caching and on piece shared buffer memory 131 are
It is realized by Static RAM (StaticRandomAccessMemory, abbreviation SRAM), 141 be graphics processor in figure,
Dedicated for work such as image procossings.151 cache for afterbody in figure, it is an independent chip, afterbody caching
Usually by embedded dynamic RAM (EmbeddedDynamicRandomAccessMemory, abbreviation eDRAM)
Realize, independent afterbody cache chip and processor chips by multi-chip package technology (Multi-ChipPackage,
Abbreviation MCP) it is packaged together to form the processing unit structure of server.Illustrating server can profit in following three kinds of situations
Voltage and frequency are adjusted with DVFS Technique dynamics, to achieve the purpose that reduce power consumption：
1, the processor in server is not when processing needs high performance task, the operating voltage and frequency of these processors
Rate will be lowered, to reduce the power consumption of processor；
2, when some processors need not handle task, then these processors being in idle condition can be closed,
The operating voltage of corresponding on piece caching or/and afterbody caching should be reduced to the guarantor of on piece caching or/and afterbody caching
Hold the holding voltage i.e. guarantee on piece caching or/and afterbody caching of voltage, so-called on piece caching or/and afterbody caching
In data do not lose the voltage of required minimum；
3, some processors need not handle task and corresponding on piece caching or/and afterbody caching are also not required to
Data are kept, therefore idle processor and corresponding on piece caching or/and afterbody caching can be closed, thus into
One step saves power consumption.
We are waken up the time wanted to processing required by task from lower power consumption, processor respectively and soft error occur below
The aspect of probability three to can as follows be analyzed using three kinds of situations of DVFS technologies above：
A, in terms of lower power consumption；Because the processor and corresponding on piece in situation 1 in server cache or/and last
Grade caching still working, only reduce processor and corresponding on piece caching or/and afterbody caching operating voltage and
Frequency, lower power consumption amount is P1 to our notes in this case herein；Idle processor is closed in situation 2, is delayed in respective flap
It deposits or/and the operating voltage of afterbody caching is reduced to holding voltage, we remember the reduction amount of power consumption in this case herein
For P2；Processor not only idle is closed in situation 3, and corresponding on piece caching or/and afterbody caching are also turned off,
Here we remember that the reduction amount of power consumption in this case is P3, are from analyzing us above and being readily seen the relationship of lower power consumption amount
P3>P2>P1。
B, processor is waken up the time that processing required by task is wanted；Processor is operating voltage and frequency in situation 1
It is reduced accordingly, but processor is still working, if so processor will be handled when needing high performance task, it can be with
Quickly enter high performance mode, we remember that processor from the pattern switching to processing time for wanting of required by task is t1 herein
(t1 very littles)；Idle processor is closed in situation 2, but still stores on piece caching or/and afterbody caching
Data, therefore only need to wake up processor, processor can execute corresponding task, we remember that processor is waken up herein
The time wanted to processing required by task is t2；Idle processor is closed in situation 3, corresponding on piece caching or/and last
Level cache is also turned off, therefore not only wakes up processor, while corresponding on piece being cached or/and afterbody delays
Wake-up is deposited, and on piece caching is usually to realize (SRAM) by Static RAM, afterbody caching is usually by embedded
Dynamic RAM (eDRAM) is realized, is stored in Static RAM and embedded DRAM after a power failure
In data can lose, so at this time on piece caching or/and afterbody caching in there is no data, need the large capacity outside piece to deposit
It carries in data to memory in reservoir, then is transported on piece caching by memory, we remember processor from waking up everywhere herein
The time that reason required by task is wanted is t3, and processor is appointed from waking up to handling in the case of we can obtain 3 kinds in the above analysis
Required time relationship of being engaged in is t3>>t2>t1.
C, there is the probability of soft error；For Static RAM and dynamic RAM, since universe is penetrated
The presence of other radioactive elements, Static RAM and dynamic RAM in line and chip are it is possible that a fixed number
The soft error of amount, and Static RAM and the operating voltage of dynamic RAM are lower, Static RAM and
The probability that soft error occurs in dynamic RAM is bigger.On piece caching is by Static RAM reality in traditional server
Existing, afterbody caching is realized by embedded DRAM, due on piece caching or/and afterbody in situation 1
The operating voltage of caching reduces, so the probability that soft error occur on piece caching or/and afterbody caching will increase, note is at this time
On piece caches or/and afterbody caching the probability of soft error occurs for C1；On piece caching or/and afterbody are slow in situation 2
The voltage deposited is reduced holding voltage, therefore the probability ratio of soft error occur on piece caching or/and afterbody caching in situation 2
Situation 1 is big, and the note probability that soft error occur on piece caching or/and afterbody caching at this time is C2；Because on piece is slow in situation 3
It deposits or/and afterbody caching is closed, so we just do not discuss on piece caching or/and afterbody in situation 3 herein
There is the probability of soft error in caching.Situation 1 and 2 on piece of situation caching or/and afterbody can be obtained from us are analyzed above
There is the probability relationship of soft error in caching：C2>C1.
In current server application, server will not generally frequently enter situation 2 and situation 3, because while service
There are many lower power consumption of device, but due to the time that required by task is wanted from be waken up to handling of the processor in server too
It is long, largely reduce the performance of server.Simultaneously because the operating voltage of on piece caching or/and afterbody caching
It reduces, the probability that soft error occur on piece caching or/and afterbody caching increases, and can equally reduce the performance of server.
At present in the data center in order to solve heat dissipation problem when processor work, generally by processor chips
The heat dissipation of processor is accelerated in face plus fan, but no matter the processor in server is in any situation of the above DVFS
Under, fan is being worked with identical frequency always.The rotation of fan is the drive by motor, therefore motor is when driving fan
Certain heat can be brought, therefore for the cabinet of data center, air-conditioning is needed to cool down cabinet, and in cabinet
Air-conditioning can also distribute heat while cooling, therefore the entire room for placing cabinet is also required to cool down, and can thus make
The cost of data center increases, even if thus processor reduces the operating voltage and frequency of processor using DVFS technologies,
The power consumption of server is reduced to a certain extent, but can not further reduce the power consumption of data center.
Invention content
In view of above-mentioned technical problem, the present invention provides a kind of method that processor starts, and can be applied to be provided with processing list
On the server of meta structure (server of such as data center), it includes processor chips and Fei Yi that the processing unit structure, which has,
The MCP chips of the property lost memory, and the server presets super low-power consumption pattern, the method includes：
When the server exits the super low-power consumption pattern, the processor chips read the nonvolatile memory
And/or the data stored in being cached outside the on piece caching and/or described carry out start-up operation.
In the method started as a preferred embodiment, above-mentioned processor：
The processor unit structure further includes being cached outside memory, on piece caching and/or piece；And
When the server is operated in the super low-power consumption pattern, at least partly described processor chips and/or at least portion
Divide the memory and/or at least partly described nonvolatile memory and/or at least partly on piece caching and/or at least partly piece
Outer caching is placed in close pattern or standby mode.
As a preferred embodiment, the server for the method that above-mentioned processor starts further includes the outer large capacity of piece
Memory, and in the method：
When the server exits the super low-power consumption pattern,
If caching is closed outside the on piece caching or/and described, and the memory is also at closed state
When, the processor chips directly read the data of storage from the nonvolatile memory, to carry out the start-up operation；
If caching is opened outside on piece caching or/and described, and when the memory is closed, the place
While the data that reason device chip directly reads storage from the nonvolatile memory carry out the start-up operation, from described
Nonvolatile memory to the on piece cache or/and described outside cache in carry data；Or
The processor chips are cached from the nonvolatile memory to the on piece or/and described caching carrying outside
Data then recycle the processor chips to execute the data in being cached outside the on piece caching or/and described, to carry out
The start-up operation；
If caching is opened outside on piece caching or/and described, and when the memory is also turned on, the processor
Chip non-volatile is deposited from described while executing application carries out the start-up operation from the nonvolatile memory
Carried in reservoir data to the on piece cache or/and described outside in caching, while also being removed from mass storage outside piece
In destiny evidence to the memory；Or
The processor chips are first carried from described outer mass storage in data to the memory, then by described
Memory is transported to be cached outside on piece caching or/and described, last processor chips execute the on piece caching or/and
The data stored in being cached outside described, to carry out the start-up operation；Or
The processor chips data from be transported in the nonvolatile memory on piece caching or/and piece outside cache
While the middle progress start-up operation, carried in data to the memory from described outer mass storage；
If caching is closed outside on piece caching or/and described, and when the memory is opened, the processor core
Piece is first transported to data in the memory from described outer mass storage, then is transported to by the memory described non-volatile
After property memory, the processor chips execute data in the nonvolatile memory, to carry out the start-up operation.
In the method started as a preferred embodiment, above-mentioned processor：
The server is also preset with normal-power mode；And
When the server is in the normal-power mode, the processor and/or the memory and/or it is described it is non-easily
The property lost memory works normally.
As a preferred embodiment, the server for the method that above-mentioned processor starts further includes closing on the place
The fan for managing the setting of device chip, in the method：
When the server is converted from the normal power consumption module to the super low-power consumption pattern, the rotating speed of the fan
It reduces.
In the method started as a preferred embodiment, above-mentioned processor：
When the server operates in the super low-power consumption pattern, the rotating speed of the fan is greater than or equal to zero.
In the method started as a preferred embodiment, above-mentioned processor：
When the server is converted from the normal power consumption module to the super low-power consumption pattern, the on piece caching
Or/and described outside cache in data be saved in the nonvolatile memory, the data in the memory preserve to
In described outer mass storage.
As a preferred embodiment, the MCP chips for the method that above-mentioned processor starts further include temperature sensing
Device, for detecting the temperature of the nonvolatile memory in real time, in the method：
If the temperature of the nonvolatile memory is more than the warning temperature standard set in temperature sensor, the temperature
Sensor-triggered warning message is spent, data center receives and closed according to the warning message partly or entirely described non-volatile
Memory.
In the method started as a preferred embodiment, above-mentioned processor：
The temperature sensor is integrated in the nonvolatile memory.
In the method started as a preferred embodiment, above-mentioned processor：
The temperature sensor is the temperature sensor integrated in being cached outside the processor chips and/or described.
The invention discloses a kind of method that processor starts, utilize the processor in server directly from non-in this method
Volatile memory and/or on piece caching and/or piece outside cache in read data, be not required to from chip external memory carry data to
Memory, then be transported in caching by memory, to allow the processor in server to start immediately.When server is in ultralow
When power consumption mode, the speed of the fan being stacked in processor chips in server can be lowered or close, and reduce service
The power consumption of device, while when the temperature of nonvolatile memory is more than the warning temperature standard being arranged in temperature sensor, this is non-
Volatile memory will be closed the normal work for ensureing the server and entire data center, prevent from working as fan work
It is abnormal, the temperature of nonvolatile memory is excessively high and the case where lead to server and entire data center's delay machine.
Description of the drawings
By reading reference with figure below to being described in detail made by non-limiting embodiment, the present invention and its feature, shape
It will become more apparent with advantage.Identical label indicates identical part in whole figures.It can not paint proportionally
Drawing, it is preferred that emphasis is show the purport of the present invention.
Fig. 1 is the structural schematic diagram of the processing unit of traditional server；
Fig. 2 is the structural schematic diagram of the processing unit of server in the embodiment of the present application.
Specific implementation mode
With reference to figure, the present invention is further illustrated with specific embodiment, but not as the limit of the present invention
It is fixed.
The present invention proposes a kind of method that processor starts, and can be applied on the server for being provided with processing unit structure
(server of such as data center) includes referring to processing unit structure as shown in Fig. 2, above-mentioned：Processor chips；It is non-volatile
Property memory；Memory is connect with processor chips, and memory is also connect with chip external memory；When the processor chips enter
After super low-power consumption pattern, then when exiting super low-power consumption pattern, the processor chips are directly from the nonvolatile memory
Data are read, the processor in server is made to start immediately.When processor chips read the data stored in chip external memory, piece
The data are directed by memory in nonvolatile memory by external memory, when next time reads the data again, processor chips
Data are read directly in nonvolatile memory and are handled.Temperature sensor, the nonvolatile memory for detecting
Temperature, when temperature sensor detects that the temperature of nonvolatile memory is more than the warning temperature mark that sets in temperature sensor
On time, temperature sensor is sent in warning message to data center, to close nonvolatile memory by the data center.
Specifically, with reference to structure shown in Fig. 2,211 be processor chips, structure and current processor chips in figure
Structure is identical, i.e., it is by N (N>0) a processor composition, there are one local on pieces to cache for corresponding each processor, and locates
Data information interaction is carried out by piece shared buffer memory between reason device.Local on piece caching and on piece in processor chips is shared
Caching is realized by Static RAM (SRAM).212 in attached drawing 2 be caching (chip) outside piece, such as by being embedded in
The afterbody caching that formula dynamic RAM is realized, it is an independent chip, processing in this embodiment that piece caches outside
Device chip can carry out the operations such as digital independent by it.It is the present invention that the outer cache chip of piece is added in structure proposed by the present invention
A preferred embodiment, can not also include the outer cache chip of piece in structure proposed by the present invention.214 be non-volatile in figure
Memory.The outer cache chip 212 of processor chips 211, piece and nonvolatile memory 214 are encapsulated by MCP technologies in attached drawing 2
Together.The nonvolatile memory 214 should at least have following characteristics：
The storage density of nonvolatile memory 214 is very big, for example storage density can reach the order of magnitude of Gb or Tb.
For example 3D phase transition storages, the memory capacity of each chip can reach 128Gb or 256Gb, in the near future even more
Height, for example reach Tb magnitudes.For example, nonvolatile memory 214 can be the nonvolatile memory that planar technology makes
214, or the nonvolatile memory 214 made of three-dimensional perpendicular manufacture craft, it is preferred that the non-volatile memories
Device 214 is the nonvolatile memory 214 that three-dimensional perpendicular technique makes.
Nonvolatile memory 214 can be used for storing the most frequently used application program of specific user in certain time
Or/and the data of most frequent processing.Such as user X, most frequently used application program is to answer within a certain period of time
With program X_1, then application program X_1 is just stored in nonvolatile memory 214 by we, and for being used for for Y,
The data of most frequent processing are data Y_1 in certain time, then data Y_1 is just stored in nonvolatile memory by us
In 214.
213 be temperature sensor in attached drawing 2, and the temperature sensor 213 is mainly used to detect nonvolatile memory 214
Temperature, a warning temperature standard is set in the temperature sensor 213, when the temperature of nonvolatile memory 214 is more than
When the warning temperature standard set in the temperature sensor 213, the temperature sensor 213 will send out police to data center
When accusing information and can make corresponding processing, for example exceeding standard, nonvolatile memory 214 will be closed, and vice versa,
Although the reduced performance of server in this way ensure that the normal work of server, nonvolatile memory 214 is prevented
Temperature is excessively high and the case where leading to server and data center's delay machine.The temperature sensor 213 may be implemented non-volatile
In memory 214；If having temperature sensor in caching 212 outside processor chips 211 or/and piece, we can also answer
It uses and caches temperature sensor in 212 outside processor chips 211 or/and piece as the temperature sensor 213, at this time temperature
The temperature that sensor 213 detects comes from two aspects, on the one hand comes from and caches 212 outside processor chips 211 or/and piece
On the other hand the temperature of body comes from nonvolatile memory 214 and is conducted through the temperature come.When the temperature sensor 213 is real
When in present nonvolatile memory 214, it will be assumed that the warning temperature standard set in the temperature sensor 213 as T1,
When caching the temperature sensor in 212 outside 213 multiplex processor chip 211 of the temperature sensor or/and piece, it will be assumed that
The warning temperature standard being arranged in the temperature sensor 213 is T2.We discuss in terms of two below：
T2>T1.In this case, if the temperature of nonvolatile memory 214 is very high, T1 has been reached, but has not had
Reach T2, so if the temperature sensor 213 is realized in nonvolatile memory 214, then temperature sensor 213 is just
It can be sent a warning message to data center, while data center closes the nonvolatile memory 214, if the temperature passes
The temperature sensor in 212 is cached outside 213 multiplex processor chip 211 of sensor or/and piece, because of the temperature sensor 213
The temperature detected does not reach the warning temperature standard T2 being arranged in the temperature sensor 213, nonvolatile memory
214 always on and maintenance working conditions, continue to increase so as to cause its temperature, when the temperature sensor 213 detects
To temperature reach T2 when, nonvolatile memory 214 may cisco unity malfunction.
T2<T1.In this case, if the temperature of nonvolatile memory 214 is relatively low, processor chips 211 or/
It is relatively high with the temperature of caching 212 outside piece, reach T2, so if the realization of the temperature sensor 213 is deposited non-volatile
In reservoir 214, since the temperature that the temperature sensor 213 detects does not reach T1, so 214 meeting of nonvolatile memory
It works on；If caching the temperature sensing in 212 outside 213 multiplex processor chip 211 of the temperature sensor or/and piece
Device detects because the temperature of caching 212 is relatively high outside processor chips 211 or/and piece when the temperature sensor 213
When temperature reaches T2, then the temperature sensor 213 will be sent a warning message, while 214 meeting of nonvolatile memory
It is closed, but this obviously belongs to maloperation, because the temperature of nonvolatile memory 214 is relatively low at this time, need not be closed,
And if closing nonvolatile memory 214 at this time, the decline of processor performance can be caused.
Based on the above analysis, it is preferred that the temperature sensor 213 should be realized in nonvolatile memory 214.
Based on technical solution of the present invention, we define cached outside on piece caching or/and piece be closed as on piece caching or/
With piece outside cache part be closed or all be closed, on piece caching or/and piece outside cache be opened as on piece caching or/
It is partly opened with being cached outside piece or is all opened；Memory 4, which is closed, to be closed as 4 part of memory or is all closed
It closes, memory 4, which is opened, to be opened as 4 part of memory or be all opened；Processor is closed as processor part quilt
Close either all be closed processor be opened be opened as processor part or all be opened；It is non-volatile to deposit
It is that all or part of nonvolatile memory is closed or enters standby shape into standby mode that reservoir, which is closed either,
State, nonvolatile memory be opened or exit standby mode be all or part of nonvolatile memory be opened or
Person exits standby mode.On the basis of above-described embodiment, the application also describes a kind of super low-power consumption pattern, and this is ultralow
The pattern of power consumption should at least have following characteristics：
A, it caches and can thoroughly be closed outside on piece caching and/or piece, on piece caching is usually to be stored by static random
What device was realized, and the leakage current of Static RAM is bigger, therefore chip power-consumption can be made to increase, and it is by embedding to be cached outside piece
Enter the realization of formula dynamic RAM, dynamic RAM needs pair within a certain period of time in order to ensure the accuracy of data
Data are refreshed, since the refresh power consumption that dynamic RAM progress refresh operation is brought is also bigger, by thorough
It is cached outside caching and/or piece in Closure panel, the refresh power consumption cached outside the leakage current or/and piece to reduce on piece caching.
B, memory 4 can be closed thoroughly, because memory 4 is realized by dynamic RAM, and dynamic random
The power consumption that memory progress refresh operation is brought is very big, therefore by thoroughly closing memory 4, to reduce the refreshing of memory 4
Power consumption.
C, all processors can be switched off, can be by all processors in server under super low-power consumption pattern
All turn off, to save power consumption.
D, nonvolatile memory can be closed or enter standby mode.The storage density of nonvolatile memory is very
Greatly, many application program and data can be stored, when the processor in server needs to be waken up execution task, as long as calling out
Processor in awake server, processor directly can read data after being waken up from nonvolatile memory 214, from
And realize the function that server starts immediately, and without as be previously required to from mass storage outside piece (i.e. chip external memory,
It is stored with data) it carries in data to memory, then be transported in caching from memory, then executed by processor.
The super low-power consumption pattern of the server can be the individualism of features above, can also be several features above
Combination, such as on piece caching or/and piece outside cache be closed, memory is closed, and all processors are closed, it is non-easily
The property lost memory is closed or enters standby mode；Or cache outside on piece caching or/and piece and be closed, memory is closed
It closes, the voltage and frequency of processor work reduce, and nonvolatile memory normal work, processor is directly from non-volatile at this time
Instruction and data is read in memory.
Data in being cached outside on piece caching or/and piece should be saved in by server before entering super low-power consumption pattern
In nonvolatile memory 214, the data in memory should be also saved in outside piece in large capacity nonvolatile memory, because of place
When managing the data during device caches outside caching in performing chip or/and piece, the data in being cached outside on piece caching or/and piece may be
Through being updated, memory is also the same, in order to ensure the consistent of data, before caching is closed outside on piece caching or/and piece, and Ying Jiang
Data in being cached outside on piece caching or/and piece are saved in nonvolatile memory 214, should also be preserved the data in memory
Outside to piece memory could be closed in large capacity nonvolatile memory later.
Server has following several situations when exiting super low-power consumption pattern：
One, on piece caching or/and piece cache outside is still within closed state, and memory is still within closed state.This
In the case of, processor (low pressure low speed) directly reads instruction and data from nonvolatile memory, and such case is suitable for that
It is a little not need processor very high-performance and processor enters the application of super low-power consumption pattern again quickly after handle task, together
When the application program have stored in nonvolatile memory.
Two, on piece caching or/and piece cache outside is opened, and memory is still within closed state.Such case is suitable for that
Some or all of processor is needed to be in the application of high performance mode a bit, while this applies storage in nonvolatile memory
In.We illustrate son to illustrate below, it is assumed that the processor application program to be executed after being waken up is X, and application program X is stored in
In nonvolatile memory, we carry out executing application X there are two types of mode, and first method is processor directly from non-volatile
Property memory in read the data of instruction, while cache from nonvolatile memory on piece or/and piece outside caching carry data,
Then again by the data in being cached outside caching in processor performing chip or/and piece；Second method is first from non-volatile memories
Device carries data to outside on piece caching or/and piece on caching, then by caching outside caching in processor performing chip or/and piece
Data.When first method needs segment processor to be in high performance mode suitable for application program X, second method is suitable for
When application program X needs whole processors to be in high performance mode.
Three, on piece caching or/and piece cache outside is opened, and memory is opened.This kind of situation needs to handle suitable for those
Device is in the application of high performance mode.The application for this kind of situation of explanation that give some instances below.First example, processor are called out
Two application programs, respectively application program X and application program Y are executed after waking up, application program X is stored in non-volatile memories
In device, application program Y is stored in the outer mass storage of piece, and processing application program X and application program Y needs processor to be in
High performance mode, thus processor can first executing application X in the nonvolatile memory, while from non-volatile memories
It carries in device in being cached outside data on piece caching or/and piece, is carried in data to memory from mass storage outside piece, this
Three steps are carried out at the same time, and accelerate the startup speed immediately of system.Second example, processor will execute application after being waken up
Program Y, application program Y are stored in the outer mass storage of piece, and processing application program Y needs processor to be in high-performance mould
Formula, it is therefore desirable to carry in data to memory from mass storage outside piece, then be transported in caching by memory, finally by
Device is managed to execute.Third example, processor want executing application X and application program Y, application program X to be stored in after being waken up
In nonvolatile memory, application program Y is stored in the outer mass storage of piece, and processing application program X needs at processor
In high performance mode, thus data from be transported in nonvolatile memory on piece caching or/and piece outside cache in opened
While dynamic operation, application program Y is transported to from mass storage outside piece in memory.
Four, on piece caching or/and piece cache outside is closed, and memory is opened.Such case is stored suitable for application program
Outside piece in mass storage and processing application program do not need the application that processor is in high performance mode.We lift below
One example explanation.Processor wants executing application X, application program X to be stored in the outer mass storage of piece after being waken up,
But execute the application processor and need not be under high performance mode, therefore can first data, large capacity is deposited outside piece
Reservoir is transported in memory, then is transported in nonvolatile memory by memory, and processor executes in the nonvolatile memory
Application program X.
3 be the fan being arranged in processor chips in attached drawing 2, when server enters the super low-power consumption pattern, wind
The speed of fan will be reduced or even is closed.For example when all processors are closed, caching is closed outside on piece caching or/and piece
It closes, memory is closed, when nonvolatile memory is all closed or enters standby mode, at this moment because of all processors
Task is not reprocessed, caches outside on piece caching or piece and is closed, so we can close fan, to further
Save power consumption.When segment processor is closed, caching part outside on piece caching or/and piece is closed, and memory is partially closed, non-
When the operating voltage of volatile memory is normal voltage, we can reduce the speed of fan, and power consumption is saved to reach
Purpose, in both cases, the speed of fan reduces or fan is closed, then driving the power consumption of the motor of fan rotation
It will reduce, the temperature of data center's cabinet will reduce, and will also be dropped accordingly to the power consumption of the air-conditioning consumption of cabinet cooling
It is low, while the temperature in the entire room for placing cabinet can also reduce, the work(consumed to the air-conditioning for the room cooling for placing cabinet
Consumption can also reduce, that is to say, that reduce the cost of data center.Other situations are similar, and which is not described herein again.
We are waken up from power consumption, processor to the occurrence probability three for executing time and soft error that required by task is wanted below
A aspect to super low-power consumption pattern server and traditional server compare：
Power consumption.Although on the one hand traditional server reduces server to a certain extent using DVFS technologies
Power consumption, but no matter server is in which kind of pattern of DVFS in the following, fan is rotating always, the rotation of fan is by motor
Drive, motor also brings along certain heat when driving fan, therefore for the cabinet of data center, need air-conditioning into
Row cooling, and the air-conditioning in cabinet can also distribute heat while cooling, therefore the entire room for putting cabinet is also required to carry out
Cooling, can thus be such that the cost of data center increases, even if server by utilizing DVFS technologies reduce operating voltage and frequency,
The power consumption of server is reduced to a certain extent, but can not further reduce the power consumption of data center.And for this hair
For the server with super low-power consumption pattern of bright proposition, when server enters super low-power consumption pattern, fan can be reduced
Speed be even switched off fan, the power consumption of server is largely further reduced in this way, to make data center
Cost reduction.On the other hand, after the processor in traditional server is closed, when task to be handled, processor needs
It carries in data to memory from mass storage outside piece, then is transported on piece caching by memory, data, which are carried, to be needed to disappear
The a large amount of time is consumed, so traditional server in order to ensure the performance of server, will not frequently enter the situation in DVFS patterns
Two and situation three, also just say the limited power consumption that traditional server utilizes DVFS technologies to reduce, and have using proposed by the present invention
For the server of super low-power consumption pattern, server can frequently enter super low-power consumption pattern, because of the processor in server
After being closed, when task to be handled, processor directly reads data from nonvolatile memory after being waken up, and does not have to picture
Traditional server needs to carry data like that.In this way using the server proposed by the present invention with super low-power consumption pattern come
It says, server can frequently enter super low-power consumption pattern, can save a large amount of power consumption, but also can ensure the property of server
Energy.Using the server proposed by the present invention with super low-power consumption pattern, for opposite traditional server, can significantly drop
The power consumption of low server, while reducing the cost of data center.
Processor is waken up the time that processing required by task is wanted.After processor in traditional server is closed, when wanting
When processing task, processor needs to carry in data to memory from mass storage outside piece after being waken up, then is removed by memory
It transports on piece caching, data carrying needs to consume a large amount of time, that is to say, that processor is held from starting to wake up to processor
The corresponding task of row will devote a tremendous amount of time, and the time of the response task of server is elongated, thus can be to a certain degree
The upper performance for reducing server.For the server proposed by the present invention with super low-power consumption pattern, server is closed
Afterwards, when task to be handled, processor can directly read data after being waken up from nonvolatile memory, that is to say, that can
Immediately to start, and do not have to need to carry in data to memory from mass storage outside piece as traditional server, then by
Memory is transported on piece caching.Using the server proposed by the present invention with super low-power consumption pattern, because in server
Processor can start immediately, therefore server can frequently enter super low-power consumption pattern, and the performance of server is not yet
It is affected.
The probability that soft error occurs.On piece caching is realized by Static RAM in traditional server, slow outside piece
Deposit is to be realized by embedded DRAM, therefore work as the work cached outside using DVFS technologies reduction on piece caching and piece
When voltage, the probability for soft error occur is cached outside on piece caching and piece and is increased.And it utilizes proposed by the present invention with super low-power consumption
Server for, after entering super low-power consumption pattern, being cached outside on piece caching and piece can be with Close All, therefore on piece caches
The problem of soft error would not occur for caching outside with piece, and nonvolatile memory 214 is radiation-resistant, so non-volatile deposit
The probability that soft error occurs in reservoir will not increase.
In conclusion the invention discloses a kind of method that processor starts, pass through the processing in server in this method
Nonvolatile memory and temperature sensor are added in device structure, and server is provided with super low-power consumption pattern (i.e. processor general
Be closed, cache and be also turned off outside on piece caching or/and piece) when, nonvolatile memory may also can power down, but it is non-volatile
After a power failure, being stored in data therein will not lose property memory, therefore when server exits above-mentioned super low-power consumption pattern
Afterwards, when the processor in server is waken up again, which can directly read data from nonvolatile memory, without
It is transported in caching to memory, then by memory with data are carried from mass storage outside piece, to make the place in server
Reason device can start immediately.Simultaneously when server is in the super low-power consumption pattern, closing in processor chips in server
Processor setting fan speed can be lowered even fan can be closed, to further decrease the work(of server
Consumption, while temperature sensor is utilized, to detect the temperature of nonvolatile memory, when the temperature of nonvolatile memory is more than temperature
When the warning temperature standard being arranged in degree sensor, which will be closed to ensure the server and whole
The normal work of a data center is prevented when fan work is abnormal, and the temperature of nonvolatile memory is excessively high and leads to server
And the case where entire data center's delay machine.
It should be appreciated by those skilled in the art that those skilled in the art are combining the prior art and above-described embodiment can be with
Realize the change case, this will not be repeated here.Such change case does not affect the essence of the present invention, not superfluous herein
It states.
Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited in above-mentioned
Particular implementation, wherein the equipment and structure be not described in detail to the greatest extent are construed as giving reality with the common mode in this field
It applies；Any technical person familiar with the field, without departing from the scope of the technical proposal of the invention, all using the disclosure above
Methods and technical content many possible changes and modifications are made to technical solution of the present invention, or be revised as equivalent variations etc.
Embodiment is imitated, this is not affected the essence of the present invention.Therefore, every content without departing from technical solution of the present invention, foundation
The technical spirit any simple modifications, equivalents, and modifications made to the above embodiment of the present invention, still fall within the present invention
In the range of technical solution protection.
Claims (8)
1. a kind of method that processor starts, which is characterized in that described applied to being provided on the server of processing unit structure
Processing unit structure is with the MCP chips for including processor chips and nonvolatile memory, and the processor unit structure is also
Including being cached outside memory, on piece caching and/or piece, and the server further includes the outer mass storage of piece, and is preset with super
Low-power consumption mode, the method includes：
When the server is operated in the super low-power consumption pattern, at least partly described processor chips and/or at least partly institute
State memory and/or at least partly described nonvolatile memory and/or at least partly described on piece caching and/or at least partly institute
It states to cache outside piece and is placed in close pattern or standby mode；
When the server exits the super low-power consumption pattern, the processor chips read the nonvolatile memory and/
Or the data stored in being cached outside the on piece caching and/or described carry out start-up operation；
Wherein, when the server exits the super low-power consumption pattern,
If caching is closed outside on piece caching or/and described, and when the memory is also at closed state, institute
The data that processor chips directly read storage from the nonvolatile memory are stated, to carry out the start-up operation；
If caching is opened outside on piece caching or/and described, and when the memory is closed, the processor
Chip directly read from the nonvolatile memory storage data carry out the start-up operation while, from it is described it is non-easily
Lose property memory to the on piece cache or/and described outside caching in carry data；Or
The processor chips are cached from the nonvolatile memory to the on piece or/and described caches carrying number outside
According to then the processor chips execute the data in being cached outside the on piece caching or/and described, to carry out the startup
Operation；
If caching is opened outside on piece caching or/and described, and when the memory is also turned on, the processor chips
While executing application carries out the start-up operation from the nonvolatile memory, from the nonvolatile memory
Middle carrying data to the on piece cache or/and described outside cache, while number is also carried from mass storage outside piece
According to in the memory；Or
The processor chips are first carried from described outer mass storage in data to the memory, then by the memory
It is transported in being cached outside on piece caching or/and described, last processor chips execute the on piece caching or/and described
The data stored in being cached outside piece, to carry out the start-up operation；Or
The processor chips data from be transported in the nonvolatile memory on piece caching or/and piece outside cache in into
While the row start-up operation, carried in data to the memory from described outer mass storage；
If caching is closed outside on piece caching or/and described, and when the memory is opened, the processor chips are first
Data are transported to from described outer mass storage in the memory, then described non-volatile deposit is transported to by the memory
After reservoir, the processor chips execute data in the nonvolatile memory, to carry out the start-up operation.
2. the method that processor as described in claim 1 starts, which is characterized in that in the method：
The server is also preset with normal-power mode；And
When the server is in the normal-power mode, the processor and/or the memory and/or described non-volatile
Memory works normally.
3. the method that processor as claimed in claim 2 starts, which is characterized in that the server further includes closing on the place
The fan for managing the setting of device chip, in the method：
When the server is converted from the normal power consumption module to the super low-power consumption pattern, the rotating speed of the fan drops
It is low.
4. the method that processor as claimed in claim 3 starts, which is characterized in that in the method：
When the server operates in the super low-power consumption pattern, the rotating speed of the fan is greater than or equal to zero.
5. the method that processor as claimed in claim 2 starts, which is characterized in that in the method：
When the server is converted from the normal power consumption module to the super low-power consumption pattern, on piece caching or/and
Data in being cached outside described are saved in the nonvolatile memory, and the data in the memory are preserved to described
In outer mass storage.
6. the method that processor as claimed in claim 2 starts, which is characterized in that the MCP chips further include temperature sensing
Device, for detecting the temperature of the nonvolatile memory in real time, in the method：
If the temperature of the nonvolatile memory is more than the warning temperature standard set in the temperature sensor, the temperature
Sensor-triggered warning message is spent, data center receives and closed according to the warning message partly or entirely described non-volatile
Memory.
7. the method that processor as claimed in claim 6 starts, which is characterized in that the temperature sensor is integrated in described non-
In volatile memory.
8. the method that processor as claimed in claim 6 starts, which is characterized in that the temperature sensor is the processor
Chip and/or the described temperature sensor integrated in caching outside.
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| CN109272972B (en) * | 2018-11-30 | 2021-04-09 | 北京集创北方科技股份有限公司 | Display device and control method thereof |
| CN110267260B (en) * | 2019-06-17 | 2022-03-01 | Oppo广东移动通信有限公司 | Flashing method, device, terminal and computer readable storage medium |
| CN112363766A (en) * | 2020-11-10 | 2021-02-12 | 北京百瑞互联技术有限公司 | Integrated circuit ultra-low power memory content retention system, method and medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1818887A (en) * | 2006-03-16 | 2006-08-16 | 浙江大学 | Built-in file system realization based on SRAM |
| CN102681447A (en) * | 2011-03-16 | 2012-09-19 | 上海华虹集成电路有限责任公司 | Method and microprocessor for reducing static and dynamic power consumption of multi-pin microcontroller |
| CN102866934A (en) * | 2011-07-05 | 2013-01-09 | 中国科学院上海微系统与信息技术研究所 | Dormancy and wake-up system for embedded device based on non-volatile random access memory |
| CN103064503A (en) * | 2012-12-24 | 2013-04-24 | 上海新储集成电路有限公司 | System on chip and register thereof |
| CN103593324A (en) * | 2013-11-12 | 2014-02-19 | 上海新储集成电路有限公司 | Quick-start and low-power-consumption computer system-on-chip with self-learning function |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US8977704B2 (en) * | 2011-12-29 | 2015-03-10 | Nokia Corporation | Method and apparatus for flexible caching of delivered media |
-
2015
- 2015-07-24 CN CN201510444020.2A patent/CN105094827B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1818887A (en) * | 2006-03-16 | 2006-08-16 | 浙江大学 | Built-in file system realization based on SRAM |
| CN102681447A (en) * | 2011-03-16 | 2012-09-19 | 上海华虹集成电路有限责任公司 | Method and microprocessor for reducing static and dynamic power consumption of multi-pin microcontroller |
| CN102866934A (en) * | 2011-07-05 | 2013-01-09 | 中国科学院上海微系统与信息技术研究所 | Dormancy and wake-up system for embedded device based on non-volatile random access memory |
| CN103064503A (en) * | 2012-12-24 | 2013-04-24 | 上海新储集成电路有限公司 | System on chip and register thereof |
| CN103593324A (en) * | 2013-11-12 | 2014-02-19 | 上海新储集成电路有限公司 | Quick-start and low-power-consumption computer system-on-chip with self-learning function |
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